Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1609349784	1606234480	0	0
CheckNGreaterZero_A	4116	4116	0	0
GntImpliesReady_A	1609349784	400911167	0	0
GntImpliesValid_A	1609349784	400911167	0	0
GrantKnown_A	1609349784	1606234480	0	0
IdxKnown_A	1609349784	1606234480	0	0
IndexIsCorrect_A	1609349784	400911167	0	0
NoReadyValidNoGrant_A	1609349784	177498973	0	0
Priority_A	1609349784	424594784	0	0
ReadyAndValidImplyGrant_A	1609349784	400911167	0	0
ReqAndReadyImplyGrant_A	1609349784	400911167	0	0
ReqImpliesValid_A	1609349784	424594784	0	0
ValidKnown_A	1609349784	1606234480	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	1606234480	0	0
T1	5260	4908	0	0
T2	13440	11092	0	0
T3	10768	10408	0	0
T4	13688	13352	0	0
T5	9936	9448	0	0
T6	11496	10924	0	0
T7	468780	468752	0	0
T8	287324	286944	0	0
T14	3352	3124	0	0
T21	6968	6444	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4116	4116	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T14	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	400911167	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137230	0	0
T9	2146	10	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	400911167	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137230	0	0
T9	2146	10	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	1606234480	0	0
T1	5260	4908	0	0
T2	13440	11092	0	0
T3	10768	10408	0	0
T4	13688	13352	0	0
T5	9936	9448	0	0
T6	11496	10924	0	0
T7	468780	468752	0	0
T8	287324	286944	0	0
T14	3352	3124	0	0
T21	6968	6444	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	1606234480	0	0
T1	5260	4908	0	0
T2	13440	11092	0	0
T3	10768	10408	0	0
T4	13688	13352	0	0
T5	9936	9448	0	0
T6	11496	10924	0	0
T7	468780	468752	0	0
T8	287324	286944	0	0
T14	3352	3124	0	0
T21	6968	6444	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	400911167	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137230	0	0
T9	2146	10	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	177498973	0	0
T1	2630	256	0	0
T2	6720	1358	0	0
T3	10768	378	0	0
T4	13688	294	0	0
T5	9936	930	0	0
T6	11496	988	0	0
T7	468780	2128	0	0
T8	287324	1220	0	0
T9	2146	12	0	0
T14	3352	256	0	0
T18	0	1052160	0	0
T21	6968	512	0	0
T25	0	32	0	0
T41	0	84	0	0
T56	1642	166	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	424594784	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137328	0	0
T9	2146	14	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	400911167	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137230	0	0
T9	2146	10	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	400911167	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137230	0	0
T9	2146	10	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	424594784	0	0
T1	2630	64	0	0
T2	6720	340	0	0
T3	10768	144	0	0
T4	13688	2056	0	0
T5	9936	992	0	0
T6	11496	436	0	0
T7	468780	1501090	0	0
T8	287324	137328	0	0
T9	2146	14	0	0
T14	3352	584	0	0
T21	6968	132	0	0
T25	0	16	0	0
T41	0	16678	0	0
T56	1642	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609349784	1606234480	0	0
T1	5260	4908	0	0
T2	13440	11092	0	0
T3	10768	10408	0	0
T4	13688	13352	0	0
T5	9936	9448	0	0
T6	11496	10924	0	0
T7	468780	468752	0	0
T8	287324	286944	0	0
T14	3352	3124	0	0
T21	6968	6444	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402337446	401558620	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	402337446	103861525	0	0
GntImpliesValid_A	402337446	103861525	0	0
GrantKnown_A	402337446	401558620	0	0
IdxKnown_A	402337446	401558620	0	0
IndexIsCorrect_A	402337446	103861525	0	0
NoReadyValidNoGrant_A	402337446	45587065	0	0
Priority_A	402337446	109744098	0	0
ReadyAndValidImplyGrant_A	402337446	103861525	0	0
ReqAndReadyImplyGrant_A	402337446	103861525	0	0
ReqImpliesValid_A	402337446	109744098	0	0
ValidKnown_A	402337446	401558620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	45587065	0	0
T1	1315	128	0	0
T2	3360	679	0	0
T3	2692	152	0	0
T4	3422	147	0	0
T5	2484	436	0	0
T6	2874	462	0	0
T7	117195	1031	0	0
T8	71831	381	0	0
T14	838	128	0	0
T21	1742	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	109744098	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67759	0	0
T14	838	292	0	0
T21	1742	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	109744098	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67759	0	0
T14	838	292	0	0
T21	1742	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402337446	401558620	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	402337446	103861525	0	0
GntImpliesValid_A	402337446	103861525	0	0
GrantKnown_A	402337446	401558620	0	0
IdxKnown_A	402337446	401558620	0	0
IndexIsCorrect_A	402337446	103861525	0	0
NoReadyValidNoGrant_A	402337446	45587065	0	0
Priority_A	402337446	109744098	0	0
ReadyAndValidImplyGrant_A	402337446	103861525	0	0
ReqAndReadyImplyGrant_A	402337446	103861525	0	0
ReqImpliesValid_A	402337446	109744098	0	0
ValidKnown_A	402337446	401558620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	45587065	0	0
T1	1315	128	0	0
T2	3360	679	0	0
T3	2692	152	0	0
T4	3422	147	0	0
T5	2484	436	0	0
T6	2874	462	0	0
T7	117195	1031	0	0
T8	71831	381	0	0
T14	838	128	0	0
T21	1742	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	109744098	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67759	0	0
T14	838	292	0	0
T21	1742	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	103861525	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67718	0	0
T14	838	292	0	0
T21	1742	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	109744098	0	0
T1	1315	32	0	0
T2	3360	170	0	0
T3	2692	48	0	0
T4	3422	1028	0	0
T5	2484	488	0	0
T6	2874	210	0	0
T7	117195	732362	0	0
T8	71831	67759	0	0
T14	838	292	0	0
T21	1742	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T21
1	0	Covered	T5,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T3,T5,T21
1	1	Covered	T5,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T3,T5,T21

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402337446	401558620	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	402337446	96594131	0	0
GntImpliesValid_A	402337446	96594131	0	0
GrantKnown_A	402337446	401558620	0	0
IdxKnown_A	402337446	401558620	0	0
IndexIsCorrect_A	402337446	96594131	0	0
NoReadyValidNoGrant_A	402337446	43162452	0	0
Priority_A	402337446	102553336	0	0
ReadyAndValidImplyGrant_A	402337446	96594131	0	0
ReqAndReadyImplyGrant_A	402337446	96594131	0	0
ReqImpliesValid_A	402337446	102553336	0	0
ValidKnown_A	402337446	401558620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96594131	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96594131	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96594131	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	43162452	0	0
T3	2692	37	0	0
T4	3422	0	0	0
T5	2484	29	0	0
T6	2874	32	0	0
T7	117195	33	0	0
T8	71831	229	0	0
T9	1073	6	0	0
T14	838	0	0	0
T18	0	526080	0	0
T21	1742	0	0	0
T25	0	16	0	0
T41	0	42	0	0
T56	821	83	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	102553336	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	905	0	0
T9	1073	7	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96594131	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96594131	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	102553336	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	905	0	0
T9	1073	7	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T21
1	0	Covered	T5,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T3,T5,T21
1	1	Covered	T5,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T3,T5,T21

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402337446	401558620	0	0
CheckNGreaterZero_A	1029	1029	0	0
GntImpliesReady_A	402337446	96593986	0	0
GntImpliesValid_A	402337446	96593986	0	0
GrantKnown_A	402337446	401558620	0	0
IdxKnown_A	402337446	401558620	0	0
IndexIsCorrect_A	402337446	96593986	0	0
NoReadyValidNoGrant_A	402337446	43162391	0	0
Priority_A	402337446	102553252	0	0
ReadyAndValidImplyGrant_A	402337446	96593986	0	0
ReqAndReadyImplyGrant_A	402337446	96593986	0	0
ReqImpliesValid_A	402337446	102553252	0	0
ValidKnown_A	402337446	401558620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96593986	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96593986	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96593986	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	43162391	0	0
T3	2692	37	0	0
T4	3422	0	0	0
T5	2484	29	0	0
T6	2874	32	0	0
T7	117195	33	0	0
T8	71831	229	0	0
T9	1073	6	0	0
T14	838	0	0	0
T18	0	526080	0	0
T21	1742	0	0	0
T25	0	16	0	0
T41	0	42	0	0
T56	821	83	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	102553252	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	905	0	0
T9	1073	7	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96593986	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	96593986	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	897	0	0
T9	1073	5	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	102553252	0	0
T3	2692	24	0	0
T4	3422	0	0	0
T5	2484	8	0	0
T6	2874	8	0	0
T7	117195	18183	0	0
T8	71831	905	0	0
T9	1073	7	0	0
T14	838	0	0	0
T21	1742	2	0	0
T25	0	8	0	0
T41	0	8339	0	0
T56	821	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402337446	401558620	0	0
T1	1315	1227	0	0
T2	3360	2773	0	0
T3	2692	2602	0	0
T4	3422	3338	0	0
T5	2484	2362	0	0
T6	2874	2731	0	0
T7	117195	117188	0	0
T8	71831	71736	0	0
T14	838	781	0	0
T21	1742	1611	0	0