Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_arbiter_tree_dup
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 95.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb 76.67 90.00 40.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc 80.00 100.00 40.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb 96.67 90.00 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.67 90.00 40.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.95 75.93 91.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.68 100.00 90.57 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[1].u_req_buf 100.00 100.00


Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 40.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 100.00 94.51 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.55 100.00 89.66 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_rr_arbiter.u_arb 97.86 100.00 97.67 100.00 93.75
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_rr_arbiter.u_arb 97.86 100.00 97.67 100.00 93.75
gen_input_bufs[1].u_req_buf 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 90.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.98 75.93 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.74 100.00 85.85 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[1].u_req_buf 100.00 100.00


Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.80 100.00 93.46 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.55 100.00 89.66 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_rr_arbiter.u_arb 95.99 100.00 90.20 100.00 93.75
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_rr_arbiter.u_arb 97.46 100.00 96.08 100.00 93.75
gen_input_bufs[1].u_req_buf 100.00 100.00

Line Coverage for Module : prim_arbiter_tree_dup ( parameter N=2,DW=16,EnDataPort=1,FixedArb=0,IdxW=1,ArbInstances=2 + N=2,DW=129,EnDataPort=1,FixedArb=0,IdxW=1,ArbInstances=2 )
Line Coverage for Module self-instances :
SCORELINE
80.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 1 1
124 1 1
125 1 1
126 1 1
132 1 1
137 1 1
139 1 1
140 1 1
142 1 1
146 1 1

Line Coverage for Module : prim_arbiter_tree_dup ( parameter N=2,DW=2,EnDataPort=0,FixedArb=1,IdxW=1,ArbInstances=2 )
Line Coverage for Module self-instances :
SCORELINE
76.67 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

SCORELINE
96.67 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

Line No.TotalCoveredPercent
TOTAL10990.00
CONT_ASSIGN10000
CONT_ASSIGN10000
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN126100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
123 1 1
124 1 1
125 1 1
126 0 1
132 1 1
137 1 1
139 1 1
140 1 1
142 1 1
146 1 1

Cond Coverage for Module : prim_arbiter_tree_dup
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT72,T74,T75 

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT72,T74,T75
10CoveredT72,T74,T75
Branch Coverage for Module : prim_arbiter_tree_dup
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
Line No.TotalCoveredPercent
TOTAL10990.00
CONT_ASSIGN10000
CONT_ASSIGN10000
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN126100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
123 1 1
124 1 1
125 1 1
126 0 1
132 1 1
137 1 1
139 1 1
140 1 1
142 1 1
146 1 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc
Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 1 1
124 1 1
125 1 1
126 1 1
132 1 1
137 1 1
139 1 1
140 1 1
142 1 1
146 1 1

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
Line No.TotalCoveredPercent
TOTAL10990.00
CONT_ASSIGN10000
CONT_ASSIGN10000
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN126100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
123 1 1
124 1 1
125 1 1
126 0 1
132 1 1
137 1 1
139 1 1
140 1 1
142 1 1
146 1 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT74,T75,T76 

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT74,T75,T76
10CoveredT74,T75,T76
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op
Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 1 1
124 1 1
125 1 1
126 1 1
132 1 1
137 1 1
139 1 1
140 1 1
142 1 1
146 1 1

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT72,T73 

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT72,T73
10CoveredT72,T73
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree_dup.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%