Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.57 96.63 84.91 100.00 91.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.96 97.55 92.78 96.90 100.00 96.58 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.22 97.67 88.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 97.56 100.00 93.85 95.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.59 99.17 93.26 100.00 99.28 96.23
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.40 98.88 95.28 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.88 97.79 93.84 100.00 100.00 97.72 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.22 97.67 88.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.65 100.00 95.38 100.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.64 99.17 93.51 100.00 99.28 96.23
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS2286583.33
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 0 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions10610296.23
Logical10610296.23
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11CoveredT87,T220,T233

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT87,T220,T233

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT3,T7,T8
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT3,T7,T8
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T8,T20
110Not Covered
111CoveredT3,T7,T8

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT7,T8,T20
101CoveredT3,T7,T8
110CoveredT68,T69,T70
111CoveredT3,T7,T8

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT60
10CoveredT3,T7,T8
11CoveredT3,T7,T8

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11CoveredT3,T7,T8

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT110,T111
10CoveredT1,T2,T3
11CoveredT3,T7,T8

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11CoveredT7,T8,T9

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T4,T20
11CoveredT1,T3,T4

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT68,T69,T70
10CoveredT234,T235

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT234,T235

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11CoveredT68,T69,T70

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T4,T20
10CoveredT1,T2,T3
11CoveredT1,T4,T20

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T28,T29
10CoveredT1,T4,T20

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT220

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT220
11CoveredT220

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T7,T8
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT220

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT16,T17,T18

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T8

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T8

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T8

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T8

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T4,T20
StCtrlProg 338 Covered T1,T3,T4
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T13,T14,T15
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T4,T20
StCtrlProg->StIdle 358 Covered T1,T3,T4
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T1,T4,T20
StIdle->StCtrlProg 338 Covered T1,T3,T4
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T13,T14,T15



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 2 100.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 3 75.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T220
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T7,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T87,T220,T233
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T220
0 0 0 Covered T3,T7,T8


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T13,T14,T15
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T3,T4
StIdle 0 0 0 1 - - - Covered T1,T4,T20
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T3,T4
StCtrlProg - - - - - 0 - Covered T1,T3,T4
StCtrl - - - - - - 1 Covered T1,T4,T20
StCtrl - - - - - - 0 Covered T1,T4,T20
StDisable - - - - - - - Covered T13,T14,T15
default - - - - - - - Covered T16,T17,T18


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 794870462 2674202 0 0
CtrlPrio_A 794870462 2674197 0 0
HostTransIdleChk_A 794870462 44820402 0 0
NoRemainder_A 2058 2058 0 0
OneHotReqs_A 794870462 793273646 0 0
Pow2Multiple_A 2058 2058 0 0
RdTxnCheck_A 794496748 792899932 0 0
u_state_regs_A 794870462 793273646 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794870462 2674202 0 0
T5 4876 0 0 0
T7 131296 4327 0 0
T8 246980 5572 0 0
T9 0 83 0 0
T14 2022 0 0 0
T19 5746 0 0 0
T20 17186 0 0 0
T25 0 2375 0 0
T28 0 84 0 0
T31 16320 0 0 0
T32 3678 0 0 0
T42 0 89301 0 0
T43 0 4567 0 0
T47 963466 0 0 0
T56 2592 0 0 0
T65 0 14570 0 0
T82 0 99 0 0
T144 0 1545 0 0
T185 0 84 0 0
T209 0 5187 0 0
T219 0 2646 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794870462 2674197 0 0
T5 4876 0 0 0
T7 131296 4327 0 0
T8 246980 5572 0 0
T9 0 83 0 0
T14 2022 0 0 0
T19 5746 0 0 0
T20 17186 0 0 0
T25 0 2375 0 0
T28 0 84 0 0
T31 16320 0 0 0
T32 3678 0 0 0
T42 0 89301 0 0
T43 0 4567 0 0
T47 963466 0 0 0
T56 2592 0 0 0
T65 0 14570 0 0
T82 0 99 0 0
T144 0 1545 0 0
T185 0 84 0 0
T209 0 5187 0 0
T219 0 2646 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794870462 44820402 0 0
T3 6036 44 0 0
T4 195602 0 0 0
T5 0 32 0 0
T7 131296 60287 0 0
T8 246980 56506 0 0
T13 6302 0 0 0
T14 2022 0 0 0
T16 0 50 0 0
T19 5746 0 0 0
T20 17186 55 0 0
T23 0 525 0 0
T31 0 50 0 0
T32 3678 8 0 0
T47 963466 0 0 0
T62 0 24 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2058 2058 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794870462 793273646 0 0
T1 436022 410434 0 0
T2 2188 1778 0 0
T3 6036 5716 0 0
T4 195602 195420 0 0
T7 131296 131152 0 0
T8 246980 246828 0 0
T13 6302 4896 0 0
T14 2022 1890 0 0
T19 5746 5610 0 0
T20 17186 16880 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2058 2058 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794496748 792899932 0 0
T1 436022 410434 0 0
T2 2188 1778 0 0
T3 6036 5716 0 0
T4 195602 195420 0 0
T7 131296 131152 0 0
T8 246980 246828 0 0
T13 6302 4896 0 0
T14 2022 1890 0 0
T19 5746 5610 0 0
T20 17186 16880 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794870462 793273646 0 0
T1 436022 410434 0 0
T2 2188 1778 0 0
T3 6036 5716 0 0
T4 195602 195420 0 0
T7 131296 131152 0 0
T8 246980 246828 0 0
T13 6302 4896 0 0
T14 2022 1890 0 0
T19 5746 5610 0 0
T20 17186 16880 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL898696.63
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS2024375.00
ALWAYS2146583.33
ALWAYS2286583.33
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 0 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 0 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 0 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1069084.91
Logical1069084.91
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT3,T4,T7
10CoveredT3,T7,T8
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT3,T7,T8
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT3,T4,T7
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT3,T7,T8
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T8,T31
110Not Covered
111CoveredT3,T7,T8

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT7,T8,T31
101CoveredT3,T7,T8
110Not Covered
111CoveredT3,T7,T8

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T7,T8
11CoveredT3,T7,T8

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT3,T4,T7
10CoveredT3,T7,T8
11CoveredT3,T7,T8

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT110,T111
10CoveredT3,T4,T7
11CoveredT3,T7,T8

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT3,T4,T7
11CoveredT7,T8,T65

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T7

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT4,T20,T31
11CoveredT3,T4,T8

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT3,T4,T7
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T7

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT3,T4,T7
11CoveredT3,T4,T8

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T4,T20
10CoveredT3,T4,T7
11CoveredT4,T20,T31

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T28,T29
10CoveredT1,T4,T20

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT3,T7,T8
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T8
11CoveredT3,T4,T7

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T7,T8
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT16,T17,T18

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T7,T8
10CoveredT3,T8,T33

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T7,T8
10CoveredT3,T8,T33

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T8,T33

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T8,T33

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T4,T20,T31
StCtrlProg 338 Covered T3,T4,T8
StCtrlRead 336 Covered T3,T4,T7
StDisable 334 Covered T13,T14,T15
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T4,T20,T31
StCtrlProg->StIdle 358 Covered T3,T4,T8
StCtrlRead->StIdle 348 Covered T3,T4,T7
StIdle->StCtrl 340 Covered T4,T20,T31
StIdle->StCtrlProg 338 Covered T3,T4,T8
StIdle->StCtrlRead 336 Covered T3,T4,T7
StIdle->StDisable 334 Covered T13,T14,T15



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 42 91.30
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 2 66.67
IF 214 4 3 75.00
IF 228 4 3 75.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T3,T8,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T3,T8,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T4,T7
0 0 1 Covered T7,T8,T65
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T3,T7,T8


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T3,T4,T7


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T13,T14,T15
StIdle 0 1 - - - - - Covered T3,T4,T7
StIdle 0 0 1 - - - - Covered T3,T4,T8
StIdle 0 0 0 1 - - - Covered T4,T20,T31
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T3,T4,T7
StCtrlRead - - - - 0 - - Covered T3,T4,T7
StCtrlProg - - - - - 1 - Covered T3,T4,T8
StCtrlProg - - - - - 0 - Covered T3,T4,T8
StCtrl - - - - - - 1 Covered T4,T20,T31
StCtrl - - - - - - 0 Covered T4,T20,T31
StDisable - - - - - - - Covered T13,T14,T15
default - - - - - - - Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 397435231 1165822 0 0
CtrlPrio_A 397435231 1165822 0 0
HostTransIdleChk_A 397435231 22363386 0 0
NoRemainder_A 1029 1029 0 0
OneHotReqs_A 397435231 396636823 0 0
Pow2Multiple_A 1029 1029 0 0
RdTxnCheck_A 397248374 396449966 0 0
u_state_regs_A 397435231 396636823 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 1165822 0 0
T5 2438 0 0 0
T7 65648 2469 0 0
T8 123490 4968 0 0
T14 1011 0 0 0
T19 2873 0 0 0
T20 8593 0 0 0
T25 0 841 0 0
T31 8160 0 0 0
T32 1839 0 0 0
T42 0 29252 0 0
T43 0 4567 0 0
T47 481733 0 0 0
T56 1296 0 0 0
T65 0 4280 0 0
T82 0 86 0 0
T144 0 1545 0 0
T209 0 5187 0 0
T219 0 656 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 1165822 0 0
T5 2438 0 0 0
T7 65648 2469 0 0
T8 123490 4968 0 0
T14 1011 0 0 0
T19 2873 0 0 0
T20 8593 0 0 0
T25 0 841 0 0
T31 8160 0 0 0
T32 1839 0 0 0
T42 0 29252 0 0
T43 0 4567 0 0
T47 481733 0 0 0
T56 1296 0 0 0
T65 0 4280 0 0
T82 0 86 0 0
T144 0 1545 0 0
T209 0 5187 0 0
T219 0 656 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 22363386 0 0
T3 3018 20 0 0
T4 97801 0 0 0
T5 0 16 0 0
T7 65648 29564 0 0
T8 123490 38816 0 0
T13 3151 0 0 0
T14 1011 0 0 0
T16 0 22 0 0
T19 2873 0 0 0
T20 8593 24 0 0
T23 0 252 0 0
T31 0 22 0 0
T32 1839 2 0 0
T47 481733 0 0 0
T62 0 16 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 396636823 0 0
T1 218011 205217 0 0
T2 1094 889 0 0
T3 3018 2858 0 0
T4 97801 97710 0 0
T7 65648 65576 0 0
T8 123490 123414 0 0
T13 3151 2448 0 0
T14 1011 945 0 0
T19 2873 2805 0 0
T20 8593 8440 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397248374 396449966 0 0
T1 218011 205217 0 0
T2 1094 889 0 0
T3 3018 2858 0 0
T4 97801 97710 0 0
T7 65648 65576 0 0
T8 123490 123414 0 0
T13 3151 2448 0 0
T14 1011 945 0 0
T19 2873 2805 0 0
T20 8593 8440 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 396636823 0 0
T1 218011 205217 0 0
T2 1094 889 0 0
T3 3018 2858 0 0
T4 97801 97710 0 0
T7 65648 65576 0 0
T8 123490 123414 0 0
T13 3151 2448 0 0
T14 1011 945 0 0
T19 2873 2805 0 0
T20 8593 8440 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS2286583.33
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 0 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions10610195.28
Logical10610195.28
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11CoveredT87,T220,T233

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT87,T220,T233

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT3,T7,T8
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT3,T7,T8
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T8,T20
110Not Covered
111CoveredT3,T7,T8

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT7,T8,T20
101CoveredT3,T7,T8
110CoveredT68,T69,T70
111CoveredT3,T7,T8

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT60
10CoveredT3,T7,T8
11CoveredT3,T7,T8

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T8
11CoveredT3,T7,T8

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T7,T8

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11CoveredT7,T8,T9

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT3,T4,T7
10CoveredT1,T4,T8
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT3,T4,T8
10CoveredT1,T4,T20
11CoveredT1,T4,T8

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT68,T69,T70
10CoveredT234,T235

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT234,T235

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT1,T2,T3
11CoveredT68,T69,T70

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T4,T8

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T4,T20
10CoveredT1,T2,T3
11CoveredT1,T4,T20

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T28,T29
10CoveredT1,T4,T20

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT220

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT3,T7,T8
10CoveredT220
11CoveredT220

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T8

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T7,T8
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT220

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT16,T17,T18

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T8,T32

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T8,T32

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T8,T32

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T8,T32

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T4,T20
StCtrlProg 338 Covered T1,T4,T8
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T13,T14,T15
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T4,T20
StCtrlProg->StIdle 358 Covered T1,T4,T8
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T1,T4,T20
StIdle->StCtrlProg 338 Covered T1,T4,T8
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T13,T14,T15



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 2 100.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 3 75.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T8,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T8,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T220
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T7,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T87,T220,T233
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T220
0 0 0 Covered T3,T7,T8


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T13,T14,T15
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T4,T8
StIdle 0 0 0 1 - - - Covered T1,T4,T20
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T4,T8
StCtrlProg - - - - - 0 - Covered T1,T4,T8
StCtrl - - - - - - 1 Covered T1,T4,T20
StCtrl - - - - - - 0 Covered T1,T4,T20
StDisable - - - - - - - Covered T13,T14,T15
default - - - - - - - Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 397435231 1508380 0 0
CtrlPrio_A 397435231 1508375 0 0
HostTransIdleChk_A 397435231 22457016 0 0
NoRemainder_A 1029 1029 0 0
OneHotReqs_A 397435231 396636823 0 0
Pow2Multiple_A 1029 1029 0 0
RdTxnCheck_A 397248374 396449966 0 0
u_state_regs_A 397435231 396636823 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 1508380 0 0
T5 2438 0 0 0
T7 65648 1858 0 0
T8 123490 604 0 0
T9 0 83 0 0
T14 1011 0 0 0
T19 2873 0 0 0
T20 8593 0 0 0
T25 0 1534 0 0
T28 0 84 0 0
T31 8160 0 0 0
T32 1839 0 0 0
T42 0 60049 0 0
T47 481733 0 0 0
T56 1296 0 0 0
T65 0 10290 0 0
T82 0 13 0 0
T185 0 84 0 0
T219 0 1990 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 1508375 0 0
T5 2438 0 0 0
T7 65648 1858 0 0
T8 123490 604 0 0
T9 0 83 0 0
T14 1011 0 0 0
T19 2873 0 0 0
T20 8593 0 0 0
T25 0 1534 0 0
T28 0 84 0 0
T31 8160 0 0 0
T32 1839 0 0 0
T42 0 60049 0 0
T47 481733 0 0 0
T56 1296 0 0 0
T65 0 10290 0 0
T82 0 13 0 0
T185 0 84 0 0
T219 0 1990 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 22457016 0 0
T3 3018 24 0 0
T4 97801 0 0 0
T5 0 16 0 0
T7 65648 30723 0 0
T8 123490 17690 0 0
T13 3151 0 0 0
T14 1011 0 0 0
T16 0 28 0 0
T19 2873 0 0 0
T20 8593 31 0 0
T23 0 273 0 0
T31 0 28 0 0
T32 1839 6 0 0
T47 481733 0 0 0
T62 0 8 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 396636823 0 0
T1 218011 205217 0 0
T2 1094 889 0 0
T3 3018 2858 0 0
T4 97801 97710 0 0
T7 65648 65576 0 0
T8 123490 123414 0 0
T13 3151 2448 0 0
T14 1011 945 0 0
T19 2873 2805 0 0
T20 8593 8440 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1029 1029 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397248374 396449966 0 0
T1 218011 205217 0 0
T2 1094 889 0 0
T3 3018 2858 0 0
T4 97801 97710 0 0
T7 65648 65576 0 0
T8 123490 123414 0 0
T13 3151 2448 0 0
T14 1011 945 0 0
T19 2873 2805 0 0
T20 8593 8440 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 397435231 396636823 0 0
T1 218011 205217 0 0
T2 1094 889 0 0
T3 3018 2858 0 0
T4 97801 97710 0 0
T7 65648 65576 0 0
T8 123490 123414 0 0
T13 3151 2448 0 0
T14 1011 945 0 0
T19 2873 2805 0 0
T20 8593 8440 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%