Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.69	100.00	90.75			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.52	100.00	90.09			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.69	100.00	90.75			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.52	100.00	90.09			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.59	99.17	93.26	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	96.63	84.91		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.69	100.00	90.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.64	99.17	93.51	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.40	98.88	95.28		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	454	412	90.75
Logical	454	412	90.75
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	91.07
706-710	66.67

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T20,T31,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T8,T20

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	794870462	1618979	0	0
ExclusiveOps_A	794870462	793273646	0	0
ExclusiveProgHazard_A	794870462	793273646	0	0
ExclusiveState_A	794870462	793273646	0	0
ForwardCheck_A	794870462	3404227	0	0
IdleCheck_A	794870462	100511443	0	0
MaxBufs_A	2058	2058	0	0
OneHotAlloc_A	794870462	793273646	0	0
OneHotMatch_A	794870462	793273646	0	0
OneHotRspMatch_A	794870462	793273646	0	0
OneHotUpdate_A	794870462	793273646	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	1618979	0	0
T1	218011	2144	0	0
T2	1094	0	0	0
T3	6036	25	0	0
T4	195602	1204	0	0
T5	0	38	0	0
T7	131296	2036	0	0
T8	246980	774	0	0
T13	6302	0	0	0
T14	2022	2	0	0
T19	5746	0	0	0
T20	17186	128	0	0
T23	0	176	0	0
T31	0	112	0	0
T32	1839	39	0	0
T47	481733	0	0	0
T48	0	8	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	3404227	0	0
T4	195602	1204	0	0
T6	0	2	0	0
T7	131296	0	0	0
T8	246980	17635	0	0
T9	0	24	0	0
T13	6302	0	0	0
T14	2022	0	0	0
T19	5746	0	0	0
T20	17186	36	0	0
T23	0	656	0	0
T31	16320	13	0	0
T32	3678	10	0	0
T36	0	32	0	0
T42	0	14582	0	0
T47	963466	0	0	0
T48	0	9	0	0
T65	0	43424	0	0
T83	0	154	0	0
T182	0	5	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	100511443	0	0
T1	218011	32224	0	0
T2	1094	264	0	0
T3	6036	425	0	0
T4	195602	3740	0	0
T5	0	41	0	0
T7	131296	75087	0	0
T8	246980	59988	0	0
T13	6302	296	0	0
T14	2022	146	0	0
T16	0	1225	0	0
T19	5746	128	0	0
T20	17186	800	0	0
T31	0	150	0	0
T32	1839	30	0	0
T47	481733	0	0	0
T48	0	26	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2058	2058	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T13	2	2	0	0
T14	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794870462	793273646	0	0
T1	436022	410434	0	0
T2	2188	1778	0	0
T3	6036	5716	0	0
T4	195602	195420	0	0
T7	131296	131152	0	0
T8	246980	246828	0	0
T13	6302	4896	0	0
T14	2022	1890	0	0
T19	5746	5610	0	0
T20	17186	16880	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	454	409	90.09
Logical	454	409	90.09
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.02
710	100.00

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T8
0	1	Covered	T25,T219,T144
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T32
0	1	Covered	T3,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T32
0	1	Covered	T3,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T7
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	397435231	788450	0	0
ExclusiveOps_A	397435231	396636823	0	0
ExclusiveProgHazard_A	397435231	396636823	0	0
ExclusiveState_A	397435231	396636823	0	0
ForwardCheck_A	397435231	1741596	0	0
IdleCheck_A	397435231	49210951	0	0
MaxBufs_A	1029	1029	0	0
OneHotAlloc_A	397435231	396636823	0	0
OneHotMatch_A	397435231	396636823	0	0
OneHotRspMatch_A	397435231	396636823	0	0
OneHotUpdate_A	397435231	396636823	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	788450	0	0
T3	3018	3	0	0
T4	97801	654	0	0
T5	0	5	0	0
T7	65648	1373	0	0
T8	123490	393	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	30	0	0
T23	0	176	0	0
T31	0	34	0	0
T32	1839	8	0	0
T47	481733	0	0	0
T48	0	8	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	1741596	0	0
T4	97801	654	0	0
T7	65648	0	0	0
T8	123490	8535	0	0
T9	0	18	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	0	0	0
T23	0	176	0	0
T31	8160	0	0	0
T32	1839	7	0	0
T42	0	14582	0	0
T47	481733	0	0	0
T48	0	9	0	0
T65	0	20937	0	0
T83	0	154	0	0
T182	0	5	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	49210951	0	0
T3	3018	35	0	0
T4	97801	1962	0	0
T5	0	41	0	0
T7	65648	39210	0	0
T8	123490	40699	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T16	0	1225	0	0
T19	2873	0	0	0
T20	8593	134	0	0
T31	0	150	0	0
T32	1839	30	0	0
T47	481733	0	0	0
T48	0	26	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	454	412	90.75
Logical	454	412	90.75
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	91.07
706-710	66.67

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T20,T31,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T8,T20

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	397435231	830529	0	0
ExclusiveOps_A	397435231	396636823	0	0
ExclusiveProgHazard_A	397435231	396636823	0	0
ExclusiveState_A	397435231	396636823	0	0
ForwardCheck_A	397435231	1662631	0	0
IdleCheck_A	397435231	51300492	0	0
MaxBufs_A	1029	1029	0	0
OneHotAlloc_A	397435231	396636823	0	0
OneHotMatch_A	397435231	396636823	0	0
OneHotRspMatch_A	397435231	396636823	0	0
OneHotUpdate_A	397435231	396636823	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	830529	0	0
T1	218011	2144	0	0
T2	1094	0	0	0
T3	3018	22	0	0
T4	97801	550	0	0
T5	0	33	0	0
T7	65648	663	0	0
T8	123490	381	0	0
T13	3151	0	0	0
T14	1011	2	0	0
T19	2873	0	0	0
T20	8593	98	0	0
T31	0	78	0	0
T32	0	31	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	1662631	0	0
T4	97801	550	0	0
T6	0	2	0	0
T7	65648	0	0	0
T8	123490	9100	0	0
T9	0	6	0	0
T13	3151	0	0	0
T14	1011	0	0	0
T19	2873	0	0	0
T20	8593	36	0	0
T23	0	480	0	0
T31	8160	13	0	0
T32	1839	3	0	0
T36	0	32	0	0
T47	481733	0	0	0
T65	0	22487	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	51300492	0	0
T1	218011	32224	0	0
T2	1094	264	0	0
T3	3018	390	0	0
T4	97801	1778	0	0
T7	65648	35877	0	0
T8	123490	19289	0	0
T13	3151	296	0	0
T14	1011	146	0	0
T19	2873	128	0	0
T20	8593	666	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397435231	396636823	0	0
T1	218011	205217	0	0
T2	1094	889	0	0
T3	3018	2858	0	0
T4	97801	97710	0	0
T7	65648	65576	0	0
T8	123490	123414	0	0
T13	3151	2448	0	0
T14	1011	945	0	0
T19	2873	2805	0	0
T20	8593	8440	0	0