Module Definition
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Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.96 100.00 65.52 85.71 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.74 89.52 65.61 82.56 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 87.32 100.00 74.29 75.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 69.33 91.43 57.14 68.75 60.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 72.63 94.44 54.84 81.25 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.51 100.00 77.50 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.17 89.08 77.37 100.00 89.41 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 98.30 100.00 91.49 100.00 100.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 91.67 100.00 72.22 94.44 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.21 100.00 84.30 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.18 92.83 83.46 100.00 94.62 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.66 97.12 94.40 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 79.64 100.00 68.57 50.00 100.00
u_reqfifo 96.53 100.00 86.11 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 97.16 100.00 88.64 100.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 96.53 100.00 86.11 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
83.96 100.00
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL6565100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12433100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26688100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46100
CONT_ASSIGN46300
CONT_ASSIGN47000
ALWAYS47633100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 unreachable
MISSING_ELSE
133 1 1
138 1 1
145 1 1
156 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 1 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
432 1 1
433 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 unreachable
463 unreachable
470 unreachable
476 1 1
480 1 1
482 1 1
MISSING_ELSE
497 1 1
502 1 1
507 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
93.51 100.00
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL6969100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12444100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26688100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN47011100.00
ALWAYS47633100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 1 1
MISSING_ELSE
133 1 1
138 1 1
145 1 1
150 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 1 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
432 1 1
433 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 1 1
463 1 1
470 1 1
476 1 1
480 1 1
482 1 1
MISSING_ELSE
497 1 1
502 1 1
507 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
95.21 100.00
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL6969100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12444100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26688100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN47011100.00
ALWAYS47633100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 1 1
MISSING_ELSE
133 1 1
138 1 1
145 1 1
150 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 1 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
432 1 1
433 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 1 1
463 1 1
470 1 1
476 1 1
480 1 1
482 1 1
MISSING_ELSE
497 1 1
502 1 1
507 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
83.96 65.52
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1167665.52
Logical1167665.52
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T17,T7
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T6,T18
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T18
11CoveredT4,T6,T18

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T8,T19
11CoveredT4,T6,T18

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T8
11CoveredT4,T6,T18

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T6,T18
1Not Covered

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T6,T18
1Not Covered

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T6,T18
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T6,T18

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T18
11Not Covered

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T6,T18
110Not Covered
111CoveredT1,T2,T3

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T6,T18
110Not Covered
111CoveredT4,T6,T18

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T6,T18

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT4,T6,T18

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT4,T6,T18

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T18
11Not Covered

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T6,T18
10Unreachable
11Unreachable

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
93.51 77.50
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1209377.50
Logical1209377.50
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T38
10Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T16,T38
010CoveredT15,T16,T38
100Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T17,T7
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T5,T6
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T8
11CoveredT4,T5,T6

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T9
11CoveredT4,T5,T6

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT4,T5,T6

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT4,T5,T6

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT9,T39,T40

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT4,T5,T6

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T39,T40
11CoveredT4,T5,T6

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT9,T39,T40

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT20,T41,T42
110Not Covered
111CoveredT4,T5,T6

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T6

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11Not Covered

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT20,T41,T42
10Not Covered
11CoveredT4,T5,T6

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
95.21 84.30
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions12110284.30
Logical12110284.30
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT22,T23,T43

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT22,T23,T43
010Unreachable
100CoveredT22,T23,T43

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T5
01CoveredT1,T3,T5
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT5,T21,T35
01CoveredT3,T5,T44
10CoveredT3,T5,T45

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT3,T5,T44
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT3,T5,T45
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT5,T6,T9
000001CoveredT22,T23,T43
000010CoveredT3,T5,T46
000100CoveredT47,T48,T49
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT47,T49,T50
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T20,T21
11CoveredT5,T6,T9

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT5,T6,T9

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT5,T6,T9

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT47,T48,T49
10CoveredT25,T21,T51

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT47,T48,T49
1110Not Covered
1111CoveredT5,T6,T9

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T21,T51
11CoveredT5,T6,T9

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT47,T48,T49
10CoveredT5,T6,T9
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT5,T6,T9
101CoveredT1,T2,T3
110CoveredT47,T48,T49
111CoveredT47,T48,T49

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T9
11Not Covered

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T9
11CoveredT25,T21,T51

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT48,T52
110Not Covered
111CoveredT5,T6,T9

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT47,T48,T49
10CoveredT5,T6,T9

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T6,T9
110CoveredT47,T48,T49
111CoveredT5,T6,T9

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T9
11Not Covered

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT5,T6,T9
1Not Covered

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T9
11Not Covered

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T6,T9

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT5,T6,T9
10Not Covered
11CoveredT5,T6,T9

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT47,T48,T49
11CoveredT5,T6,T9

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 138 2 2 100.00
TERNARY 328 2 2 100.00
TERNARY 334 3 2 66.67
TERNARY 379 2 2 100.00
TERNARY 502 2 2 100.00
IF 124 3 3 100.00
IF 268 4 4 100.00
IF 288 3 3 100.00
IF 349 2 2 100.00
IF 412 2 2 100.00
IF 424 2 2 100.00
IF 480 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 328 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 334 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 502 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 if ((!rst_ni)) -2-: 126 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T11,T16
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (reqfifo_rvalid) -2-: 269 if (reqfifo_rdata.error) -3-: 272 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T47,T48,T49
1 0 1 Covered T4,T5,T6
1 0 0 Covered T4,T6,T18
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 288 if (reqfifo_rvalid) -2-: 289 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T4,T6,T18
0 - Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 412 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 480 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1115785170 1113114609 0 0
DataIntgOptions_A 3042 3042 0 0
ReqOutKnown_A 1115785170 1113114609 0 0
SramDwHasByteGranularity_A 3042 3042 0 0
SramDwIsMultipleOfTlulWidth_A 3042 3042 0 0
TlOutKnownIfFifoKnown_A 1115785170 1113114609 0 0
TlOutValidKnown_A 1115785170 1113114609 0 0
WdataOutKnown_A 1115785170 1113114609 0 0
WeOutKnown_A 1115785170 1113114609 0 0
WmaskOutKnown_A 1115785170 1113114609 0 0
adapterNoReadOrWrite 3042 3042 0 0
rvalidHighReqFifoEmpty 1115785170 7082280 0 0
rvalidHighWhenRspFifoFull 1115119515 7075681 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3042 3042 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T9 3 3 0 0
T13 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3042 3042 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T9 3 3 0 0
T13 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3042 3042 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T9 3 3 0 0
T13 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 1113114609 0 0
T1 3330 2625 0 0
T2 1445046 1444656 0 0
T3 9735 7710 0 0
T4 171048 170895 0 0
T5 162156 161940 0 0
T6 1072581 1072362 0 0
T9 326043 325749 0 0
T13 10065 7809 0 0
T17 5172 4962 0 0
T18 96393 96096 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 3042 3042 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T9 3 3 0 0
T13 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115785170 7082280 0 0
T4 57016 8192 0 0
T5 108104 23351 0 0
T6 715054 49631 0 0
T7 5576 8 0 0
T8 0 5632 0 0
T9 217362 19626 0 0
T13 6710 0 0 0
T17 3448 0 0 0
T18 64262 6144 0 0
T20 0 131072 0 0
T24 0 64 0 0
T25 0 8 0 0
T26 0 16913 0 0
T34 0 16604 0 0
T39 197226 20231 0 0
T53 0 41 0 0
T54 0 10 0 0
T55 3002 0 0 0
T56 1832 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1115119515 7075681 0 0
T4 57016 8192 0 0
T5 108104 23351 0 0
T6 715054 49631 0 0
T7 5576 8 0 0
T8 0 5632 0 0
T9 217362 19626 0 0
T13 6710 0 0 0
T17 3448 0 0 0
T18 64262 6144 0 0
T20 0 131072 0 0
T24 0 64 0 0
T25 0 8 0 0
T26 0 16913 0 0
T34 0 16604 0 0
T39 197226 20231 0 0
T53 0 41 0 0
T54 0 10 0 0
T55 3002 0 0 0
T56 1832 0 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL6565100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12433100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26688100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46100
CONT_ASSIGN46300
CONT_ASSIGN47000
ALWAYS47633100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 unreachable
MISSING_ELSE
133 1 1
138 1 1
145 1 1
156 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 1 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
432 1 1
433 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 unreachable
463 unreachable
470 unreachable
476 1 1
480 1 1
482 1 1
MISSING_ELSE
497 1 1
502 1 1
507 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1167665.52
Logical1167665.52
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T17,T7
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T6,T18
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T18
11CoveredT4,T6,T18

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T8,T19
11CoveredT4,T6,T18

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T8
11CoveredT4,T6,T18

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T6,T18
1Not Covered

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT4,T6,T18
1Not Covered

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T6,T18
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T6,T18

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T18
11Not Covered

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T6,T18
110Not Covered
111CoveredT1,T2,T3

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T6,T18
110Not Covered
111CoveredT4,T6,T18

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T6,T18

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T18

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT4,T6,T18

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT4,T6,T18

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T18
11Not Covered

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T6,T18
10Unreachable
11Unreachable

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 28 24 85.71
TERNARY 138 2 2 100.00
TERNARY 328 2 1 50.00
TERNARY 334 3 1 33.33
TERNARY 379 2 2 100.00
TERNARY 502 2 1 50.00
IF 124 2 2 100.00
IF 268 4 4 100.00
IF 288 3 3 100.00
IF 349 2 2 100.00
IF 412 2 2 100.00
IF 424 2 2 100.00
IF 480 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 328 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 334 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 502 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 if ((!rst_ni)) -2-: 126 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (reqfifo_rvalid) -2-: 269 if (reqfifo_rdata.error) -3-: 272 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T11
1 0 1 Covered T11
1 0 0 Covered T4,T6,T18
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 288 if (reqfifo_rvalid) -2-: 289 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T11
1 0 Covered T4,T6,T18
0 - Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 412 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T6,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T6,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 480 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T11
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 371928390 371038203 0 0
DataIntgOptions_A 1014 1014 0 0
ReqOutKnown_A 371928390 371038203 0 0
SramDwHasByteGranularity_A 1014 1014 0 0
SramDwIsMultipleOfTlulWidth_A 1014 1014 0 0
TlOutKnownIfFifoKnown_A 371928390 371038203 0 0
TlOutValidKnown_A 371928390 371038203 0 0
WdataOutKnown_A 371928390 371038203 0 0
WeOutKnown_A 371928390 371038203 0 0
WmaskOutKnown_A 371928390 371038203 0 0
adapterNoReadOrWrite 1014 1014 0 0
rvalidHighReqFifoEmpty 371928390 0 0 0
rvalidHighWhenRspFifoFull 371928390 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL6969100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12444100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26688100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN47011100.00
ALWAYS47633100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 1 1
MISSING_ELSE
133 1 1
138 1 1
145 1 1
150 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 1 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
432 1 1
433 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 1 1
463 1 1
470 1 1
476 1 1
480 1 1
482 1 1
MISSING_ELSE
497 1 1
502 1 1
507 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1209377.50
Logical1209377.50
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T38
10Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T16,T38
010CoveredT15,T16,T38
100Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T17,T7
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T5,T6
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T8
11CoveredT4,T5,T6

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T9
11CoveredT4,T5,T6

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT4,T5,T6

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT4,T5,T6

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT4,T5,T6
01Not Covered
10CoveredT9,T39,T40

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT4,T5,T6

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T39,T40
11CoveredT4,T5,T6

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT9,T39,T40

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT20,T41,T42
110Not Covered
111CoveredT4,T5,T6

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T6

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11Not Covered

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11Not Covered

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT20,T41,T42
10Not Covered
11CoveredT4,T5,T6

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 138 2 2 100.00
TERNARY 328 2 2 100.00
TERNARY 334 3 2 66.67
TERNARY 379 2 2 100.00
TERNARY 502 2 2 100.00
IF 124 3 3 100.00
IF 268 4 4 100.00
IF 288 3 3 100.00
IF 349 2 2 100.00
IF 412 2 2 100.00
IF 424 2 2 100.00
IF 480 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 328 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 334 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 502 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 if ((!rst_ni)) -2-: 126 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T11,T16
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (reqfifo_rvalid) -2-: 269 if (reqfifo_rdata.error) -3-: 272 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T11
1 0 1 Covered T4,T5,T6
1 0 0 Covered T11
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 288 if (reqfifo_rvalid) -2-: 289 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T11
0 - Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 412 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 480 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 371928390 371038203 0 0
DataIntgOptions_A 1014 1014 0 0
ReqOutKnown_A 371928390 371038203 0 0
SramDwHasByteGranularity_A 1014 1014 0 0
SramDwIsMultipleOfTlulWidth_A 1014 1014 0 0
TlOutKnownIfFifoKnown_A 371928390 371038203 0 0
TlOutValidKnown_A 371928390 371038203 0 0
WdataOutKnown_A 371928390 371038203 0 0
WeOutKnown_A 371928390 371038203 0 0
WmaskOutKnown_A 371928390 371038203 0 0
adapterNoReadOrWrite 1014 1014 0 0
rvalidHighReqFifoEmpty 371928390 3123213 0 0
rvalidHighWhenRspFifoFull 371262735 3116614 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 3123213 0 0
T4 57016 8192 0 0
T5 54052 6489 0 0
T6 357527 7588 0 0
T7 2788 8 0 0
T8 0 5632 0 0
T9 108681 2768 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 6144 0 0
T24 0 52 0 0
T39 98613 3785 0 0
T53 0 41 0 0
T55 1501 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 371262735 3116614 0 0
T4 57016 8192 0 0
T5 54052 6489 0 0
T6 357527 7588 0 0
T7 2788 8 0 0
T8 0 5632 0 0
T9 108681 2768 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 6144 0 0
T24 0 52 0 0
T39 98613 3785 0 0
T53 0 41 0 0
T55 1501 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL6969100.00
CONT_ASSIGN10200
CONT_ASSIGN10900
ALWAYS12444100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
ALWAYS26688100.00
ALWAYS28666100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN34611100.00
ALWAYS34933100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
ALWAYS40966100.00
ALWAYS42155100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46311100.00
CONT_ASSIGN47011100.00
ALWAYS47633100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 unreachable
109 unreachable
124 1 1
125 1 1
126 1 1
127 1 1
MISSING_ELSE
133 1 1
138 1 1
145 1 1
150 1 1
170 1 1
182 1 1
259 1 1
260 1 1
261 1 1
266 1 1
268 1 1
269 1 1
271 1 1
272 1 1
273 1 1
276 1 1
279 1 1
286 1 1
288 1 1
289 1 1
290 1 1
292 1 1
295 1 1
300 1 1
304 1 1
323 1 1
328 1 1
334 1 1
346 1 1
349 1 1
350 1 1
352 1 1
356 1 1
376 1 1
377 1 1
378 1 1
379 1 1
409 1 1
410 1 1
412 1 1
413 1 1
414 1 1
415 1 1
MISSING_ELSE
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
432 1 1
433 1 1
442 1 1
443 1 1
445 1 1
446 1 1
453 1 1
456 1 1
460 1 1
461 1 1
463 1 1
470 1 1
476 1 1
480 1 1
482 1 1
MISSING_ELSE
497 1 1
502 1 1
507 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions12110284.30
Logical12110284.30
Non-Logical00
Event00

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT22,T23,T43

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT22,T23,T43
010Unreachable
100CoveredT22,T23,T43

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T5
01CoveredT1,T3,T5
10CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT5,T21,T35
01CoveredT3,T5,T44
10CoveredT3,T5,T45

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT3,T5,T44
1CoveredT1,T2,T3

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT3,T5,T45
1CoveredT1,T2,T3

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT5,T6,T9
000001CoveredT22,T23,T43
000010CoveredT3,T5,T46
000100CoveredT47,T48,T49
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT47,T49,T50
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T20,T21
11CoveredT5,T6,T9

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT5,T6,T9

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT11
1CoveredT5,T6,T9

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT47,T48,T49
10CoveredT25,T21,T51

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT47,T48,T49
1110Not Covered
1111CoveredT5,T6,T9

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T21,T51
11CoveredT5,T6,T9

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT47,T48,T49
10CoveredT5,T6,T9
11Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT5,T6,T9
101CoveredT1,T2,T3
110CoveredT47,T48,T49
111CoveredT47,T48,T49

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T9
11Not Covered

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T9
11CoveredT25,T21,T51

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT48,T52
110Not Covered
111CoveredT5,T6,T9

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT47,T48,T49
10CoveredT5,T6,T9

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T6,T9
110CoveredT47,T48,T49
111CoveredT5,T6,T9

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T9
11Not Covered

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT5,T6,T9
1Not Covered

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T9
11Not Covered

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT1,T2,T3

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T6,T9

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT5,T6,T9
10Not Covered
11CoveredT5,T6,T9

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT47,T48,T49
11CoveredT5,T6,T9

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 138 2 2 100.00
TERNARY 328 2 2 100.00
TERNARY 334 3 2 66.67
TERNARY 379 2 2 100.00
TERNARY 502 2 2 100.00
IF 124 3 3 100.00
IF 268 4 4 100.00
IF 288 3 3 100.00
IF 349 2 2 100.00
IF 412 2 2 100.00
IF 424 2 2 100.00
IF 480 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T5


LineNo. Expression -1-: 328 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 334 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 334 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T5,T6,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 502 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 124 if ((!rst_ni)) -2-: 126 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T22,T23
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if (reqfifo_rvalid) -2-: 269 if (reqfifo_rdata.error) -3-: 272 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T47,T48,T49
1 0 1 Covered T5,T6,T9
1 0 0 Covered T11
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 288 if (reqfifo_rvalid) -2-: 289 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T5,T6,T9
1 0 Covered T11
0 - Covered T1,T2,T3


LineNo. Expression -1-: 349 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 412 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 424 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 480 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 371928390 371038203 0 0
DataIntgOptions_A 1014 1014 0 0
ReqOutKnown_A 371928390 371038203 0 0
SramDwHasByteGranularity_A 1014 1014 0 0
SramDwIsMultipleOfTlulWidth_A 1014 1014 0 0
TlOutKnownIfFifoKnown_A 371928390 371038203 0 0
TlOutValidKnown_A 371928390 371038203 0 0
WdataOutKnown_A 371928390 371038203 0 0
WeOutKnown_A 371928390 371038203 0 0
WmaskOutKnown_A 371928390 371038203 0 0
adapterNoReadOrWrite 1014 1014 0 0
rvalidHighReqFifoEmpty 371928390 3959067 0 0
rvalidHighWhenRspFifoFull 371928390 3959067 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 3959067 0 0
T5 54052 16862 0 0
T6 357527 42043 0 0
T7 2788 0 0 0
T9 108681 16858 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 131072 0 0
T24 0 12 0 0
T25 0 8 0 0
T26 0 16913 0 0
T34 0 16604 0 0
T39 98613 16446 0 0
T54 0 10 0 0
T55 1501 0 0 0
T56 1832 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 3959067 0 0
T5 54052 16862 0 0
T6 357527 42043 0 0
T7 2788 0 0 0
T9 108681 16858 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 131072 0 0
T24 0 12 0 0
T25 0 8 0 0
T26 0 16913 0 0
T34 0 16604 0 0
T39 98613 16446 0 0
T54 0 10 0 0
T55 1501 0 0 0
T56 1832 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%