Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo.u_sram_byte	100.00	100.00					100.00
tb.dut.u_to_rd_fifo.u_sram_byte	100.00	100.00					100.00
tb.dut.u_tl_adapter_eflash.u_sram_byte	100.00	100.00					100.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.96	100.00	65.52			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.51	100.00	77.50			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.21	100.00	84.30			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	704	0	0
CONT_ASSIGN	710	0	0
CONT_ASSIGN	711	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
696	1	1
697	1	1
698	1	1
704		unreachable
710		unreachable
711		unreachable

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	3042	3042	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	3042	3042	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T9	3	3	0	0
T13	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	704	0	0
CONT_ASSIGN	710	0	0
CONT_ASSIGN	711	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
696	1	1
697	1	1
698	1	1
704		unreachable
710		unreachable
711		unreachable

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1014	1014	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	704	0	0
CONT_ASSIGN	710	0	0
CONT_ASSIGN	711	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
696	1	1
697	1	1
698	1	1
704		unreachable
710		unreachable
711		unreachable

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1014	1014	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	704	0	0
CONT_ASSIGN	710	0	0
CONT_ASSIGN	711	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
696	1	1
697	1	1
698	1	1
704		unreachable
710		unreachable
711		unreachable

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1014	1014	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0