Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.17 92.31 97.69 100.00 86.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.17 92.31 97.69 100.00 86.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.63 100.00 90.53 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.17 92.31 97.69 100.00 86.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.17 92.31 97.69 100.00 86.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.47 100.00 89.87 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
SCORELINE
94.17 92.31
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORELINE
94.17 92.31
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORELINE
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T39,T61
11CoveredT5,T39,T61

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT5,T39,T26
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT5,T39,T26
110CoveredT5,T39,T61
111UnreachableT5,T39,T61

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T39,T61
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T39,T61
01CoveredT5,T39,T61
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT5,T39,T61
11CoveredT5,T39,T61

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T39,T26
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT5,T39,T26
10CoveredT1,T2,T3
11CoveredT5,T39,T61

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T39,T61
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T39,T61

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
95.01 86.27
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
95.01 86.27
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions514486.27
Logical514486.27
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T61,T24
11CoveredT39,T61,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT39,T61,T24
111CoveredT39,T61,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT39,T61,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT39,T61,T24
01CoveredT39,T61,T24
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T61,T24
11CoveredT39,T61,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT39,T61,T24

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT39,T61,T24
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT39,T61,T24

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
SCORECOND
94.17 97.69
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORECOND
94.17 97.69
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T9,T39
11CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T9,T39
10CoveredT6,T9,T39

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T9,T39
10CoveredT4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT4,T5,T6
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
SCOREBRANCH
94.17 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCOREBRANCH
94.17 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCOREBRANCH
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_tree
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 6084 6084 0 0
GntImpliesReady_A 2147483647 69710126 0 0
GntImpliesValid_A 2147483647 69710126 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 69710126 0 0
LockArbDecision_A 2147483647 64778120 0 0
NoReadyValidNoGrant_A 2147483647 1886066422 0 0
ReadyAndValidImplyGrant_A 2147483647 69710126 0 0
ReqAndReadyImplyGrant_A 2147483647 69710126 0 0
ReqImpliesValid_A 2147483647 330392073 0 0
ReqStaysHighUntilGranted0_M 2147483647 64777774 0 0
RoundRobin_A 2147483647 23651 0 6048
ValidKnown_A 2147483647 2147483647 0 0
gen_data_port_assertion.DataFlow_A 1487713560 64778120 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6660 5250 0 0
T2 2890092 2889312 0 0
T3 19470 15420 0 0
T4 342096 341790 0 0
T5 324312 323880 0 0
T6 2145162 2144724 0 0
T9 652086 651498 0 0
T13 20130 15618 0 0
T17 10344 9924 0 0
T18 192786 192192 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6084 6084 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T9 6 6 0 0
T13 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69710126 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 285080 2808 0 0
T5 324312 61015 0 0
T6 2145162 73177 0 0
T7 5576 1 0 0
T8 0 252 0 0
T9 652086 27949 0 0
T13 20130 576 0 0
T17 10344 128 0 0
T18 192786 1276 0 0
T20 0 134396 0 0
T24 0 26 0 0
T25 0 7 0 0
T39 197226 18665 0 0
T53 0 33 0 0
T55 3002 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69710126 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 285080 2808 0 0
T5 324312 61015 0 0
T6 2145162 73177 0 0
T7 5576 1 0 0
T8 0 252 0 0
T9 652086 27949 0 0
T13 20130 576 0 0
T17 10344 128 0 0
T18 192786 1276 0 0
T20 0 134396 0 0
T24 0 26 0 0
T25 0 7 0 0
T39 197226 18665 0 0
T53 0 33 0 0
T55 3002 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6660 5250 0 0
T2 2890092 2889312 0 0
T3 19470 15420 0 0
T4 342096 341790 0 0
T5 324312 323880 0 0
T6 2145162 2144724 0 0
T9 652086 651498 0 0
T13 20130 15618 0 0
T17 10344 9924 0 0
T18 192786 192192 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6660 5250 0 0
T2 2890092 2889312 0 0
T3 19470 15420 0 0
T4 342096 341790 0 0
T5 324312 323880 0 0
T6 2145162 2144724 0 0
T9 652086 651498 0 0
T13 20130 15618 0 0
T17 10344 9924 0 0
T18 192786 192192 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69710126 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 285080 2808 0 0
T5 324312 61015 0 0
T6 2145162 73177 0 0
T7 5576 1 0 0
T8 0 252 0 0
T9 652086 27949 0 0
T13 20130 576 0 0
T17 10344 128 0 0
T18 192786 1276 0 0
T20 0 134396 0 0
T24 0 26 0 0
T25 0 7 0 0
T39 197226 18665 0 0
T53 0 33 0 0
T55 3002 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 64778120 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 228064 2048 0 0
T5 216208 40930 0 0
T6 1430108 26612 0 0
T9 434724 10016 0 0
T13 13420 576 0 0
T17 6896 128 0 0
T18 128524 1024 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1886066422 0 0
T1 6660 4665 0 0
T2 2890092 2889024 0 0
T3 19470 14483 0 0
T4 342096 287655 0 0
T5 324312 134840 0 0
T6 2145162 1377372 0 0
T9 652086 415065 0 0
T13 20130 14322 0 0
T17 10344 9636 0 0
T18 192786 169854 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69710126 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 285080 2808 0 0
T5 324312 61015 0 0
T6 2145162 73177 0 0
T7 5576 1 0 0
T8 0 252 0 0
T9 652086 27949 0 0
T13 20130 576 0 0
T17 10344 128 0 0
T18 192786 1276 0 0
T20 0 134396 0 0
T24 0 26 0 0
T25 0 7 0 0
T39 197226 18665 0 0
T53 0 33 0 0
T55 3002 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69710126 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 285080 2808 0 0
T5 324312 61015 0 0
T6 2145162 73177 0 0
T7 5576 1 0 0
T8 0 252 0 0
T9 652086 27949 0 0
T13 20130 576 0 0
T17 10344 128 0 0
T18 192786 1276 0 0
T20 0 134396 0 0
T24 0 26 0 0
T25 0 7 0 0
T39 197226 18665 0 0
T53 0 33 0 0
T55 3002 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 330392073 0 0
T1 4440 520 0 0
T2 1926728 256 0 0
T3 12980 832 0 0
T4 285080 54095 0 0
T5 324312 189000 0 0
T6 2145162 767312 0 0
T7 5576 1889 0 0
T8 0 38843 0 0
T9 652086 236393 0 0
T13 20130 1152 0 0
T17 10344 256 0 0
T18 192786 22302 0 0
T20 0 466054 0 0
T24 0 3299 0 0
T25 0 830 0 0
T39 197226 196291 0 0
T53 0 134094 0 0
T55 3002 0 0 0
T56 1832 0 0 0
T66 0 52694 0 0
T67 0 141002 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 64777774 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 228064 2048 0 0
T5 216208 40930 0 0
T6 1430108 26612 0 0
T9 434724 10016 0 0
T13 13420 576 0 0
T17 6896 128 0 0
T18 128524 1024 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 23651 0 6048
T6 715054 499 0 2
T7 5576 0 0 2
T8 106402 0 0 2
T9 217362 181 0 2
T18 64262 0 0 2
T19 6822 0 0 2
T21 0 522 0 0
T39 197226 96 0 2
T55 3002 0 0 2
T56 3664 0 0 2
T61 456186 0 0 2
T71 0 152 0 0
T73 0 43 0 0
T105 0 315 0 0
T174 0 39 0 0
T175 0 40 0 0
T176 0 251 0 0
T177 0 48 0 0
T178 0 71 0 0
T179 0 1096 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6660 5250 0 0
T2 2890092 2889312 0 0
T3 19470 15420 0 0
T4 342096 341790 0 0
T5 324312 323880 0 0
T6 2145162 2144724 0 0
T9 652086 651498 0 0
T13 20130 15618 0 0
T17 10344 9924 0 0
T18 192786 192192 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1487713560 64778120 0 0
T1 4440 260 0 0
T2 1926728 128 0 0
T3 12980 416 0 0
T4 228064 2048 0 0
T5 216208 40930 0 0
T6 1430108 26612 0 0
T9 434724 10016 0 0
T13 13420 576 0 0
T17 6896 128 0 0
T18 128524 1024 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T9,T39
11CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T6
110CoveredT4,T5,T6
111CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T9,T39
10CoveredT6,T9,T39

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T9,T39
10CoveredT4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT4,T5,T6
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 13 86.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 13 86.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 371928390 371038203 0 0
CheckNGreaterZero_A 1014 1014 0 0
GntImpliesReady_A 371928390 2206738 0 0
GntImpliesValid_A 371928390 2206738 0 0
GrantKnown_A 371928390 371038203 0 0
IdxKnown_A 371928390 371038203 0 0
IndexIsCorrect_A 371928390 2206738 0 0
LockArbDecision_A 371928390 0 0 0
NoReadyValidNoGrant_A 371928390 270761980 0 0
ReadyAndValidImplyGrant_A 371928390 2206738 0 0
ReqAndReadyImplyGrant_A 371928390 2206738 0 0
ReqImpliesValid_A 371928390 95011588 0 0
ReqStaysHighUntilGranted0_M 371928390 0 0 0
RoundRobin_A 371928390 11790 0 1008
ValidKnown_A 371928390 371038203 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2206738 0 0
T4 57016 760 0 0
T5 54052 10478 0 0
T6 357527 24172 0 0
T7 2788 1 0 0
T8 0 252 0 0
T9 108681 8642 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 252 0 0
T24 0 16 0 0
T39 98613 9318 0 0
T53 0 14 0 0
T55 1501 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2206738 0 0
T4 57016 760 0 0
T5 54052 10478 0 0
T6 357527 24172 0 0
T7 2788 1 0 0
T8 0 252 0 0
T9 108681 8642 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 252 0 0
T24 0 16 0 0
T39 98613 9318 0 0
T53 0 14 0 0
T55 1501 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2206738 0 0
T4 57016 760 0 0
T5 54052 10478 0 0
T6 357527 24172 0 0
T7 2788 1 0 0
T8 0 252 0 0
T9 108681 8642 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 252 0 0
T24 0 16 0 0
T39 98613 9318 0 0
T53 0 14 0 0
T55 1501 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 270761980 0 0
T1 1110 810 0 0
T2 481682 481520 0 0
T3 3245 2465 0 0
T4 57016 6926 0 0
T5 54052 379 0 0
T6 357527 371 0 0
T9 108681 362 0 0
T13 3355 2459 0 0
T17 1724 1622 0 0
T18 32131 11742 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2206738 0 0
T4 57016 760 0 0
T5 54052 10478 0 0
T6 357527 24172 0 0
T7 2788 1 0 0
T8 0 252 0 0
T9 108681 8642 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 252 0 0
T24 0 16 0 0
T39 98613 9318 0 0
T53 0 14 0 0
T55 1501 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2206738 0 0
T4 57016 760 0 0
T5 54052 10478 0 0
T6 357527 24172 0 0
T7 2788 1 0 0
T8 0 252 0 0
T9 108681 8642 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 252 0 0
T24 0 16 0 0
T39 98613 9318 0 0
T53 0 14 0 0
T55 1501 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 95011588 0 0
T4 57016 49999 0 0
T5 54052 53565 0 0
T6 357527 357047 0 0
T7 2788 1889 0 0
T8 0 38843 0 0
T9 108681 108185 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 20254 0 0
T24 0 1619 0 0
T39 98613 98153 0 0
T53 0 70980 0 0
T55 1501 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 11790 0 1008
T6 357527 231 0 1
T7 2788 0 0 1
T8 53201 0 0 1
T9 108681 54 0 1
T18 32131 0 0 1
T19 3411 0 0 1
T21 0 302 0 0
T39 98613 64 0 1
T55 1501 0 0 1
T56 1832 0 0 1
T61 228093 0 0 1
T71 0 40 0 0
T73 0 11 0 0
T174 0 39 0 0
T175 0 40 0 0
T176 0 183 0 0
T177 0 48 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT6,T9,T39
11CoveredT5,T6,T9

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T6,T9
110CoveredT5,T6,T9
111CoveredT5,T6,T9

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T6,T9
110CoveredT5,T6,T9
111CoveredT5,T6,T9

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T6,T9
110CoveredT5,T6,T9
111CoveredT5,T6,T9

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT5,T6,T9
101CoveredT5,T6,T9
110CoveredT5,T6,T9
111CoveredT5,T6,T9

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT1,T2,T3
11CoveredT5,T6,T9

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT1,T2,T3
11CoveredT5,T6,T9

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT5,T6,T9
01CoveredT5,T6,T9
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT1,T2,T3
11CoveredT5,T6,T9

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT39,T26,T21
10CoveredT39,T26,T21

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT39,T26,T21
10CoveredT5,T6,T9

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT5,T6,T9

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT5,T6,T9
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT5,T6,T9
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT5,T6,T9
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT5,T6,T9
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT5,T6,T9
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT5,T6,T9
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT5,T6,T9

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT1,T2,T3
11CoveredT5,T6,T9

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T9
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T9
11CoveredT5,T6,T9

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT5,T6,T9
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T9
10CoveredT5,T6,T9

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T9


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T9


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T9


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T9


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T9


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T6,T9


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 13 86.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 13 86.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 371928390 371038203 0 0
CheckNGreaterZero_A 1014 1014 0 0
GntImpliesReady_A 371928390 2725268 0 0
GntImpliesValid_A 371928390 2725268 0 0
GrantKnown_A 371928390 371038203 0 0
IdxKnown_A 371928390 371038203 0 0
IndexIsCorrect_A 371928390 2725268 0 0
LockArbDecision_A 371928390 0 0 0
NoReadyValidNoGrant_A 371928390 260707968 0 0
ReadyAndValidImplyGrant_A 371928390 2725268 0 0
ReqAndReadyImplyGrant_A 371928390 2725268 0 0
ReqImpliesValid_A 371928390 105824147 0 0
ReqStaysHighUntilGranted0_M 371928390 0 0 0
RoundRobin_A 371928390 11861 0 1008
ValidKnown_A 371928390 371038203 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2725268 0 0
T5 54052 9607 0 0
T6 357527 22393 0 0
T7 2788 0 0 0
T9 108681 9291 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 134396 0 0
T24 0 10 0 0
T25 0 7 0 0
T39 98613 9347 0 0
T53 0 19 0 0
T55 1501 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2725268 0 0
T5 54052 9607 0 0
T6 357527 22393 0 0
T7 2788 0 0 0
T9 108681 9291 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 134396 0 0
T24 0 10 0 0
T25 0 7 0 0
T39 98613 9347 0 0
T53 0 19 0 0
T55 1501 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2725268 0 0
T5 54052 9607 0 0
T6 357527 22393 0 0
T7 2788 0 0 0
T9 108681 9291 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 134396 0 0
T24 0 10 0 0
T25 0 7 0 0
T39 98613 9347 0 0
T53 0 19 0 0
T55 1501 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 260707968 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 401 0 0
T6 357527 409 0 0
T9 108681 403 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2725268 0 0
T5 54052 9607 0 0
T6 357527 22393 0 0
T7 2788 0 0 0
T9 108681 9291 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 134396 0 0
T24 0 10 0 0
T25 0 7 0 0
T39 98613 9347 0 0
T53 0 19 0 0
T55 1501 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 2725268 0 0
T5 54052 9607 0 0
T6 357527 22393 0 0
T7 2788 0 0 0
T9 108681 9291 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 134396 0 0
T24 0 10 0 0
T25 0 7 0 0
T39 98613 9347 0 0
T53 0 19 0 0
T55 1501 0 0 0
T56 1832 0 0 0
T66 0 18 0 0
T67 0 574 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 105824147 0 0
T5 54052 53575 0 0
T6 357527 357041 0 0
T7 2788 0 0 0
T9 108681 108176 0 0
T13 3355 0 0 0
T17 1724 0 0 0
T18 32131 0 0 0
T20 0 466054 0 0
T24 0 1680 0 0
T25 0 830 0 0
T39 98613 98138 0 0
T53 0 63114 0 0
T55 1501 0 0 0
T56 1832 0 0 0
T66 0 52694 0 0
T67 0 141002 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 11861 0 1008
T6 357527 268 0 1
T7 2788 0 0 1
T8 53201 0 0 1
T9 108681 127 0 1
T18 32131 0 0 1
T19 3411 0 0 1
T21 0 220 0 0
T39 98613 32 0 1
T55 1501 0 0 1
T56 1832 0 0 1
T61 228093 0 0 1
T71 0 112 0 0
T73 0 32 0 0
T105 0 315 0 0
T176 0 68 0 0
T178 0 71 0 0
T179 0 1096 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514486.27
Logical514486.27
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T61,T24
11CoveredT39,T61,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT39,T61,T24
111CoveredT39,T61,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT39,T61,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT39,T61,T24
01CoveredT39,T61,T24
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T61,T24
11CoveredT39,T61,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT39,T61,T24

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT39,T61,T24
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT39,T61,T24

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 371928390 371038203 0 0
CheckNGreaterZero_A 1014 1014 0 0
GntImpliesReady_A 371928390 15624127 0 0
GntImpliesValid_A 371928390 15624127 0 0
GrantKnown_A 371928390 371038203 0 0
IdxKnown_A 371928390 371038203 0 0
IndexIsCorrect_A 371928390 15624127 0 0
LockArbDecision_A 371928390 15624127 0 0
NoReadyValidNoGrant_A 371928390 339789944 0 0
ReadyAndValidImplyGrant_A 371928390 15624127 0 0
ReqAndReadyImplyGrant_A 371928390 15624127 0 0
ReqImpliesValid_A 371928390 31248259 0 0
ReqStaysHighUntilGranted0_M 371928390 15624127 0 0
RoundRobin_A 371928390 0 0 1008
ValidKnown_A 371928390 371038203 0 0
gen_data_port_assertion.DataFlow_A 371928390 15624127 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 339789944 0 0
T1 1110 745 0 0
T2 481682 481488 0 0
T3 3245 2362 0 0
T4 57016 55941 0 0
T5 54052 53300 0 0
T6 357527 356412 0 0
T9 108681 103575 0 0
T13 3355 2315 0 0
T17 1724 1590 0 0
T18 32131 31520 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 31248259 0 0
T1 1110 130 0 0
T2 481682 64 0 0
T3 3245 208 0 0
T4 57016 1024 0 0
T5 54052 680 0 0
T6 357527 1042 0 0
T9 108681 5008 0 0
T13 3355 288 0 0
T17 1724 64 0 0
T18 32131 512 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 1008

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514486.27
Logical514486.27
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T61,T24
11CoveredT39,T61,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT39,T61,T24
111CoveredT39,T61,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT39,T61,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT39,T61,T24
01CoveredT39,T61,T24
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T61,T24
11CoveredT39,T61,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT39,T61,T24

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT39,T61,T24
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT39,T61,T24

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 371928390 371038203 0 0
CheckNGreaterZero_A 1014 1014 0 0
GntImpliesReady_A 371928390 15624127 0 0
GntImpliesValid_A 371928390 15624127 0 0
GrantKnown_A 371928390 371038203 0 0
IdxKnown_A 371928390 371038203 0 0
IndexIsCorrect_A 371928390 15624127 0 0
LockArbDecision_A 371928390 15624127 0 0
NoReadyValidNoGrant_A 371928390 339789944 0 0
ReadyAndValidImplyGrant_A 371928390 15624127 0 0
ReqAndReadyImplyGrant_A 371928390 15624127 0 0
ReqImpliesValid_A 371928390 31248259 0 0
ReqStaysHighUntilGranted0_M 371928390 15624127 0 0
RoundRobin_A 371928390 0 0 1008
ValidKnown_A 371928390 371038203 0 0
gen_data_port_assertion.DataFlow_A 371928390 15624127 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 339789944 0 0
T1 1110 745 0 0
T2 481682 481488 0 0
T3 3245 2362 0 0
T4 57016 55941 0 0
T5 54052 53300 0 0
T6 357527 356412 0 0
T9 108681 103575 0 0
T13 3355 2315 0 0
T17 1724 1590 0 0
T18 32131 31520 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 31248259 0 0
T1 1110 130 0 0
T2 481682 64 0 0
T3 3245 208 0 0
T4 57016 1024 0 0
T5 54052 680 0 0
T6 357527 1042 0 0
T9 108681 5008 0 0
T13 3355 288 0 0
T17 1724 64 0 0
T18 32131 512 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 1008

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 15624127 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 340 0 0
T6 357527 521 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 unreachable
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T39,T61
11CoveredT5,T39,T61

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT5,T39,T26
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT5,T39,T26
110CoveredT5,T39,T61
111UnreachableT5,T39,T61

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T39,T61
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T39,T61
01CoveredT5,T39,T61
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT5,T39,T61
11CoveredT5,T39,T61

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T39,T26
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT5,T39,T26
10CoveredT1,T2,T3
11CoveredT5,T39,T61

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T39,T61
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T39,T61

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 371928390 371038203 0 0
CheckNGreaterZero_A 1014 1014 0 0
GntImpliesReady_A 371928390 16764933 0 0
GntImpliesValid_A 371928390 16764933 0 0
GrantKnown_A 371928390 371038203 0 0
IdxKnown_A 371928390 371038203 0 0
IndexIsCorrect_A 371928390 16764933 0 0
LockArbDecision_A 371928317 16764933 0 0
NoReadyValidNoGrant_A 371928390 337508257 0 0
ReadyAndValidImplyGrant_A 371928390 16764933 0 0
ReqAndReadyImplyGrant_A 371928390 16764933 0 0
ReqImpliesValid_A 371928390 33529946 0 0
ReqStaysHighUntilGranted0_M 371906883 16764760 0 0
RoundRobin_A 371928390 0 0 1008
ValidKnown_A 371928390 371038203 0 0
gen_data_port_assertion.DataFlow_A 371928390 16764933 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928317 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 337508257 0 0
T1 1110 745 0 0
T2 481682 481488 0 0
T3 3245 2362 0 0
T4 57016 55941 0 0
T5 54052 13730 0 0
T6 357527 331884 0 0
T9 108681 103575 0 0
T13 3355 2315 0 0
T17 1724 1590 0 0
T18 32131 31520 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 33529946 0 0
T1 1110 130 0 0
T2 481682 64 0 0
T3 3245 208 0 0
T4 57016 1024 0 0
T5 54052 40250 0 0
T6 357527 25570 0 0
T9 108681 5008 0 0
T13 3355 288 0 0
T17 1724 64 0 0
T18 32131 512 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 371906883 16764760 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 1008

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 unreachable
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T39,T61
11CoveredT5,T39,T61

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT5,T39,T26
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT5,T39,T26
110CoveredT5,T39,T61
111UnreachableT5,T39,T61

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT5,T39,T61
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT5,T39,T61
01CoveredT5,T39,T61
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT5,T39,T61
11CoveredT5,T39,T61

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T39,T26
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT5,T39,T26
10CoveredT1,T2,T3
11CoveredT5,T39,T61

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T39,T61
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T39,T61

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 371928390 371038203 0 0
CheckNGreaterZero_A 1014 1014 0 0
GntImpliesReady_A 371928390 16764933 0 0
GntImpliesValid_A 371928390 16764933 0 0
GrantKnown_A 371928390 371038203 0 0
IdxKnown_A 371928390 371038203 0 0
IndexIsCorrect_A 371928390 16764933 0 0
LockArbDecision_A 371928317 16764933 0 0
NoReadyValidNoGrant_A 371928390 337508329 0 0
ReadyAndValidImplyGrant_A 371928390 16764933 0 0
ReqAndReadyImplyGrant_A 371928390 16764933 0 0
ReqImpliesValid_A 371928390 33529874 0 0
ReqStaysHighUntilGranted0_M 371906883 16764760 0 0
RoundRobin_A 371928390 0 0 1008
ValidKnown_A 371928390 371038203 0 0
gen_data_port_assertion.DataFlow_A 371928390 16764933 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1014 1014 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928317 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 337508329 0 0
T1 1110 745 0 0
T2 481682 481488 0 0
T3 3245 2362 0 0
T4 57016 55941 0 0
T5 54052 13730 0 0
T6 357527 331884 0 0
T9 108681 103575 0 0
T13 3355 2315 0 0
T17 1724 1590 0 0
T18 32131 31520 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 33529874 0 0
T1 1110 130 0 0
T2 481682 64 0 0
T3 3245 208 0 0
T4 57016 1024 0 0
T5 54052 40250 0 0
T6 357527 25570 0 0
T9 108681 5008 0 0
T13 3355 288 0 0
T17 1724 64 0 0
T18 32131 512 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 371906883 16764760 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 0 0 1008

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 371038203 0 0
T1 1110 875 0 0
T2 481682 481552 0 0
T3 3245 2570 0 0
T4 57016 56965 0 0
T5 54052 53980 0 0
T6 357527 357454 0 0
T9 108681 108583 0 0
T13 3355 2603 0 0
T17 1724 1654 0 0
T18 32131 32032 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 371928390 16764933 0 0
T1 1110 65 0 0
T2 481682 32 0 0
T3 3245 104 0 0
T4 57016 512 0 0
T5 54052 20125 0 0
T6 357527 12785 0 0
T9 108681 2504 0 0
T13 3355 144 0 0
T17 1724 32 0 0
T18 32131 256 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%