Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.63	100.00	90.53			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.47	100.00	89.87			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.63	100.00	90.53			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.47	100.00	89.87			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.57	99.17	93.18	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.63	100.00	90.53			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	99.17	93.43	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	454	411	90.53
Logical	454	411	90.53
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.85
706-710	66.67

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T55,T24,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T55,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	743856780	1567435	0	0
ExclusiveOps_A	743856780	742076406	0	0
ExclusiveProgHazard_A	743856780	742076406	0	0
ExclusiveState_A	743856780	742076406	0	0
ForwardCheck_A	743856780	3776882	0	0
IdleCheck_A	743856780	100993019	0	0
MaxBufs_A	2028	2028	0	0
OneHotAlloc_A	743856780	742076406	0	0
OneHotMatch_A	743856780	742076406	0	0
OneHotRspMatch_A	743856780	742076406	0	0
OneHotUpdate_A	743856780	742076406	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	1567435	0	0
T4	57016	768	0	0
T5	108104	2098	0	0
T6	715054	2765	0	0
T7	5576	3	0	0
T8	0	256	0	0
T9	217362	601	0	0
T13	6710	0	0	0
T17	3448	0	0	0
T18	64262	256	0	0
T20	0	134400	0	0
T24	0	21	0	0
T25	0	6	0	0
T26	0	5967	0	0
T39	197226	1417	0	0
T54	0	5	0	0
T55	3002	0	0	0
T56	1832	0	0	0
T67	0	567	0	0
T86	0	530	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	3776882	0	0
T4	57016	288	0	0
T5	108104	19785	0	0
T6	715054	45630	0	0
T7	5576	5	0	0
T8	0	288	0	0
T9	217362	14583	0	0
T13	6710	0	0	0
T17	3448	0	0	0
T18	64262	32	0	0
T20	0	134400	0	0
T26	0	501	0	0
T34	0	15050	0	0
T39	197226	0	0	0
T53	0	41	0	0
T54	0	5	0	0
T55	3002	0	0	0
T56	1832	0	0	0
T66	0	42	0	0
T67	0	578	0	0
T86	0	530	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	100993019	0	0
T1	1110	260	0	0
T2	481682	128	0	0
T3	3245	416	0	0
T4	57016	3392	0	0
T5	108104	43175	0	0
T6	715054	143103	0	0
T7	2788	0	0	0
T9	217362	59591	0	0
T13	6710	576	0	0
T17	3448	128	0	0
T18	64262	1344	0	0
T20	0	403200	0	0
T24	0	63	0	0
T25	0	50	0	0
T39	98613	35635	0	0
T53	0	46	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T66	0	44	0	0
T67	0	1723	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2028	2028	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T9	2	2	0	0
T13	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743856780	742076406	0	0
T1	2220	1750	0	0
T2	963364	963104	0	0
T3	6490	5140	0	0
T4	114032	113930	0	0
T5	108104	107960	0	0
T6	715054	714908	0	0
T9	217362	217166	0	0
T13	6710	5206	0	0
T17	3448	3308	0	0
T18	64262	64064	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	454	408	89.87
Logical	454	408	89.87
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	89.80
710	100.00

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T21,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T39,T24,T25
0	1	Covered	T5,T59,T176
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T9
0	1	Covered	T39,T24,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T9
0	1	Covered	T39,T24,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T21,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T9
0	0	1	Covered	T5,T6,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T39,T24
0	0	1	Covered	T5,T39,T24
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	371928390	1019820	0	0
ExclusiveOps_A	371928390	371038203	0	0
ExclusiveProgHazard_A	371928390	371038203	0	0
ExclusiveState_A	371928390	371038203	0	0
ForwardCheck_A	371928390	2048872	0	0
IdleCheck_A	371928390	49900598	0	0
MaxBufs_A	1014	1014	0	0
OneHotAlloc_A	371928390	371038203	0	0
OneHotMatch_A	371928390	371038203	0	0
OneHotRspMatch_A	371928390	371038203	0	0
OneHotUpdate_A	371928390	371038203	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	1019820	0	0
T5	54052	852	0	0
T6	357527	834	0	0
T7	2788	0	0	0
T9	108681	469	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T20	0	134400	0	0
T24	0	7	0	0
T25	0	6	0	0
T26	0	5967	0	0
T39	98613	486	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T67	0	567	0	0
T86	0	530	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	2048872	0	0
T5	54052	9611	0	0
T6	357527	21928	0	0
T7	2788	0	0	0
T9	108681	9084	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T20	0	134400	0	0
T26	0	501	0	0
T34	0	15050	0	0
T39	98613	0	0	0
T53	0	23	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T66	0	22	0	0
T67	0	578	0	0
T86	0	530	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	49900598	0	0
T5	54052	20074	0	0
T6	357527	65326	0	0
T7	2788	0	0	0
T9	108681	30606	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	0	0	0
T20	0	403200	0	0
T24	0	63	0	0
T25	0	50	0	0
T39	98613	35635	0	0
T53	0	46	0	0
T55	1501	0	0	0
T56	1832	0	0	0
T66	0	44	0	0
T67	0	1723	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	454	411	90.53
Logical	454	411	90.53
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.85
706-710	66.67

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T55,T25,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T55,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	371928390	547615	0	0
ExclusiveOps_A	371928390	371038203	0	0
ExclusiveProgHazard_A	371928390	371038203	0	0
ExclusiveState_A	371928390	371038203	0	0
ForwardCheck_A	371928390	1728010	0	0
IdleCheck_A	371928390	51092421	0	0
MaxBufs_A	1014	1014	0	0
OneHotAlloc_A	371928390	371038203	0	0
OneHotMatch_A	371928390	371038203	0	0
OneHotRspMatch_A	371928390	371038203	0	0
OneHotUpdate_A	371928390	371038203	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	547615	0	0
T4	57016	768	0	0
T5	54052	1246	0	0
T6	357527	1931	0	0
T7	2788	3	0	0
T8	0	256	0	0
T9	108681	132	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	256	0	0
T24	0	14	0	0
T39	98613	931	0	0
T54	0	5	0	0
T55	1501	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	1728010	0	0
T4	57016	288	0	0
T5	54052	10174	0	0
T6	357527	23702	0	0
T7	2788	5	0	0
T8	0	288	0	0
T9	108681	5499	0	0
T13	3355	0	0	0
T17	1724	0	0	0
T18	32131	32	0	0
T39	98613	0	0	0
T53	0	18	0	0
T54	0	5	0	0
T55	1501	0	0	0
T66	0	20	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	51092421	0	0
T1	1110	260	0	0
T2	481682	128	0	0
T3	3245	416	0	0
T4	57016	3392	0	0
T5	54052	23101	0	0
T6	357527	77777	0	0
T9	108681	28985	0	0
T13	3355	576	0	0
T17	1724	128	0	0
T18	32131	1344	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1014	1014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371928390	371038203	0	0
T1	1110	875	0	0
T2	481682	481552	0	0
T3	3245	2570	0	0
T4	57016	56965	0	0
T5	54052	53980	0	0
T6	357527	357454	0	0
T9	108681	108583	0	0
T13	3355	2603	0	0
T17	1724	1654	0	0
T18	32131	32032	0	0