Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T12

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1654606492	1651569960	0	0
CheckNGreaterZero_A	4108	4108	0	0
GntImpliesReady_A	1654606492	413024689	0	0
GntImpliesValid_A	1654606492	413024689	0	0
GrantKnown_A	1654606492	1651569960	0	0
IdxKnown_A	1654606492	1651569960	0	0
IndexIsCorrect_A	1654606492	413024689	0	0
NoReadyValidNoGrant_A	1654606492	179863831	0	0
Priority_A	1654606492	436948756	0	0
ReadyAndValidImplyGrant_A	1654606492	413024689	0	0
ReqAndReadyImplyGrant_A	1654606492	413024689	0	0
ReqImpliesValid_A	1654606492	436948756	0	0
ValidKnown_A	1654606492	1651569960	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	1651569960	0	0
T1	1618168	1617864	0	0
T2	5620	5276	0	0
T3	14408	11800	0	0
T4	688156	687812	0	0
T5	41164	40576	0	0
T12	2952	2732	0	0
T17	281088	280708	0	0
T18	126792	126448	0	0
T19	446676	446356	0	0
T20	7244	6896	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4108	4108	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	413024689	0	0
T1	1618168	507620	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	175308	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	413024689	0	0
T1	1618168	507620	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	175308	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	1651569960	0	0
T1	1618168	1617864	0	0
T2	5620	5276	0	0
T3	14408	11800	0	0
T4	688156	687812	0	0
T5	41164	40576	0	0
T12	2952	2732	0	0
T17	281088	280708	0	0
T18	126792	126448	0	0
T19	446676	446356	0	0
T20	7244	6896	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	1651569960	0	0
T1	1618168	1617864	0	0
T2	5620	5276	0	0
T3	14408	11800	0	0
T4	688156	687812	0	0
T5	41164	40576	0	0
T12	2952	2732	0	0
T17	281088	280708	0	0
T18	126792	126448	0	0
T19	446676	446356	0	0
T20	7244	6896	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	413024689	0	0
T1	1618168	507620	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	175308	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	179863831	0	0
T1	1618168	194818	0	0
T2	5620	256	0	0
T3	14408	1564	0	0
T4	688156	128	0	0
T5	41164	1084	0	0
T6	0	1232	0	0
T7	0	96534	0	0
T12	2952	304	0	0
T17	281088	12900	0	0
T18	126792	256	0	0
T19	446676	6784	0	0
T20	7244	314	0	0
T31	0	20	0	0
T33	0	54	0	0
T56	0	38	0	0
T57	0	414	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	436948756	0	0
T1	1618168	649736	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	226754	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	413024689	0	0
T1	1618168	507620	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	175308	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	413024689	0	0
T1	1618168	507620	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	175308	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	436948756	0	0
T1	1618168	649736	0	0
T2	5620	64	0	0
T3	14408	428	0	0
T4	688156	27210	0	0
T5	41164	16072	0	0
T6	0	298304	0	0
T7	0	226754	0	0
T12	2952	82	0	0
T17	281088	102006	0	0
T18	126792	39738	0	0
T19	446676	143936	0	0
T20	7244	102	0	0
T31	0	500	0	0
T32	0	210112	0	0
T33	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654606492	1651569960	0	0
T1	1618168	1617864	0	0
T2	5620	5276	0	0
T3	14408	11800	0	0
T4	688156	687812	0	0
T5	41164	40576	0	0
T12	2952	2732	0	0
T17	281088	280708	0	0
T18	126792	126448	0	0
T19	446676	446356	0	0
T20	7244	6896	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413651623	412892490	0	0
CheckNGreaterZero_A	1027	1027	0	0
GntImpliesReady_A	413651623	108739508	0	0
GntImpliesValid_A	413651623	108739508	0	0
GrantKnown_A	413651623	412892490	0	0
IdxKnown_A	413651623	412892490	0	0
IndexIsCorrect_A	413651623	108739508	0	0
NoReadyValidNoGrant_A	413651623	46477338	0	0
Priority_A	413651623	114719002	0	0
ReadyAndValidImplyGrant_A	413651623	108739508	0	0
ReqAndReadyImplyGrant_A	413651623	108739508	0	0
ReqImpliesValid_A	413651623	114719002	0	0
ValidKnown_A	413651623	412892490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739508	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739508	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739508	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	46477338	0	0
T1	404542	45247	0	0
T2	1405	128	0	0
T3	3602	782	0	0
T4	172039	64	0	0
T5	10291	481	0	0
T12	738	152	0	0
T17	70272	3374	0	0
T18	31698	128	0	0
T19	111669	3392	0	0
T20	1811	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	114719002	0	0
T1	404542	138620	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739508	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739508	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	114719002	0	0
T1	404542	138620	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413651623	412892490	0	0
CheckNGreaterZero_A	1027	1027	0	0
GntImpliesReady_A	413651623	108739502	0	0
GntImpliesValid_A	413651623	108739502	0	0
GrantKnown_A	413651623	412892490	0	0
IdxKnown_A	413651623	412892490	0	0
IndexIsCorrect_A	413651623	108739502	0	0
NoReadyValidNoGrant_A	413651623	46477332	0	0
Priority_A	413651623	114719002	0	0
ReadyAndValidImplyGrant_A	413651623	108739502	0	0
ReqAndReadyImplyGrant_A	413651623	108739502	0	0
ReqImpliesValid_A	413651623	114719002	0	0
ValidKnown_A	413651623	412892490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739502	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739502	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739502	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	46477332	0	0
T1	404542	45247	0	0
T2	1405	128	0	0
T3	3602	782	0	0
T4	172039	64	0	0
T5	10291	481	0	0
T12	738	152	0	0
T17	70272	3374	0	0
T18	31698	128	0	0
T19	111669	3392	0	0
T20	1811	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	114719002	0	0
T1	404542	138620	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739502	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	108739502	0	0
T1	404542	107551	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	114719002	0	0
T1	404542	138620	0	0
T2	1405	32	0	0
T3	3602	214	0	0
T4	172039	13605	0	0
T5	10291	4344	0	0
T12	738	41	0	0
T17	70272	33182	0	0
T18	31698	9949	0	0
T19	111669	71968	0	0
T20	1811	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T17
1	0	Covered	T1,T5,T31

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T31
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T31
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T33
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T5,T31

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T31
1	1	Covered	T1,T5,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T33
1	1	Covered	T1,T5,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T31

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T31

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413651623	412892490	0	0
CheckNGreaterZero_A	1027	1027	0	0
GntImpliesReady_A	413651623	97772800	0	0
GntImpliesValid_A	413651623	97772800	0	0
GrantKnown_A	413651623	412892490	0	0
IdxKnown_A	413651623	412892490	0	0
IndexIsCorrect_A	413651623	97772800	0	0
NoReadyValidNoGrant_A	413651623	43454584	0	0
Priority_A	413651623	103755333	0	0
ReadyAndValidImplyGrant_A	413651623	97772800	0	0
ReqAndReadyImplyGrant_A	413651623	97772800	0	0
ReqImpliesValid_A	413651623	103755333	0	0
ValidKnown_A	413651623	412892490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772800	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772800	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772800	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	43454584	0	0
T1	404542	52162	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	61	0	0
T6	0	616	0	0
T7	0	48267	0	0
T12	738	0	0	0
T17	70272	3076	0	0
T18	31698	0	0	0
T19	111669	0	0	0
T20	1811	29	0	0
T31	0	10	0	0
T33	0	27	0	0
T56	0	19	0	0
T57	0	207	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	103755333	0	0
T1	404542	186248	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	113377	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772800	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772800	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	103755333	0	0
T1	404542	186248	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	113377	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T17
1	0	Covered	T1,T5,T31

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T31
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T31
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T33
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T5,T31

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T31
1	1	Covered	T1,T5,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T33
1	1	Covered	T1,T5,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T31

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T31

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413651623	412892490	0	0
CheckNGreaterZero_A	1027	1027	0	0
GntImpliesReady_A	413651623	97772879	0	0
GntImpliesValid_A	413651623	97772879	0	0
GrantKnown_A	413651623	412892490	0	0
IdxKnown_A	413651623	412892490	0	0
IndexIsCorrect_A	413651623	97772879	0	0
NoReadyValidNoGrant_A	413651623	43454577	0	0
Priority_A	413651623	103755419	0	0
ReadyAndValidImplyGrant_A	413651623	97772879	0	0
ReqAndReadyImplyGrant_A	413651623	97772879	0	0
ReqImpliesValid_A	413651623	103755419	0	0
ValidKnown_A	413651623	412892490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772879	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772879	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772879	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	43454577	0	0
T1	404542	52162	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	61	0	0
T6	0	616	0	0
T7	0	48267	0	0
T12	738	0	0	0
T17	70272	3076	0	0
T18	31698	0	0	0
T19	111669	0	0	0
T20	1811	29	0	0
T31	0	10	0	0
T33	0	27	0	0
T56	0	19	0	0
T57	0	207	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	103755419	0	0
T1	404542	186248	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	113377	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772879	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	97772879	0	0
T1	404542	146259	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	87654	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	103755419	0	0
T1	404542	186248	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	3692	0	0
T6	0	149152	0	0
T7	0	113377	0	0
T12	738	0	0	0
T17	70272	17821	0	0
T18	31698	9920	0	0
T19	111669	0	0	0
T20	1811	19	0	0
T31	0	250	0	0
T32	0	105056	0	0
T33	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0