Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
 gen_flash_cores[0].u_core 97.84 96.90 93.35 100.00 100.00 98.86 97.94
 gen_flash_cores[0].u_host_rsp_fifo 90.93 100.00 82.98 80.00 91.67 100.00
 gen_flash_cores[1].u_core 97.23 96.90 92.78 96.90 100.00 98.86 97.94
 gen_flash_cores[1].u_host_rsp_fifo 90.08 100.00 78.72 80.00 91.67 100.00
 u_bank_sequence_fifo 96.53 100.00 86.11 100.00 100.00
 u_disable_buf 100.00 100.00 100.00
 u_flash 97.75 98.80 94.58 100.00 93.75 99.37 100.00
 u_lc_nvm_debug_en_sync 100.00 100.00 100.00 100.00
u_region_sel 100.00 100.00 100.00 100.00
 u_scramble 97.71 100.00 94.63 100.00 100.00 93.94