Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.68	100.00	90.57		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T29,T10
1	0	Covered	T9,T29,T10

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T9,T29,T10

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T29,T10
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T18,T6,T56

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T18,T6,T57

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14
1	Covered	T18,T6,T57

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T18,T6,T56

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14
1	Covered	T18,T6,T56

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T18,T19
1	Covered	T1,T17,T19

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T19
1	1	Covered	T1,T17,T19

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T19
1	1	Covered	T1,T17,T19

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T17
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T4,T17

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T17,T19
StCalcMask	237	Covered	T1,T17,T19
StCalcPlainEcc	215	Covered	T1,T4,T17
StDisabled	193	Covered	T12,T13,T9
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T17
StPostPack	218	Covered	T18,T6,T56
StPrePack	195	Covered	T18,T6,T57
StReqFlash	237	Covered	T1,T4,T17
StScrambleData	244	Covered	T1,T17,T19
StWaitFlash	270	Covered	T1,T4,T17

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T17,T19
StCalcMask->StScrambleData	244	Covered	T1,T17,T19
StCalcPlainEcc->StCalcMask	237	Covered	T1,T17,T19
StCalcPlainEcc->StReqFlash	237	Covered	T4,T18,T19
StIdle->StDisabled	193	Covered	T12,T13,T9
StIdle->StPackData	197	Covered	T1,T4,T17
StIdle->StPrePack	195	Covered	T18,T6,T57
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T17
StPackData->StPostPack	218	Covered	T18,T6,T56
StPostPack->StCalcPlainEcc	231	Covered	T18,T6,T56
StPrePack->StPackData	205	Covered	T18,T6,T57
StReqFlash->StIdle	273	Covered	T1,T4,T17
StReqFlash->StWaitFlash	270	Covered	T1,T4,T17
StScrambleData->StCalcEcc	252	Covered	T1,T17,T19
StWaitFlash->StIdle	280	Covered	T1,T4,T17

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T17
0	0	1	Covered	T1,T4,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T9
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T56
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T18,T6,T56
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T17,T19
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T18,T19
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T17,T19
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T17,T19
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T17,T19
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T17,T19
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T4,T17
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T17
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T17
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T17
0	0	1	-	-	Covered	T1,T17,T19
0	0	0	1	-	Covered	T1,T17,T19
0	0	0	0	1	Covered	T1,T4,T17
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	827303246	2445948	0	0
PostPackRule_A	827303246	1845	0	0
PrePackRule_A	827303246	1269	0	0
WidthCheck_A	2054	2054	0	0
u_state_regs_A	827303246	825784980	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827303246	2445948	0	0
T1	809084	1865	0	0
T2	2810	0	0	0
T3	7204	0	0	0
T4	344078	32	0	0
T5	20582	0	0	0
T6	0	74	0	0
T7	0	1437	0	0
T12	1476	0	0	0
T17	140544	240	0	0
T18	63396	53	0	0
T19	223338	160	0	0
T20	3622	0	0	0
T31	0	8	0	0
T32	0	1504	0	0
T33	0	2	0	0
T56	0	1	0	0
T57	0	12	0	0
T99	0	5	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827303246	1845	0	0
T6	869674	54	0	0
T7	679082	0	0	0
T12	1476	0	0	0
T13	6866	0	0	0
T18	63396	33	0	0
T19	223338	0	0	0
T20	3622	0	0	0
T25	0	5	0	0
T31	5296	0	0	0
T32	400408	0	0	0
T48	2006	0	0	0
T56	0	1	0	0
T57	0	10	0	0
T59	0	2	0	0
T72	0	6	0	0
T83	0	5	0	0
T99	0	2	0	0
T166	0	50	0	0
T219	0	3	0	0
T220	0	1	0	0
T221	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827303246	1269	0	0
T6	869674	31	0	0
T7	679082	0	0	0
T12	1476	0	0	0
T13	6866	0	0	0
T18	63396	24	0	0
T19	223338	0	0	0
T20	3622	0	0	0
T25	0	3	0	0
T31	5296	0	0	0
T32	400408	0	0	0
T48	2006	0	0	0
T57	0	10	0	0
T59	0	2	0	0
T72	0	6	0	0
T83	0	6	0	0
T99	0	5	0	0
T104	0	6	0	0
T162	0	1	0	0
T166	0	31	0	0
T219	0	3	0	0
T221	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2054	2054	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T12	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827303246	825784980	0	0
T1	809084	808932	0	0
T2	2810	2638	0	0
T3	7204	5900	0	0
T4	344078	343906	0	0
T5	20582	20288	0	0
T12	1476	1366	0	0
T17	140544	140354	0	0
T18	63396	63224	0	0
T19	223338	223178	0	0
T20	3622	3448	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T29,T10
1	0	Covered	T9,T29,T10

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T9,T29,T10

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T29,T10
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T18,T6,T57

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T18,T6,T57

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14
1	Covered	T18,T6,T57

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T18,T6,T57

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14
1	Covered	T18,T6,T57

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T18,T19
1	Covered	T1,T17,T19

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T19
1	1	Covered	T1,T17,T19

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T19
1	1	Covered	T1,T17,T19

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T17
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T4,T17

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T17,T19
StCalcMask	237	Covered	T1,T17,T19
StCalcPlainEcc	215	Covered	T1,T4,T17
StDisabled	193	Covered	T12,T13,T9
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T17
StPostPack	218	Covered	T18,T6,T57
StPrePack	195	Covered	T18,T6,T57
StReqFlash	237	Covered	T1,T4,T17
StScrambleData	244	Covered	T1,T17,T19
StWaitFlash	270	Covered	T1,T4,T17

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T17,T19
StCalcMask->StScrambleData	244	Covered	T1,T17,T19
StCalcPlainEcc->StCalcMask	237	Covered	T1,T17,T19
StCalcPlainEcc->StReqFlash	237	Covered	T4,T18,T19
StIdle->StDisabled	193	Covered	T12,T13,T9
StIdle->StPackData	197	Covered	T1,T4,T17
StIdle->StPrePack	195	Covered	T18,T6,T57
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T17
StPackData->StPostPack	218	Covered	T18,T6,T57
StPostPack->StCalcPlainEcc	231	Covered	T18,T6,T57
StPrePack->StPackData	205	Covered	T18,T6,T57
StReqFlash->StIdle	273	Covered	T1,T4,T17
StReqFlash->StWaitFlash	270	Covered	T1,T4,T17
StScrambleData->StCalcEcc	252	Covered	T1,T17,T19
StWaitFlash->StIdle	280	Covered	T1,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T17
0	0	1	Covered	T1,T4,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T9
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T18,T6,T57
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T17,T19
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T18,T19
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T17,T19
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T17,T19
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T17,T19
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T17,T19
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T4,T17
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T17
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T17
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T17
0	0	1	-	-	Covered	T1,T17,T19
0	0	0	1	-	Covered	T1,T17,T19
0	0	0	0	1	Covered	T1,T4,T17
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	413651623	1237303	0	0
PostPackRule_A	413651623	938	0	0
PrePackRule_A	413651623	639	0	0
WidthCheck_A	1027	1027	0	0
u_state_regs_A	413651623	412892490	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	1237303	0	0
T1	404542	795	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	32	0	0
T5	10291	0	0	0
T6	0	34	0	0
T7	0	791	0	0
T12	738	0	0	0
T17	70272	162	0	0
T18	31698	26	0	0
T19	111669	160	0	0
T20	1811	0	0	0
T31	0	4	0	0
T32	0	734	0	0
T33	0	2	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	938	0	0
T6	434837	25	0	0
T7	339541	0	0	0
T12	738	0	0	0
T13	3433	0	0	0
T18	31698	17	0	0
T19	111669	0	0	0
T20	1811	0	0	0
T31	2648	0	0	0
T32	200204	0	0	0
T48	1003	0	0	0
T57	0	3	0	0
T59	0	2	0	0
T83	0	1	0	0
T99	0	1	0	0
T166	0	33	0	0
T219	0	3	0	0
T220	0	1	0	0
T221	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	639	0	0
T6	434837	19	0	0
T7	339541	0	0	0
T12	738	0	0	0
T13	3433	0	0	0
T18	31698	13	0	0
T19	111669	0	0	0
T20	1811	0	0	0
T25	0	2	0	0
T31	2648	0	0	0
T32	200204	0	0	0
T48	1003	0	0	0
T57	0	5	0	0
T59	0	2	0	0
T72	0	4	0	0
T83	0	2	0	0
T166	0	21	0	0
T219	0	3	0	0
T221	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T179
1	0	Covered	T9,T10,T179

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T9,T10,T179

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T179
1	0	Covered	T1,T5,T17

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T18,T6,T56

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T17,T18

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T18,T6,T57

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14
1	Covered	T18,T6,T57

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T17,T18

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T17,T18

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T17,T18
1	1	Covered	T18,T6,T56

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14
1	Covered	T18,T6,T56

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T18,T32,T6
1	Covered	T1,T17,T7

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T17,T18

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T17,T18

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T17,T18

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T7
1	0	Covered	T1,T17,T7
1	1	Covered	T1,T17,T7

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T7
1	0	Covered	T1,T17,T7
1	1	Covered	T1,T17,T7

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T17,T18
1	1	0	Covered	T1,T17,T18
1	1	1	Covered	T1,T17,T18

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T17,T7
StCalcMask	237	Covered	T1,T17,T7
StCalcPlainEcc	215	Covered	T1,T17,T18
StDisabled	193	Covered	T12,T13,T9
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T17,T18
StPostPack	218	Covered	T18,T6,T56
StPrePack	195	Covered	T18,T6,T57
StReqFlash	237	Covered	T1,T17,T18
StScrambleData	244	Covered	T1,T17,T7
StWaitFlash	270	Covered	T1,T17,T18

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T17,T7
StCalcMask->StScrambleData	244	Covered	T1,T17,T7
StCalcPlainEcc->StCalcMask	237	Covered	T1,T17,T7
StCalcPlainEcc->StReqFlash	237	Covered	T18,T32,T6
StIdle->StDisabled	193	Covered	T12,T13,T9
StIdle->StPackData	197	Covered	T1,T17,T18
StIdle->StPrePack	195	Covered	T18,T6,T57
StPackData->StCalcPlainEcc	215	Covered	T1,T17,T18
StPackData->StPostPack	218	Covered	T18,T6,T56
StPostPack->StCalcPlainEcc	231	Covered	T18,T6,T56
StPrePack->StPackData	205	Covered	T18,T6,T57
StReqFlash->StIdle	273	Covered	T1,T17,T18
StReqFlash->StWaitFlash	270	Covered	T1,T17,T18
StScrambleData->StCalcEcc	252	Covered	T1,T17,T7
StWaitFlash->StIdle	280	Covered	T1,T17,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T17,T18
0	1	Covered	T1,T5,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T17,T18
0	0	1	Covered	T1,T17,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T9
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T57
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T6,T56
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T18,T6,T56
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T17,T7
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T18,T32,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T17,T7
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T17,T7
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T17,T7
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T17,T7
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T17,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T17,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T17,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T17,T18
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T17,T18
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T17,T18
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T17,T18
0	0	1	-	-	Covered	T1,T17,T7
0	0	0	1	-	Covered	T1,T17,T7
0	0	0	0	1	Covered	T1,T17,T18
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T17,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	413651623	1208645	0	0
PostPackRule_A	413651623	907	0	0
PrePackRule_A	413651623	630	0	0
WidthCheck_A	1027	1027	0	0
u_state_regs_A	413651623	412892490	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	1208645	0	0
T1	404542	1070	0	0
T2	1405	0	0	0
T3	3602	0	0	0
T4	172039	0	0	0
T5	10291	0	0	0
T6	0	40	0	0
T7	0	646	0	0
T12	738	0	0	0
T17	70272	78	0	0
T18	31698	27	0	0
T19	111669	0	0	0
T20	1811	0	0	0
T31	0	4	0	0
T32	0	770	0	0
T56	0	1	0	0
T57	0	12	0	0
T99	0	5	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	907	0	0
T6	434837	29	0	0
T7	339541	0	0	0
T12	738	0	0	0
T13	3433	0	0	0
T18	31698	16	0	0
T19	111669	0	0	0
T20	1811	0	0	0
T25	0	5	0	0
T31	2648	0	0	0
T32	200204	0	0	0
T48	1003	0	0	0
T56	0	1	0	0
T57	0	7	0	0
T72	0	6	0	0
T83	0	4	0	0
T99	0	1	0	0
T166	0	17	0	0
T221	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	630	0	0
T6	434837	12	0	0
T7	339541	0	0	0
T12	738	0	0	0
T13	3433	0	0	0
T18	31698	11	0	0
T19	111669	0	0	0
T20	1811	0	0	0
T25	0	1	0	0
T31	2648	0	0	0
T32	200204	0	0	0
T48	1003	0	0	0
T57	0	5	0	0
T72	0	2	0	0
T83	0	4	0	0
T99	0	5	0	0
T104	0	6	0	0
T162	0	1	0	0
T166	0	10	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413651623	412892490	0	0
T1	404542	404466	0	0
T2	1405	1319	0	0
T3	3602	2950	0	0
T4	172039	171953	0	0
T5	10291	10144	0	0
T12	738	683	0	0
T17	70272	70177	0	0
T18	31698	31612	0	0
T19	111669	111589	0	0
T20	1811	1724	0	0