Unified Coverage Report :: Module :: flash_phy

Module : flash_phy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56	97.67	86.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash	94.56	97.67	86.00			100.00

---

Module Instance : tb.dut.u_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56	97.67	86.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	98.05	92.94	98.46	97.62	99.17	97.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	97.12	95.20	98.44		100.00	98.57	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flash_cores[0].u_core	97.86	97.07	92.77	100.00	100.00	99.29	98.04
gen_flash_cores[0].u_host_rsp_fifo	90.93	100.00	82.98	80.00		91.67	100.00
gen_flash_cores[1].u_core	97.24	97.07	92.49	96.90	100.00	98.94	98.04
gen_flash_cores[1].u_host_rsp_fifo	90.08	100.00	78.72	80.00		91.67	100.00
u_bank_sequence_fifo	96.53	100.00	86.11			100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_flash	97.76	98.80	94.66	100.00	93.75	99.37	100.00
u_lc_nvm_debug_en_sync	100.00	100.00				100.00	100.00
u_region_sel	100.00	100.00	100.00			100.00
u_scramble	97.71	100.00	94.63	100.00		100.00	93.94

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_phy

	Line No.	Total	Covered	Percent
TOTAL		43	42	97.67
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	133	0	0
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	333	0	0
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	392	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	1	1
122	1	1
125	1	1
128	1	1
129	1	1
130	1	1
133		unreachable
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
147	1	1
178	9	9
193	1	1
199	1	1
201	1	1
211	1	1
212	1	1
230	2	2
254	2	2
255	2	2
333		unreachable
349	1	1
389	1	1
392	0	1

---

Cond Coverage for Module : flash_phy

	Total	Covered	Percent
Conditions	50	43	86.00
Logical	50	43	86.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       125
 EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
             -------------1-------------   --------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T21

 LINE       128
 EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
             --------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T47
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       145
 EXPRESSION (((|arb_err)) | scramble_arb_err)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T72,T73,T74
1	0	Covered	T75

 LINE       155
 EXPRESSION (host_req_i & host_req_rdy_o)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       230
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       230
 SUB-EXPRESSION (rsp_bank_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       230
 SUB-EXPRESSION (rsp_bank_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       254
 EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
             -----1----   ----------2---------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T18,T21
1	1	0	Covered	T7,T59,T76
1	1	1	Covered	T4,T18,T21

 LINE       254
 SUB-EXPRESSION (host_bank_sel == 0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
             -----1----   ----------2---------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T18,T21
1	1	0	Covered	T7,T8,T59
1	1	1	Covered	T4,T18,T21

 LINE       254
 SUB-EXPRESSION (host_bank_sel == 1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       255
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (ctrl_bank_sel == 0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       255
 SUB-EXPRESSION (ctrl_bank_sel == 1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       389
 EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : flash_phy

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	121	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	121	(host_req_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3