Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	95.28		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.55	100.00	84.91		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	98.87	100.00	94.34		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	84.91		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	97.07	92.49	96.90	100.00	98.94	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.13	97.64	92.74	100.00		98.73	96.55
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.87	100.00	94.34		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	97.07	92.77	100.00	100.00	99.29	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.49	100.00	96.92	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.09	97.64	92.50	100.00		98.73	96.55
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	588	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
524	1	1
551	1	1
552	1	1
553	1	1
554	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
562	1	1
569	1	1
586	1	1
587	1	1
588	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	101	95.28
Logical	106	101	95.28
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T155,T230,T211

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T155,T230,T211

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T21

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T6,T7
1	0	1	Covered	T4,T18,T21
1	1	0	Covered	T45,T46,T47
1	1	1	Covered	T4,T18,T21

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T75
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T21

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T6,T7

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T11
1	1	Covered	T2,T3,T4

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T46,T47
1	0	Covered	T20,T231

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T231

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T47

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T35,T57
1	0	Covered	T2,T3,T11

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T155

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T155
1	1	Covered	T155

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T155

 LINE       524
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15
1	0	Covered	T14,T15

 LINE       551
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T29

 LINE       552
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T29

 LINE       553
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T29

 LINE       554
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T29

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T2,T3,T11
StCtrlProg	339	Covered	T2,T3,T4
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T1,T5,T11
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T2,T3,T11
StCtrlProg->StIdle	359	Covered	T2,T3,T4
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T2,T3,T11
StIdle->StCtrlProg	339	Covered	T2,T3,T4
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T1,T5,T11

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	554	2	2	100.00
TERNARY	431	2	2	100.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T155
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T18,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T155,T230,T211
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T155,T12,T13
0	0	0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T5,T11
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	-	Covered	T2,T3,T11
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T4
StCtrl	-	-	-	-	-	-	1	Covered	T2,T3,T11
StCtrl	-	-	-	-	-	-	0	Covered	T2,T3,T11
StDisable	-	-	-	-	-	-	-	Covered	T1,T5,T11
default	-	-	-	-	-	-	-	Covered	T14,T15,T12

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	718995632	2733227	0	0
CtrlPrio_A	718995632	2733221	0	0
HostTransIdleChk_A	718995632	44425512	0	0
NoRemainder_A	2046	2046	0	0
OneHotReqs_A	718995632	717330982	0	0
Pow2Multiple_A	2046	2046	0	0
RdTxnCheck_A	718629658	716965008	0	0
u_state_regs_A	718995632	717330982	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	2733227	0	0
T6	120539	76426	0	0
T7	435006	21643	0	0
T8	563474	0	0	0
T18	73334	6300	0	0
T19	3743	0	0	0
T21	9820	0	0	0
T27	3671	0	0	0
T28	4060	0	0	0
T29	3189	0	0	0
T30	1860	0	0	0
T35	178944	0	0	0
T36	0	89095	0	0
T37	0	5184	0	0
T38	0	86005	0	0
T42	11343	0	0	0
T43	6197	0	0	0
T44	190840	0	0	0
T50	2278	0	0	0
T53	1753	0	0	0
T54	991	0	0	0
T55	192206	0	0	0
T59	316628	16863	0	0
T60	0	2130	0	0
T61	0	5969	0	0
T93	1797	0	0	0
T172	0	2211	0	0
T177	0	2220	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	2733221	0	0
T6	120539	76426	0	0
T7	435006	21643	0	0
T8	563474	0	0	0
T18	73334	6300	0	0
T19	3743	0	0	0
T21	9820	0	0	0
T27	3671	0	0	0
T28	4060	0	0	0
T29	3189	0	0	0
T30	1860	0	0	0
T35	178944	0	0	0
T36	0	89095	0	0
T37	0	5184	0	0
T38	0	86005	0	0
T42	11343	0	0	0
T43	6197	0	0	0
T44	190840	0	0	0
T50	2278	0	0	0
T53	1753	0	0	0
T54	991	0	0	0
T55	192206	0	0	0
T59	316628	16863	0	0
T60	0	2130	0	0
T61	0	5969	0	0
T93	1797	0	0	0
T172	0	2211	0	0
T177	0	2220	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	44425512	0	0
T4	4260	28	0	0
T5	2964	0	0	0
T6	0	839817	0	0
T7	0	90348	0	0
T11	1978	0	0	0
T16	1097316	0	0	0
T17	2498	0	0	0
T18	146668	57067	0	0
T19	7486	0	0	0
T21	19640	66	0	0
T29	6378	36	0	0
T30	0	16	0	0
T50	0	24	0	0
T51	0	48	0	0
T52	0	28	0	0
T53	0	28	0	0
T54	1982	0	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2046	2046	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T11	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2046	2046	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T11	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718629658	716965008	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	588	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
524	1	1
551	1	1
552	1	1
553	1	1
554	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
562	1	1
569	1	1
586	1	1
587	1	1
588	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	90	84.91
Logical	106	90	84.91
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T18,T21
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T6,T8
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T21

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T6,T8
1	0	1	Covered	T4,T18,T21
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T21

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T75
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T18,T21

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T6,T7,T59

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T5

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T16

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T35,T57
1	0	Covered	T2,T3,T11

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       524
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15
1	0	Covered	T14,T15

 LINE       551
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T21
1	0	Covered	T5,T29,T55

 LINE       552
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T21
1	0	Covered	T5,T29,T55

 LINE       553
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T29,T55

 LINE       554
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T29,T55

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T2,T3,T16
StCtrlProg	339	Covered	T2,T3,T5
StCtrlRead	337	Covered	T2,T3,T4
StDisable	335	Covered	T1,T5,T11
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T2,T3,T16
StCtrlProg->StIdle	359	Covered	T2,T3,T5
StCtrlRead->StIdle	349	Covered	T2,T3,T4
StIdle->StCtrl	341	Covered	T2,T3,T16
StIdle->StCtrlProg	339	Covered	T2,T3,T5
StIdle->StCtrlRead	337	Covered	T2,T3,T4
StIdle->StDisable	335	Covered	T1,T5,T11

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	554	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T29,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T29,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T6,T7,T59
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T13
0	0	0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T13
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T5,T11
StIdle	0	1	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T5
StIdle	0	0	0	1	-	-	-	Covered	T2,T3,T16
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T2,T3,T4
StCtrlRead	-	-	-	-	0	-	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T5
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T5
StCtrl	-	-	-	-	-	-	1	Covered	T2,T3,T16
StCtrl	-	-	-	-	-	-	0	Covered	T2,T3,T16
StDisable	-	-	-	-	-	-	-	Covered	T1,T5,T11
default	-	-	-	-	-	-	-	Covered	T14,T15,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	359497816	1271241	0	0
CtrlPrio_A	359497816	1271235	0	0
HostTransIdleChk_A	359497816	22200367	0	0
NoRemainder_A	1023	1023	0	0
OneHotReqs_A	359497816	358665491	0	0
Pow2Multiple_A	1023	1023	0	0
RdTxnCheck_A	359314829	358482504	0	0
u_state_regs_A	359497816	358665491	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	1271241	0	0
T6	120539	42539	0	0
T7	435006	8305	0	0
T8	563474	0	0	0
T28	4060	0	0	0
T35	178944	0	0	0
T36	0	26780	0	0
T37	0	5184	0	0
T38	0	41818	0	0
T43	6197	0	0	0
T44	190840	0	0	0
T53	1753	0	0	0
T59	316628	8059	0	0
T60	0	359	0	0
T61	0	3069	0	0
T93	1797	0	0	0
T172	0	1585	0	0
T177	0	670	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	1271235	0	0
T6	120539	42539	0	0
T7	435006	8305	0	0
T8	563474	0	0	0
T28	4060	0	0	0
T35	178944	0	0	0
T36	0	26780	0	0
T37	0	5184	0	0
T38	0	41818	0	0
T43	6197	0	0	0
T44	190840	0	0	0
T53	1753	0	0	0
T59	316628	8059	0	0
T60	0	359	0	0
T61	0	3069	0	0
T93	1797	0	0	0
T172	0	1585	0	0
T177	0	670	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	22200367	0	0
T4	2130	4	0	0
T5	1482	0	0	0
T6	0	446301	0	0
T7	0	90348	0	0
T11	989	0	0	0
T16	548658	0	0	0
T17	1249	0	0	0
T18	73334	28814	0	0
T19	3743	0	0	0
T21	9820	41	0	0
T29	3189	28	0	0
T50	0	12	0	0
T51	0	20	0	0
T52	0	12	0	0
T53	0	12	0	0
T54	991	0	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359314829	358482504	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	588	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
524	1	1
551	1	1
552	1	1
553	1	1
554	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
562	1	1
569	1	1
586	1	1
587	1	1
588	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	100	94.34
Logical	106	100	94.34
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T155,T230,T211

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T155,T230,T211

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T18,T21
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T18,T21

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T6,T7
1	0	1	Covered	T4,T18,T21
1	1	0	Covered	T45,T46,T47
1	1	1	Covered	T4,T18,T21

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T4,T18,T21

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T21

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T6,T7

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T11
1	1	Covered	T2,T3,T4

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T46,T47
1	0	Covered	T20,T231

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T231

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T47

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T35,T57
1	0	Covered	T2,T3,T11

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T155

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T21
1	0	Covered	T155
1	1	Covered	T155

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T21

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T21
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T155

 LINE       524
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15
1	0	Covered	T14,T15

 LINE       551
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T29,T55

 LINE       552
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T29,T55

 LINE       553
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T29,T55

 LINE       554
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T29,T55

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T2,T3,T11
StCtrlProg	339	Covered	T2,T3,T4
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T5,T11,T27
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T2,T3,T11
StCtrlProg->StIdle	359	Covered	T2,T3,T4
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T2,T3,T11
StIdle->StCtrlProg	339	Covered	T2,T3,T4
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T5,T11,T27

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	554	2	2	100.00
TERNARY	431	2	2	100.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T29,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T29,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T155
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T18,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T155,T230,T211
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T155,T12,T13
0	0	0	Covered	T4,T18,T21

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T5,T11
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	-	Covered	T2,T3,T11
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T4
StCtrl	-	-	-	-	-	-	1	Covered	T2,T3,T11
StCtrl	-	-	-	-	-	-	0	Covered	T2,T3,T11
StDisable	-	-	-	-	-	-	-	Covered	T5,T11,T27
default	-	-	-	-	-	-	-	Covered	T14,T15,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	359497816	1461986	0	0
CtrlPrio_A	359497816	1461986	0	0
HostTransIdleChk_A	359497816	22225145	0	0
NoRemainder_A	1023	1023	0	0
OneHotReqs_A	359497816	358665491	0	0
Pow2Multiple_A	1023	1023	0	0
RdTxnCheck_A	359314829	358482504	0	0
u_state_regs_A	359497816	358665491	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	1461986	0	0
T6	0	33887	0	0
T7	0	13338	0	0
T18	73334	6300	0	0
T19	3743	0	0	0
T21	9820	0	0	0
T27	3671	0	0	0
T29	3189	0	0	0
T30	1860	0	0	0
T36	0	62315	0	0
T38	0	44187	0	0
T42	11343	0	0	0
T50	2278	0	0	0
T54	991	0	0	0
T55	192206	0	0	0
T59	0	8804	0	0
T60	0	1771	0	0
T61	0	2900	0	0
T172	0	626	0	0
T177	0	1550	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	1461986	0	0
T6	0	33887	0	0
T7	0	13338	0	0
T18	73334	6300	0	0
T19	3743	0	0	0
T21	9820	0	0	0
T27	3671	0	0	0
T29	3189	0	0	0
T30	1860	0	0	0
T36	0	62315	0	0
T38	0	44187	0	0
T42	11343	0	0	0
T50	2278	0	0	0
T54	991	0	0	0
T55	192206	0	0	0
T59	0	8804	0	0
T60	0	1771	0	0
T61	0	2900	0	0
T172	0	626	0	0
T177	0	1550	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	22225145	0	0
T4	2130	24	0	0
T5	1482	0	0	0
T6	0	393516	0	0
T11	989	0	0	0
T16	548658	0	0	0
T17	1249	0	0	0
T18	73334	28253	0	0
T19	3743	0	0	0
T21	9820	25	0	0
T29	3189	8	0	0
T30	0	16	0	0
T50	0	12	0	0
T51	0	28	0	0
T52	0	16	0	0
T53	0	16	0	0
T54	991	0	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359314829	358482504	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0