Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.54	100.00	90.15			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.32	100.00	89.28			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.48	100.00	89.93			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.32	100.00	89.28			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.09	97.64	92.50	100.00		98.73	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.87	100.00	94.34		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	93.90	100.00	79.49	100.00		90.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.48	100.00	89.93			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.13	97.64	92.74	100.00		98.73	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	93.90	100.00	79.49	100.00		90.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	457	412	90.15
Logical	457	412	90.15
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
141-792	90.09
796	100.00

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T29,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T59,T94
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	718995632	1557468	0	0
ExclusiveOps_A	718995632	717330982	0	0
ExclusiveProgHazard_A	718995632	717330982	0	0
ExclusiveState_A	718995632	717330982	0	0
ForwardCheck_A	718995632	4396173	0	0
IdleCheck_A	718995632	102087202	0	0
MaxBufs_A	2046	2046	0	0
OneHotAlloc_A	718995632	717330982	0	0
OneHotMatch_A	718995632	717330982	0	0
OneHotRspMatch_A	718995632	717330982	0	0
OneHotUpdate_A	718995632	717330982	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	1557468	0	0
T2	518160	447	0	0
T3	129432	0	0	0
T4	4260	26	0	0
T5	2964	0	0	0
T11	1978	0	0	0
T16	1097316	2636	0	0
T17	2498	0	0	0
T18	146668	2785	0	0
T19	7486	0	0	0
T21	19640	126	0	0
T29	0	29	0	0
T30	0	19	0	0
T42	0	136	0	0
T50	0	37	0	0
T51	0	14	0	0
T52	0	5	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	4396173	0	0
T2	518160	513	0	0
T3	129432	42	0	0
T4	4260	0	0	0
T5	2964	0	0	0
T6	0	30271	0	0
T11	1978	0	0	0
T16	1097316	2658	0	0
T17	2498	0	0	0
T18	146668	0	0	0
T19	7486	0	0	0
T21	19640	54	0	0
T29	0	2	0	0
T35	0	2895	0	0
T42	0	168	0	0
T43	0	54	0	0
T44	0	1206	0	0
T52	0	4	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	102087202	0	0
T1	1078	268	0	0
T2	518160	1601	0	0
T3	129432	212	0	0
T4	4260	414	0	0
T5	2964	128	0	0
T11	1978	128	0	0
T16	1097316	8080	0	0
T17	2498	260	0	0
T18	146668	75988	0	0
T19	7486	128	0	0
T21	9820	132	0	0
T29	0	42	0	0
T30	0	10	0	0
T42	0	270	0	0
T50	0	27	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2046	2046	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T11	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718995632	717330982	0	0
T1	2156	1764	0	0
T2	518160	518042	0	0
T3	129432	129110	0	0
T4	4260	3992	0	0
T5	2964	2764	0	0
T11	1978	1828	0	0
T16	1097316	1097176	0	0
T17	2498	2100	0	0
T18	146668	146432	0	0
T19	7486	7360	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	457	408	89.28
Logical	457	408	89.28
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T7,T40,T165
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T7,T40,T165

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T7,T166,T167
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T7,T166,T167

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T7,T40,T169
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T7,T40,T169

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T7,T40,T166
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T7,T40,T166

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T3,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T21,T30,T50
1	1	1	0	1	1	1	Covered	T2,T3,T4
1	1	1	1	0	1	1	Covered	T7,T171,T181
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T172,T173,T174
1	1	1	1	1	1	1	Covered	T2,T4,T16

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T3,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T21,T80,T44
1	1	1	0	1	1	1	Covered	T2,T3,T4
1	1	1	1	0	1	1	Covered	T7,T166,T175
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T59,T172,T76
1	1	1	1	1	1	1	Covered	T2,T4,T16

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T3,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T80,T44,T102
1	1	1	0	1	1	1	Covered	T2,T3,T4
1	1	1	1	0	1	1	Covered	T7,T175,T181
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T59,T60,T176
1	1	1	1	1	1	1	Covered	T2,T4,T16

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T3,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T21,T80,T44
1	1	1	0	1	1	1	Covered	T2,T3,T4
1	1	1	1	0	1	1	Covered	T7,T170,T175
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T59,T177,T180
1	1	1	1	1	1	1	Covered	T2,T4,T16

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T172,T178,T173
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T59,T172,T76
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T59,T60,T176
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T59,T177,T182
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T7,T172
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T7,T59
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T7,T59
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T7,T59
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T30,T50
1	0	Covered	T2,T3,T4
1	1	Covered	T21,T30,T50

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T21,T24,T80
0	1	0	Covered	T30,T50,T24
1	0	0	Covered	T35,T57,T71

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T30,T50,T24

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T21,T24,T80

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T80
1	0	Covered	T2,T3,T4
1	1	Covered	T21,T80,T44

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T21,T24,T80
0	1	0	Covered	T24,T80,T35
1	0	0	Covered	T35,T57,T71

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T24,T80,T35

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T21,T24,T80

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T80
1	0	Covered	T2,T3,T4
1	1	Covered	T21,T80,T44

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T21,T24,T80
0	1	0	Covered	T24,T80,T35
1	0	0	Covered	T35,T57,T71

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T24,T80,T35

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T21,T24,T80

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T80
1	0	Covered	T2,T3,T4
1	1	Covered	T21,T80,T44

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T21,T24,T80
0	1	0	Covered	T24,T80,T35
1	0	0	Covered	T35,T57,T71

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T24,T80,T35

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T11
1	1	Covered	T21,T24,T80

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T59,T71
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T59,T71
1	1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T21
1	1	Covered	T1,T2,T3

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T4,T18,T21
1	1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T18,T7,T61
1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T6,T7,T8
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T2,T4,T16
1	1	1	1	1	0	Covered	T7,T177,T60
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T21,T44

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T40,T114

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T30,T50

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T30,T50
1	0	Covered	T7,T40,T114

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T30,T50

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T18,T7,T61
1	1	1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T16
1	1	0	Covered	T21,T59,T94
1	1	1	Covered	T1,T2,T3

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T44,T35
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T21,T59,T94

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T76,T180,T174
1	1	1	Covered	T2,T3,T16

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T59,T94

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T59,T94

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T60,T155
1	1	Covered	T2,T3,T16

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T59,T94

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T76,T180
1	1	0	Covered	T2,T3,T16
1	1	1	Covered	T1,T2,T3

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T18,T7,T60
1	1	0	Covered	T21,T59,T94
1	1	1	Covered	T1,T2,T3

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T16

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T3,T4
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T2,T4,T16

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T3,T4
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T2,T4,T16

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T3,T4
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T2,T4,T16

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T3,T4
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T2,T4,T16

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T16
0	1	Not Covered
1	0	Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T16

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T30

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T16

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T16
1	0	Covered	T1,T2,T3

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T155
1	0	Covered	T1,T4,T30

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T30

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T7,T114,T169

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T16
1	1	Not Covered

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T30

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T30,T50
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T59,T94
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	359497816	948980	0	0
ExclusiveOps_A	359497816	358665491	0	0
ExclusiveProgHazard_A	359497816	358665491	0	0
ExclusiveState_A	359497816	358665491	0	0
ForwardCheck_A	359497816	2556110	0	0
IdleCheck_A	359497816	53172563	0	0
MaxBufs_A	1023	1023	0	0
OneHotAlloc_A	359497816	358665491	0	0
OneHotMatch_A	359497816	358665491	0	0
OneHotRspMatch_A	359497816	358665491	0	0
OneHotUpdate_A	359497816	358665491	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	948980	0	0
T2	259080	193	0	0
T3	64716	0	0	0
T4	2130	20	0	0
T5	1482	0	0	0
T11	989	0	0	0
T16	548658	1321	0	0
T17	1249	0	0	0
T18	73334	2785	0	0
T19	3743	0	0	0
T21	9820	98	0	0
T29	0	27	0	0
T30	0	17	0	0
T42	0	60	0	0
T50	0	34	0	0
T51	0	11	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	2556110	0	0
T2	259080	223	0	0
T3	64716	19	0	0
T4	2130	0	0	0
T5	1482	0	0	0
T6	0	14789	0	0
T11	989	0	0	0
T16	548658	1334	0	0
T17	1249	0	0	0
T18	73334	0	0	0
T19	3743	0	0	0
T21	9820	40	0	0
T29	0	2	0	0
T35	0	1319	0	0
T42	0	71	0	0
T43	0	30	0	0
T44	0	562	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	53172563	0	0
T1	1078	268	0	0
T2	259080	767	0	0
T3	64716	166	0	0
T4	2130	380	0	0
T5	1482	128	0	0
T11	989	128	0	0
T16	548658	4117	0	0
T17	1249	260	0	0
T18	73334	47174	0	0
T19	3743	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	457	411	89.93
Logical	457	411	89.93
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
141-792	89.87
796	100.00

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T52,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T18,T21
0	1	Covered	T177,T60,T123
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T4,T18,T21
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T16
0	1	Covered	T4,T18,T21
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T52,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T18,T21
0	0	1	Covered	T4,T18,T21
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	359497816	608488	0	0
ExclusiveOps_A	359497816	358665491	0	0
ExclusiveProgHazard_A	359497816	358665491	0	0
ExclusiveState_A	359497816	358665491	0	0
ForwardCheck_A	359497816	1840063	0	0
IdleCheck_A	359497816	48914639	0	0
MaxBufs_A	1023	1023	0	0
OneHotAlloc_A	359497816	358665491	0	0
OneHotMatch_A	359497816	358665491	0	0
OneHotRspMatch_A	359497816	358665491	0	0
OneHotUpdate_A	359497816	358665491	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	608488	0	0
T2	259080	254	0	0
T3	64716	0	0	0
T4	2130	6	0	0
T5	1482	0	0	0
T11	989	0	0	0
T16	548658	1315	0	0
T17	1249	0	0	0
T18	73334	0	0	0
T19	3743	0	0	0
T21	9820	28	0	0
T29	0	2	0	0
T30	0	2	0	0
T42	0	76	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	5	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	1840063	0	0
T2	259080	290	0	0
T3	64716	23	0	0
T4	2130	0	0	0
T5	1482	0	0	0
T6	0	15482	0	0
T11	989	0	0	0
T16	548658	1324	0	0
T17	1249	0	0	0
T18	73334	0	0	0
T19	3743	0	0	0
T21	9820	14	0	0
T35	0	1576	0	0
T42	0	97	0	0
T43	0	24	0	0
T44	0	644	0	0
T52	0	4	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	48914639	0	0
T2	259080	834	0	0
T3	64716	46	0	0
T4	2130	34	0	0
T5	1482	0	0	0
T11	989	0	0	0
T16	548658	3963	0	0
T17	1249	0	0	0
T18	73334	28814	0	0
T19	3743	0	0	0
T21	9820	132	0	0
T29	0	42	0	0
T30	0	10	0	0
T42	0	270	0	0
T50	0	27	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	359497816	358665491	0	0
T1	1078	882	0	0
T2	259080	259021	0	0
T3	64716	64555	0	0
T4	2130	1996	0	0
T5	1482	1382	0	0
T11	989	914	0	0
T16	548658	548588	0	0
T17	1249	1050	0	0
T18	73334	73216	0	0
T19	3743	3680	0	0