Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	415198468	3915	0	0
addr_rd_A	415198468	1045	0	0
bank0_info0_page_cfg_0_rd_A	415198468	1810	0	0
bank0_info0_page_cfg_1_rd_A	415198468	1656	0	0
bank0_info0_page_cfg_2_rd_A	415198468	1526	0	0
bank0_info0_page_cfg_3_rd_A	415198468	1523	0	0
bank0_info0_page_cfg_4_rd_A	415198468	1679	0	0
bank0_info0_page_cfg_5_rd_A	415198468	1637	0	0
bank0_info0_page_cfg_6_rd_A	415198468	1500	0	0
bank0_info0_page_cfg_7_rd_A	415198468	1573	0	0
bank0_info0_page_cfg_8_rd_A	415198468	1470	0	0
bank0_info0_page_cfg_9_rd_A	415198468	1871	0	0
bank0_info0_regwen_0_rd_A	415198468	934	0	0
bank0_info0_regwen_1_rd_A	415198468	913	0	0
bank0_info0_regwen_2_rd_A	415198468	955	0	0
bank0_info0_regwen_3_rd_A	415198468	865	0	0
bank0_info0_regwen_4_rd_A	415198468	917	0	0
bank0_info0_regwen_5_rd_A	415198468	1060	0	0
bank0_info0_regwen_6_rd_A	415198468	861	0	0
bank0_info0_regwen_7_rd_A	415198468	926	0	0
bank0_info0_regwen_8_rd_A	415198468	919	0	0
bank0_info0_regwen_9_rd_A	415198468	971	0	0
bank0_info1_page_cfg_rd_A	415198468	1523	0	0
bank0_info1_regwen_rd_A	415198468	969	0	0
bank0_info2_page_cfg_0_rd_A	415198468	1723	0	0
bank0_info2_page_cfg_1_rd_A	415198468	1751	0	0
bank0_info2_regwen_0_rd_A	415198468	890	0	0
bank0_info2_regwen_1_rd_A	415198468	946	0	0
bank1_info0_page_cfg_0_rd_A	415198468	1549	0	0
bank1_info0_page_cfg_1_rd_A	415198468	1523	0	0
bank1_info0_page_cfg_2_rd_A	415198468	1651	0	0
bank1_info0_page_cfg_3_rd_A	415198468	1706	0	0
bank1_info0_page_cfg_4_rd_A	415198468	1473	0	0
bank1_info0_page_cfg_5_rd_A	415198468	1581	0	0
bank1_info0_page_cfg_6_rd_A	415198468	1559	0	0
bank1_info0_page_cfg_7_rd_A	415198468	1648	0	0
bank1_info0_page_cfg_8_rd_A	415198468	1470	0	0
bank1_info0_page_cfg_9_rd_A	415198468	1543	0	0
bank1_info0_regwen_0_rd_A	415198468	954	0	0
bank1_info0_regwen_1_rd_A	415198468	952	0	0
bank1_info0_regwen_2_rd_A	415198468	850	0	0
bank1_info0_regwen_3_rd_A	415198468	899	0	0
bank1_info0_regwen_4_rd_A	415198468	935	0	0
bank1_info0_regwen_5_rd_A	415198468	896	0	0
bank1_info0_regwen_6_rd_A	415198468	902	0	0
bank1_info0_regwen_7_rd_A	415198468	916	0	0
bank1_info0_regwen_8_rd_A	415198468	851	0	0
bank1_info0_regwen_9_rd_A	415198468	975	0	0
bank1_info1_page_cfg_rd_A	415198468	1436	0	0
bank1_info1_regwen_rd_A	415198468	953	0	0
bank1_info2_page_cfg_0_rd_A	415198468	1664	0	0
bank1_info2_page_cfg_1_rd_A	415198468	1674	0	0
bank1_info2_regwen_0_rd_A	415198468	812	0	0
bank1_info2_regwen_1_rd_A	415198468	1054	0	0
bank_cfg_regwen_rd_A	415198468	878	0	0
default_region_rd_A	415198468	1453	0	0
exec_rd_A	415198468	885	0	0
fifo_lvl_rd_A	415198468	1000	0	0
fifo_rst_rd_A	415198468	800	0	0
hw_info_cfg_override_rd_A	415198468	1033	0	0
intr_enable_rd_A	415198468	1479	0	0
mp_region_0_rd_A	415198468	923	0	0
mp_region_1_rd_A	415198468	1137	0	0
mp_region_2_rd_A	415198468	998	0	0
mp_region_3_rd_A	415198468	954	0	0
mp_region_4_rd_A	415198468	994	0	0
mp_region_5_rd_A	415198468	968	0	0
mp_region_6_rd_A	415198468	886	0	0
mp_region_7_rd_A	415198468	1020	0	0
mp_region_cfg_0_rd_A	415198468	1647	0	0
mp_region_cfg_1_rd_A	415198468	1493	0	0
mp_region_cfg_2_rd_A	415198468	1710	0	0
mp_region_cfg_3_rd_A	415198468	1675	0	0
mp_region_cfg_4_rd_A	415198468	1391	0	0
mp_region_cfg_5_rd_A	415198468	1663	0	0
mp_region_cfg_6_rd_A	415198468	1659	0	0
mp_region_cfg_7_rd_A	415198468	1619	0	0
phy_alert_cfg_rd_A	415198468	199	0	0
region_cfg_regwen_0_rd_A	415198468	836	0	0
region_cfg_regwen_1_rd_A	415198468	884	0	0
region_cfg_regwen_2_rd_A	415198468	959	0	0
region_cfg_regwen_3_rd_A	415198468	845	0	0
region_cfg_regwen_4_rd_A	415198468	940	0	0
region_cfg_regwen_5_rd_A	415198468	924	0	0
region_cfg_regwen_6_rd_A	415198468	803	0	0
region_cfg_regwen_7_rd_A	415198468	882	0	0
scratch_rd_A	415198468	744	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	3915	0	0
T69	35610	1	0	0
T70	64704	1	0	0
T111	4702	3	0	0
T211	3322	248	0	0
T212	3063	149	0	0
T224	3265	35	0	0
T226	2574	54	0	0
T227	3404	223	0	0
T228	2875	27	0	0
T229	7632	3	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1045	0	0
T249	20831	57	0	0
T266	41516	36	0	0
T293	17892	9	0	0
T294	3867	9	0	0
T295	22040	27	0	0
T296	9624	13	0	0
T297	3793	3	0	0
T298	10238	23	0	0
T299	72006	75	0	0
T300	21092	53	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1810	0	0
T249	20831	97	0	0
T266	41516	173	0	0
T293	17892	24	0	0
T294	3867	20	0	0
T295	22040	67	0	0
T296	9624	43	0	0
T297	3793	28	0	0
T298	10238	34	0	0
T299	72006	223	0	0
T300	21092	17	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1656	0	0
T249	20831	70	0	0
T266	41516	233	0	0
T293	17892	25	0	0
T294	3867	7	0	0
T295	22040	43	0	0
T296	9624	73	0	0
T297	3793	7	0	0
T298	10238	25	0	0
T299	72006	127	0	0
T300	21092	24	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1526	0	0
T249	20831	59	0	0
T266	41516	162	0	0
T293	17892	6	0	0
T294	3867	37	0	0
T295	22040	67	0	0
T296	9624	15	0	0
T297	3793	28	0	0
T298	10238	13	0	0
T299	72006	163	0	0
T300	21092	63	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1523	0	0
T249	20831	29	0	0
T266	41516	104	0	0
T293	17892	33	0	0
T295	22040	50	0	0
T296	9624	12	0	0
T297	3793	26	0	0
T298	10238	47	0	0
T299	72006	165	0	0
T300	21092	66	0	0
T301	79108	190	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1679	0	0
T249	20831	55	0	0
T266	41516	191	0	0
T293	17892	17	0	0
T294	3867	3	0	0
T295	22040	38	0	0
T296	9624	8	0	0
T297	3793	25	0	0
T298	10238	44	0	0
T299	72006	288	0	0
T300	21092	41	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1637	0	0
T249	20831	65	0	0
T266	41516	168	0	0
T293	17892	8	0	0
T294	3867	37	0	0
T295	22040	27	0	0
T296	9624	21	0	0
T297	3793	37	0	0
T298	10238	30	0	0
T299	72006	144	0	0
T300	21092	57	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1500	0	0
T249	20831	65	0	0
T266	41516	70	0	0
T293	17892	11	0	0
T294	3867	2	0	0
T295	22040	26	0	0
T296	9624	18	0	0
T297	3793	17	0	0
T298	10238	4	0	0
T299	72006	205	0	0
T300	21092	45	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1573	0	0
T249	20831	38	0	0
T266	41516	193	0	0
T293	17892	55	0	0
T294	3867	31	0	0
T295	22040	24	0	0
T296	9624	77	0	0
T297	3793	32	0	0
T298	10238	7	0	0
T299	72006	192	0	0
T300	21092	73	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1470	0	0
T249	20831	23	0	0
T266	41516	153	0	0
T293	17892	19	0	0
T294	3867	24	0	0
T295	22040	69	0	0
T296	9624	40	0	0
T297	3793	2	0	0
T298	10238	21	0	0
T299	72006	188	0	0
T300	21092	45	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1871	0	0
T249	20831	105	0	0
T266	41516	194	0	0
T293	17892	8	0	0
T294	3867	6	0	0
T295	22040	41	0	0
T296	9624	48	0	0
T297	3793	41	0	0
T299	72006	252	0	0
T300	21092	57	0	0
T301	79108	204	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	934	0	0
T249	20831	25	0	0
T266	41516	53	0	0
T293	17892	26	0	0
T294	3867	8	0	0
T295	22040	93	0	0
T296	9624	19	0	0
T298	10238	7	0	0
T299	72006	52	0	0
T300	21092	21	0	0
T301	79108	35	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	913	0	0
T249	20831	62	0	0
T266	41516	36	0	0
T293	17892	24	0	0
T294	3867	8	0	0
T295	22040	39	0	0
T296	9624	11	0	0
T297	3793	5	0	0
T298	10238	2	0	0
T299	72006	58	0	0
T300	21092	18	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	955	0	0
T249	20831	57	0	0
T266	41516	29	0	0
T293	17892	16	0	0
T294	3867	4	0	0
T295	22040	34	0	0
T296	9624	16	0	0
T297	3793	10	0	0
T298	10238	42	0	0
T299	72006	57	0	0
T300	21092	61	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	865	0	0
T249	20831	42	0	0
T266	41516	46	0	0
T294	3867	9	0	0
T295	22040	34	0	0
T296	9624	15	0	0
T297	3793	1	0	0
T298	10238	18	0	0
T299	72006	38	0	0
T300	21092	42	0	0
T301	79108	37	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	917	0	0
T249	20831	38	0	0
T266	41516	22	0	0
T293	17892	6	0	0
T294	3867	2	0	0
T295	22040	51	0	0
T296	9624	16	0	0
T298	10238	10	0	0
T299	72006	52	0	0
T300	21092	74	0	0
T301	79108	42	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1060	0	0
T249	20831	72	0	0
T266	41516	41	0	0
T293	17892	40	0	0
T294	3867	5	0	0
T295	22040	26	0	0
T296	9624	19	0	0
T298	10238	51	0	0
T299	72006	52	0	0
T300	21092	71	0	0
T301	79108	26	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	861	0	0
T249	20831	66	0	0
T266	41516	44	0	0
T293	17892	50	0	0
T294	3867	2	0	0
T295	22040	1	0	0
T296	9624	19	0	0
T297	3793	2	0	0
T299	72006	35	0	0
T300	21092	18	0	0
T301	79108	61	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	926	0	0
T249	20831	57	0	0
T266	41516	34	0	0
T293	17892	10	0	0
T294	3867	4	0	0
T295	22040	51	0	0
T296	9624	15	0	0
T297	3793	2	0	0
T298	10238	31	0	0
T299	72006	35	0	0
T300	21092	35	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	919	0	0
T249	20831	23	0	0
T266	41516	44	0	0
T293	17892	22	0	0
T294	3867	2	0	0
T295	22040	75	0	0
T296	9624	11	0	0
T297	3793	3	0	0
T298	10238	33	0	0
T299	72006	47	0	0
T300	21092	62	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	971	0	0
T249	20831	47	0	0
T266	41516	43	0	0
T293	17892	35	0	0
T294	3867	4	0	0
T295	22040	65	0	0
T296	9624	18	0	0
T297	3793	3	0	0
T298	10238	36	0	0
T299	72006	55	0	0
T300	21092	72	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1523	0	0
T249	20831	53	0	0
T266	41516	124	0	0
T293	17892	21	0	0
T294	3867	31	0	0
T295	22040	21	0	0
T296	9624	31	0	0
T298	10238	30	0	0
T299	72006	173	0	0
T300	21092	38	0	0
T301	79108	138	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	969	0	0
T249	20831	56	0	0
T266	41516	36	0	0
T293	17892	39	0	0
T294	3867	3	0	0
T295	22040	60	0	0
T296	9624	8	0	0
T297	3793	1	0	0
T298	10238	12	0	0
T299	72006	47	0	0
T300	21092	67	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1723	0	0
T249	20831	47	0	0
T266	41516	147	0	0
T293	17892	50	0	0
T294	3867	8	0	0
T295	22040	84	0	0
T296	9624	33	0	0
T297	3793	1	0	0
T298	10238	1	0	0
T299	72006	186	0	0
T300	21092	31	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1751	0	0
T249	20831	45	0	0
T266	41516	239	0	0
T293	17892	23	0	0
T294	3867	32	0	0
T295	22040	68	0	0
T296	9624	36	0	0
T297	3793	13	0	0
T299	72006	233	0	0
T300	21092	44	0	0
T301	79108	136	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	890	0	0
T249	20831	95	0	0
T266	41516	63	0	0
T293	17892	8	0	0
T294	3867	2	0	0
T295	22040	13	0	0
T296	9624	23	0	0
T297	3793	1	0	0
T298	10238	47	0	0
T299	72006	28	0	0
T300	21092	23	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	946	0	0
T249	20831	32	0	0
T266	41516	51	0	0
T293	17892	40	0	0
T294	3867	3	0	0
T295	22040	20	0	0
T296	9624	10	0	0
T297	3793	6	0	0
T298	10238	6	0	0
T299	72006	37	0	0
T300	21092	8	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1549	0	0
T249	20831	43	0	0
T266	41516	116	0	0
T293	17892	33	0	0
T294	3867	8	0	0
T295	22040	30	0	0
T296	9624	74	0	0
T297	3793	25	0	0
T298	10238	75	0	0
T299	72006	137	0	0
T300	21092	92	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1523	0	0
T249	20831	54	0	0
T266	41516	134	0	0
T293	17892	20	0	0
T294	3867	10	0	0
T295	22040	23	0	0
T296	9624	61	0	0
T297	3793	3	0	0
T298	10238	17	0	0
T299	72006	221	0	0
T300	21092	35	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1651	0	0
T249	20831	52	0	0
T266	41516	213	0	0
T293	17892	11	0	0
T294	3867	31	0	0
T295	22040	38	0	0
T296	9624	35	0	0
T297	3793	15	0	0
T298	10238	44	0	0
T299	72006	137	0	0
T300	21092	57	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1706	0	0
T249	20831	45	0	0
T266	41516	148	0	0
T293	17892	29	0	0
T294	3867	2	0	0
T295	22040	73	0	0
T296	9624	36	0	0
T297	3793	44	0	0
T298	10238	29	0	0
T299	72006	217	0	0
T300	21092	46	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1473	0	0
T249	20831	45	0	0
T266	41516	152	0	0
T293	17892	29	0	0
T294	3867	32	0	0
T295	22040	44	0	0
T296	9624	35	0	0
T297	3793	5	0	0
T298	10238	48	0	0
T299	72006	122	0	0
T300	21092	9	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1581	0	0
T249	20831	50	0	0
T266	41516	170	0	0
T293	17892	43	0	0
T294	3867	9	0	0
T295	22040	54	0	0
T296	9624	64	0	0
T297	3793	22	0	0
T298	10238	39	0	0
T299	72006	209	0	0
T300	21092	43	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1559	0	0
T249	20831	54	0	0
T266	41516	193	0	0
T293	17892	17	0	0
T294	3867	27	0	0
T295	22040	50	0	0
T296	9624	78	0	0
T297	3793	6	0	0
T298	10238	11	0	0
T299	72006	147	0	0
T300	21092	26	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1648	0	0
T249	20831	21	0	0
T266	41516	193	0	0
T293	17892	23	0	0
T294	3867	3	0	0
T295	22040	34	0	0
T296	9624	43	0	0
T297	3793	1	0	0
T298	10238	11	0	0
T299	72006	212	0	0
T300	21092	18	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1470	0	0
T249	20831	38	0	0
T266	41516	88	0	0
T293	17892	35	0	0
T294	3867	38	0	0
T295	22040	22	0	0
T296	9624	44	0	0
T297	3793	26	0	0
T298	10238	22	0	0
T299	72006	211	0	0
T300	21092	55	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1543	0	0
T249	20831	51	0	0
T266	41516	158	0	0
T293	17892	35	0	0
T294	3867	28	0	0
T295	22040	41	0	0
T296	9624	14	0	0
T298	10238	7	0	0
T299	72006	183	0	0
T300	21092	35	0	0
T301	79108	224	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	954	0	0
T249	20831	54	0	0
T266	41516	50	0	0
T293	17892	21	0	0
T294	3867	2	0	0
T295	22040	76	0	0
T296	9624	24	0	0
T297	3793	5	0	0
T298	10238	26	0	0
T299	72006	49	0	0
T300	21092	81	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	952	0	0
T249	20831	97	0	0
T266	41516	36	0	0
T293	17892	13	0	0
T294	3867	8	0	0
T295	22040	24	0	0
T296	9624	27	0	0
T297	3793	8	0	0
T298	10238	26	0	0
T299	72006	50	0	0
T300	21092	29	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	850	0	0
T249	20831	36	0	0
T266	41516	39	0	0
T293	17892	15	0	0
T294	3867	5	0	0
T295	22040	33	0	0
T296	9624	19	0	0
T297	3793	4	0	0
T298	10238	1	0	0
T299	72006	28	0	0
T300	21092	25	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	899	0	0
T249	20831	19	0	0
T266	41516	35	0	0
T293	17892	4	0	0
T295	22040	64	0	0
T296	9624	9	0	0
T297	3793	3	0	0
T298	10238	33	0	0
T299	72006	48	0	0
T300	21092	35	0	0
T301	79108	52	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	935	0	0
T249	20831	55	0	0
T266	41516	32	0	0
T293	17892	49	0	0
T294	3867	5	0	0
T295	22040	24	0	0
T296	9624	21	0	0
T297	3793	8	0	0
T298	10238	11	0	0
T299	72006	44	0	0
T300	21092	14	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	896	0	0
T249	20831	69	0	0
T266	41516	36	0	0
T293	17892	22	0	0
T294	3867	1	0	0
T295	22040	47	0	0
T296	9624	14	0	0
T297	3793	3	0	0
T298	10238	31	0	0
T299	72006	54	0	0
T300	21092	58	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	902	0	0
T249	20831	72	0	0
T266	41516	32	0	0
T293	17892	27	0	0
T294	3867	2	0	0
T295	22040	62	0	0
T296	9624	21	0	0
T297	3793	3	0	0
T298	10238	43	0	0
T299	72006	34	0	0
T300	21092	19	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	916	0	0
T249	20831	70	0	0
T266	41516	31	0	0
T293	17892	23	0	0
T294	3867	3	0	0
T295	22040	24	0	0
T296	9624	16	0	0
T297	3793	4	0	0
T298	10238	29	0	0
T299	72006	36	0	0
T300	21092	64	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	851	0	0
T249	20831	47	0	0
T266	41516	31	0	0
T294	3867	1	0	0
T295	22040	51	0	0
T296	9624	23	0	0
T297	3793	3	0	0
T299	72006	42	0	0
T300	21092	35	0	0
T301	79108	43	0	0
T302	2596	1	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	975	0	0
T249	20831	66	0	0
T266	41516	53	0	0
T293	17892	26	0	0
T294	3867	2	0	0
T295	22040	40	0	0
T296	9624	24	0	0
T297	3793	7	0	0
T298	10238	20	0	0
T299	72006	41	0	0
T300	21092	49	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1436	0	0
T249	20831	20	0	0
T266	41516	124	0	0
T293	17892	20	0	0
T294	3867	35	0	0
T295	22040	24	0	0
T296	9624	36	0	0
T297	3793	27	0	0
T298	10238	37	0	0
T299	72006	142	0	0
T300	21092	78	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	953	0	0
T249	20831	44	0	0
T266	41516	47	0	0
T293	17892	31	0	0
T294	3867	1	0	0
T295	22040	33	0	0
T296	9624	20	0	0
T298	10238	25	0	0
T299	72006	45	0	0
T300	21092	33	0	0
T301	79108	44	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1664	0	0
T249	20831	50	0	0
T266	41516	212	0	0
T293	17892	31	0	0
T294	3867	37	0	0
T295	22040	22	0	0
T296	9624	44	0	0
T297	3793	30	0	0
T298	10238	22	0	0
T299	72006	194	0	0
T300	21092	32	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1674	0	0
T249	20831	39	0	0
T266	41516	138	0	0
T293	17892	11	0	0
T294	3867	3	0	0
T295	22040	60	0	0
T296	9624	62	0	0
T297	3793	24	0	0
T298	10238	40	0	0
T299	72006	207	0	0
T300	21092	25	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	812	0	0
T249	20831	1	0	0
T266	41516	42	0	0
T293	17892	9	0	0
T294	3867	1	0	0
T295	22040	39	0	0
T296	9624	3	0	0
T297	3793	1	0	0
T298	10238	20	0	0
T299	72006	24	0	0
T300	21092	55	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1054	0	0
T249	20831	20	0	0
T266	41516	47	0	0
T293	17892	39	0	0
T294	3867	2	0	0
T295	22040	66	0	0
T296	9624	10	0	0
T297	3793	6	0	0
T298	10238	23	0	0
T299	72006	44	0	0
T300	21092	83	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	878	0	0
T249	20831	64	0	0
T266	41516	50	0	0
T293	17892	8	0	0
T295	22040	59	0	0
T296	9624	20	0	0
T297	3793	3	0	0
T298	10238	16	0	0
T299	72006	38	0	0
T300	21092	52	0	0
T301	79108	37	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1453	0	0
T249	20831	50	0	0
T266	41516	68	0	0
T293	17892	19	0	0
T294	3867	4	0	0
T295	22040	53	0	0
T296	9624	64	0	0
T297	3793	10	0	0
T298	10238	10	0	0
T299	72006	193	0	0
T300	21092	18	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	885	0	0
T249	20831	28	0	0
T266	41516	38	0	0
T293	17892	37	0	0
T294	3867	8	0	0
T295	22040	20	0	0
T296	9624	16	0	0
T297	3793	6	0	0
T298	10238	24	0	0
T299	72006	18	0	0
T300	21092	53	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1000	0	0
T249	20831	66	0	0
T266	41516	58	0	0
T293	17892	13	0	0
T294	3867	9	0	0
T295	22040	11	0	0
T296	9624	19	0	0
T297	3793	11	0	0
T298	10238	8	0	0
T299	72006	71	0	0
T300	21092	65	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	800	0	0
T249	20831	11	0	0
T266	41516	51	0	0
T293	17892	6	0	0
T294	3867	4	0	0
T295	22040	15	0	0
T296	9624	12	0	0
T297	3793	3	0	0
T298	10238	16	0	0
T299	72006	45	0	0
T300	21092	37	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1033	0	0
T249	20831	26	0	0
T266	41516	55	0	0
T293	17892	5	0	0
T294	3867	6	0	0
T295	22040	20	0	0
T296	9624	34	0	0
T297	3793	7	0	0
T298	10238	14	0	0
T299	72006	67	0	0
T300	21092	61	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1479	0	0
T249	20831	19	0	0
T266	41516	145	0	0
T293	17892	22	0	0
T294	3867	33	0	0
T295	22040	30	0	0
T296	9624	27	0	0
T297	3793	30	0	0
T298	10238	51	0	0
T299	72006	153	0	0
T300	21092	47	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	923	0	0
T249	20831	26	0	0
T266	41516	63	0	0
T293	17892	5	0	0
T294	3867	4	0	0
T295	22040	7	0	0
T296	9624	16	0	0
T297	3793	9	0	0
T298	10238	34	0	0
T299	72006	42	0	0
T300	21092	70	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1137	0	0
T249	20831	71	0	0
T266	41516	77	0	0
T293	17892	28	0	0
T294	3867	4	0	0
T295	22040	55	0	0
T296	9624	22	0	0
T297	3793	7	0	0
T298	10238	20	0	0
T299	72006	83	0	0
T300	21092	38	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	998	0	0
T249	20831	22	0	0
T266	41516	68	0	0
T293	17892	50	0	0
T294	3867	7	0	0
T295	22040	21	0	0
T296	9624	17	0	0
T297	3793	9	0	0
T298	10238	11	0	0
T299	72006	37	0	0
T300	21092	37	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	954	0	0
T249	20831	44	0	0
T266	41516	51	0	0
T293	17892	9	0	0
T294	3867	2	0	0
T295	22040	35	0	0
T296	9624	31	0	0
T297	3793	9	0	0
T298	10238	26	0	0
T299	72006	57	0	0
T300	21092	49	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	994	0	0
T249	20831	39	0	0
T266	41516	63	0	0
T293	17892	14	0	0
T295	22040	47	0	0
T296	9624	12	0	0
T297	3793	12	0	0
T298	10238	21	0	0
T299	72006	57	0	0
T300	21092	37	0	0
T301	79108	91	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	968	0	0
T249	20831	51	0	0
T266	41516	70	0	0
T293	17892	32	0	0
T294	3867	9	0	0
T295	22040	35	0	0
T296	9624	20	0	0
T297	3793	7	0	0
T298	10238	19	0	0
T299	72006	35	0	0
T300	21092	62	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	886	0	0
T249	20831	63	0	0
T266	41516	58	0	0
T293	17892	16	0	0
T294	3867	7	0	0
T295	22040	21	0	0
T296	9624	16	0	0
T297	3793	2	0	0
T299	72006	100	0	0
T300	21092	19	0	0
T301	79108	61	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1020	0	0
T249	20831	58	0	0
T266	41516	54	0	0
T293	17892	11	0	0
T294	3867	8	0	0
T295	22040	60	0	0
T296	9624	13	0	0
T297	3793	15	0	0
T298	10238	21	0	0
T299	72006	61	0	0
T300	21092	61	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1647	0	0
T249	20831	38	0	0
T266	41516	195	0	0
T293	17892	21	0	0
T294	3867	5	0	0
T295	22040	68	0	0
T296	9624	52	0	0
T297	3793	4	0	0
T298	10238	19	0	0
T299	72006	223	0	0
T300	21092	53	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1493	0	0
T249	20831	77	0	0
T266	41516	132	0	0
T293	17892	7	0	0
T294	3867	23	0	0
T295	22040	18	0	0
T296	9624	13	0	0
T297	3793	3	0	0
T298	10238	31	0	0
T299	72006	106	0	0
T300	21092	14	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1710	0	0
T249	20831	24	0	0
T266	41516	203	0	0
T293	17892	21	0	0
T294	3867	40	0	0
T295	22040	58	0	0
T296	9624	26	0	0
T297	3793	35	0	0
T298	10238	49	0	0
T299	72006	191	0	0
T300	21092	43	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1675	0	0
T249	20831	20	0	0
T266	41516	216	0	0
T293	17892	24	0	0
T294	3867	2	0	0
T295	22040	37	0	0
T296	9624	9	0	0
T297	3793	3	0	0
T298	10238	27	0	0
T299	72006	194	0	0
T300	21092	55	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1391	0	0
T249	20831	8	0	0
T266	41516	126	0	0
T293	17892	16	0	0
T294	3867	5	0	0
T295	22040	38	0	0
T296	9624	34	0	0
T297	3793	2	0	0
T298	10238	47	0	0
T299	72006	167	0	0
T300	21092	11	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1663	0	0
T249	20831	30	0	0
T266	41516	234	0	0
T293	17892	26	0	0
T294	3867	18	0	0
T295	22040	70	0	0
T296	9624	64	0	0
T297	3793	9	0	0
T298	10238	32	0	0
T299	72006	163	0	0
T300	21092	20	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1659	0	0
T249	20831	41	0	0
T266	41516	116	0	0
T293	17892	25	0	0
T294	3867	29	0	0
T295	22040	37	0	0
T296	9624	55	0	0
T297	3793	2	0	0
T298	10238	25	0	0
T299	72006	196	0	0
T300	21092	68	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	1619	0	0
T249	20831	60	0	0
T266	41516	195	0	0
T293	17892	14	0	0
T294	3867	37	0	0
T295	22040	1	0	0
T296	9624	62	0	0
T297	3793	1	0	0
T298	10238	26	0	0
T299	72006	111	0	0
T300	21092	54	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	199	0	0
T249	20831	40	0	0
T293	17892	25	0	0
T295	22040	56	0	0
T296	9624	4	0	0
T298	10238	15	0	0
T300	21092	17	0	0
T303	5429	5	0	0
T304	10330	4	0	0
T305	4574	1	0	0
T306	22719	15	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	836	0	0
T249	20831	48	0	0
T266	41516	55	0	0
T293	17892	2	0	0
T295	22040	37	0	0
T296	9624	18	0	0
T297	3793	9	0	0
T298	10238	22	0	0
T299	72006	30	0	0
T300	21092	37	0	0
T301	79108	43	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	884	0	0
T249	20831	46	0	0
T266	41516	44	0	0
T293	17892	27	0	0
T294	3867	7	0	0
T295	22040	57	0	0
T296	9624	21	0	0
T298	10238	26	0	0
T299	72006	38	0	0
T300	21092	13	0	0
T301	79108	55	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	959	0	0
T249	20831	28	0	0
T266	41516	32	0	0
T293	17892	47	0	0
T294	3867	6	0	0
T295	22040	61	0	0
T296	9624	6	0	0
T298	10238	26	0	0
T299	72006	56	0	0
T300	21092	13	0	0
T301	79108	69	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	845	0	0
T249	20831	43	0	0
T266	41516	40	0	0
T293	17892	17	0	0
T294	3867	4	0	0
T295	22040	24	0	0
T296	9624	15	0	0
T297	3793	1	0	0
T298	10238	7	0	0
T299	72006	52	0	0
T300	21092	49	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	940	0	0
T249	20831	31	0	0
T266	41516	46	0	0
T293	17892	48	0	0
T294	3867	1	0	0
T295	22040	76	0	0
T296	9624	4	0	0
T297	3793	4	0	0
T298	10238	29	0	0
T299	72006	20	0	0
T300	21092	32	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	924	0	0
T249	20831	70	0	0
T266	41516	27	0	0
T293	17892	17	0	0
T294	3867	6	0	0
T295	22040	60	0	0
T296	9624	5	0	0
T297	3793	8	0	0
T298	10238	9	0	0
T299	72006	56	0	0
T300	21092	26	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	803	0	0
T249	20831	73	0	0
T266	41516	49	0	0
T293	17892	10	0	0
T294	3867	4	0	0
T295	22040	23	0	0
T296	9624	18	0	0
T297	3793	5	0	0
T298	10238	7	0	0
T299	72006	50	0	0
T300	21092	38	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	882	0	0
T249	20831	54	0	0
T266	41516	39	0	0
T293	17892	34	0	0
T294	3867	3	0	0
T295	22040	34	0	0
T296	9624	13	0	0
T297	3793	7	0	0
T298	10238	15	0	0
T299	72006	36	0	0
T300	21092	6	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415198468	744	0	0
T249	20831	32	0	0
T266	41516	46	0	0
T293	17892	14	0	0
T294	3867	1	0	0
T295	22040	9	0	0
T296	9624	18	0	0
T297	3793	4	0	0
T298	10238	6	0	0
T299	72006	24	0	0
T300	21092	33	0	0