SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_num_num_enable_bytes | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_write | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cr_all | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_num_num_enable_bytes | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_write | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cr_all | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
partial | 26968747 | 1 | T1 | 104 | T2 | 6811 | T3 | 830 | |||
full_word | 7835746 | 1 | T1 | 55 | T2 | 3913 | T3 | 2622 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 34804193 | 1 | T1 | 159 | T2 | 10724 | T3 | 3452 | |||
auto[TlIntgErrCmd] | 97 | 1 | T69 | 2 | T70 | 7 | T225 | 3 | |||
auto[TlIntgErrData] | 107 | 1 | T69 | 7 | T70 | 10 | T225 | 3 | |||
auto[TlIntgErrBoth] | 96 | 1 | T69 | 1 | T70 | 3 | T225 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 30419098 | 1 | T1 | 58 | T2 | 6474 | T3 | 1245 | |||
auto[1] | 4385395 | 1 | T1 | 101 | T2 | 4250 | T3 | 2207 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 16 | 0 | 16 | 100.00 |
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | partial | auto[0] | 26305170 | 1 | T1 | 57 | T2 | 6469 | T3 | 651 | |||
auto[TlIntgErrNone] | partial | auto[1] | 663298 | 1 | T1 | 47 | T2 | 342 | T3 | 179 | |||
auto[TlIntgErrNone] | full_word | auto[0] | 4113787 | 1 | T1 | 1 | T2 | 5 | T3 | 594 | |||
auto[TlIntgErrNone] | full_word | auto[1] | 3721938 | 1 | T1 | 54 | T2 | 3908 | T3 | 2028 | |||
auto[TlIntgErrCmd] | partial | auto[0] | 34 | 1 | T70 | 4 | T225 | 2 | T266 | 2 | |||
auto[TlIntgErrCmd] | partial | auto[1] | 55 | 1 | T69 | 2 | T70 | 2 | T225 | 1 | |||
auto[TlIntgErrCmd] | full_word | auto[0] | 6 | 1 | T70 | 1 | T345 | 1 | T350 | 1 | |||
auto[TlIntgErrCmd] | full_word | auto[1] | 2 | 1 | T301 | 1 | T349 | 1 | - | - | |||
auto[TlIntgErrData] | partial | auto[0] | 56 | 1 | T69 | 6 | T70 | 5 | T225 | 1 | |||
auto[TlIntgErrData] | partial | auto[1] | 44 | 1 | T69 | 1 | T70 | 5 | T225 | 2 | |||
auto[TlIntgErrData] | full_word | auto[0] | 3 | 1 | T351 | 1 | T346 | 1 | T349 | 1 | |||
auto[TlIntgErrData] | full_word | auto[1] | 4 | 1 | T301 | 1 | T353 | 2 | T349 | 1 | |||
auto[TlIntgErrBoth] | partial | auto[0] | 38 | 1 | T70 | 1 | T225 | 2 | T266 | 2 | |||
auto[TlIntgErrBoth] | partial | auto[1] | 52 | 1 | T69 | 1 | T70 | 2 | T225 | 2 | |||
auto[TlIntgErrBoth] | full_word | auto[0] | 4 | 1 | T301 | 1 | T353 | 1 | T354 | 1 | |||
auto[TlIntgErrBoth] | full_word | auto[1] | 2 | 1 | T354 | 1 | T348 | 1 | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
partial | 18673 | 1 | T69 | 10 | T70 | 17 | T111 | 19 | |||
full_word | 4022441 | 1 | T3 | 360 | T4 | 17 | T5 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4040833 | 1 | T3 | 360 | T4 | 17 | T5 | 7 | |||
auto[TlIntgErrCmd] | 82 | 1 | T69 | 2 | T70 | 2 | T225 | 2 | |||
auto[TlIntgErrData] | 103 | 1 | T69 | 1 | T70 | 10 | T225 | 2 | |||
auto[TlIntgErrBoth] | 96 | 1 | T69 | 7 | T70 | 6 | T225 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4018047 | 1 | T3 | 360 | T4 | 17 | T5 | 7 | |||
auto[1] | 23067 | 1 | T69 | 3 | T70 | 10 | T111 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 16 | 0 | 16 | 100.00 |
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | partial | auto[0] | 1167 | 1 | T111 | 2 | T211 | 35 | T212 | 63 | |||
auto[TlIntgErrNone] | partial | auto[1] | 17249 | 1 | T111 | 17 | T211 | 303 | T212 | 423 | |||
auto[TlIntgErrNone] | full_word | auto[0] | 4016758 | 1 | T3 | 360 | T4 | 17 | T5 | 7 | |||
auto[TlIntgErrNone] | full_word | auto[1] | 5659 | 1 | T111 | 5 | T211 | 92 | T212 | 157 | |||
auto[TlIntgErrCmd] | partial | auto[0] | 18 | 1 | T69 | 1 | T70 | 1 | T225 | 1 | |||
auto[TlIntgErrCmd] | partial | auto[1] | 55 | 1 | T69 | 1 | T70 | 1 | T225 | 1 | |||
auto[TlIntgErrCmd] | full_word | auto[0] | 4 | 1 | T346 | 1 | T352 | 1 | T353 | 1 | |||
auto[TlIntgErrCmd] | full_word | auto[1] | 5 | 1 | T350 | 1 | T351 | 1 | T349 | 1 | |||
auto[TlIntgErrData] | partial | auto[0] | 50 | 1 | T70 | 5 | T266 | 3 | T345 | 8 | |||
auto[TlIntgErrData] | partial | auto[1] | 45 | 1 | T69 | 1 | T70 | 5 | T225 | 2 | |||
auto[TlIntgErrData] | full_word | auto[0] | 5 | 1 | T266 | 1 | T345 | 1 | T351 | 1 | |||
auto[TlIntgErrData] | full_word | auto[1] | 3 | 1 | T299 | 1 | T346 | 1 | T355 | 1 | |||
auto[TlIntgErrBoth] | partial | auto[0] | 42 | 1 | T69 | 6 | T70 | 2 | T225 | 2 | |||
auto[TlIntgErrBoth] | partial | auto[1] | 47 | 1 | T69 | 1 | T70 | 3 | T225 | 1 | |||
auto[TlIntgErrBoth] | full_word | auto[0] | 3 | 1 | T301 | 1 | T356 | 2 | - | - | |||
auto[TlIntgErrBoth] | full_word | auto[1] | 4 | 1 | T70 | 1 | T225 | 1 | T299 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |