Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T30
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1651360412	1648084760	0	0
CheckNGreaterZero_A	4160	4160	0	0
GntImpliesReady_A	1651360412	414216040	0	0
GntImpliesValid_A	1651360412	414216040	0	0
GrantKnown_A	1651360412	1648084760	0	0
IdxKnown_A	1651360412	1648084760	0	0
IndexIsCorrect_A	1651360412	414216040	0	0
NoReadyValidNoGrant_A	1651360412	178479045	0	0
Priority_A	1651360412	438304055	0	0
ReadyAndValidImplyGrant_A	1651360412	414216040	0	0
ReqAndReadyImplyGrant_A	1651360412	414216040	0	0
ReqImpliesValid_A	1651360412	438304055	0	0
ValidKnown_A	1651360412	1648084760	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	1648084760	0	0
T1	10248	9912	0	0
T2	399228	395424	0	0
T3	120468	120268	0	0
T4	26912	26132	0	0
T5	10712	10128	0	0
T11	14248	11468	0	0
T12	15572	12784	0	0
T21	5172	4800	0	0
T22	3780	3552	0	0
T23	275324	275028	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4160	4160	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	414216040	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	38062	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	414216040	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	38062	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	1648084760	0	0
T1	10248	9912	0	0
T2	399228	395424	0	0
T3	120468	120268	0	0
T4	26912	26132	0	0
T5	10712	10128	0	0
T11	14248	11468	0	0
T12	15572	12784	0	0
T21	5172	4800	0	0
T22	3780	3552	0	0
T23	275324	275028	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	1648084760	0	0
T1	10248	9912	0	0
T2	399228	395424	0	0
T3	120468	120268	0	0
T4	26912	26132	0	0
T5	10712	10128	0	0
T11	14248	11468	0	0
T12	15572	12784	0	0
T21	5172	4800	0	0
T22	3780	3552	0	0
T23	275324	275028	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	414216040	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	38062	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	178479045	0	0
T1	5124	256	0	0
T2	199614	256	0	0
T3	120468	2786	0	0
T4	26912	1528	0	0
T5	10712	982	0	0
T6	0	56236	0	0
T11	14248	928	0	0
T12	15572	1600	0	0
T13	2326	0	0	0
T21	5172	256	0	0
T22	3780	256	0	0
T23	275324	320	0	0
T29	0	76	0	0
T30	12882	172	0	0
T36	0	7900	0	0
T48	0	42	0	0
T64	0	1966	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	438304055	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	43970	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	414216040	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	38062	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	414216040	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	38062	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	438304055	0	0
T1	5124	64	0	0
T2	399228	74538	0	0
T3	120468	1740	0	0
T4	26912	6290	0	0
T5	10712	448	0	0
T6	0	43970	0	0
T11	14248	256	0	0
T12	15572	400	0	0
T21	5172	64	0	0
T22	3780	64	0	0
T23	275324	132034	0	0
T29	0	26	0	0
T30	12882	3742	0	0
T36	0	180744	0	0
T64	0	644428	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651360412	1648084760	0	0
T1	10248	9912	0	0
T2	399228	395424	0	0
T3	120468	120268	0	0
T4	26912	26132	0	0
T5	10712	10128	0	0
T11	14248	11468	0	0
T12	15572	12784	0	0
T21	5172	4800	0	0
T22	3780	3552	0	0
T23	275324	275028	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T30
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412840103	412021190	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	412840103	107359170	0	0
GntImpliesValid_A	412840103	107359170	0	0
GrantKnown_A	412840103	412021190	0	0
IdxKnown_A	412840103	412021190	0	0
IndexIsCorrect_A	412840103	107359170	0	0
NoReadyValidNoGrant_A	412840103	45665390	0	0
Priority_A	412840103	113592913	0	0
ReadyAndValidImplyGrant_A	412840103	107359170	0	0
ReqAndReadyImplyGrant_A	412840103	107359170	0	0
ReqImpliesValid_A	412840103	113592913	0	0
ValidKnown_A	412840103	412021190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359170	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359170	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359170	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	45665390	0	0
T1	2562	128	0	0
T2	99807	128	0	0
T3	30117	679	0	0
T4	6728	556	0	0
T5	2678	433	0	0
T11	3562	464	0	0
T12	3893	800	0	0
T21	1293	128	0	0
T22	945	128	0	0
T23	68831	139	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	113592913	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359170	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359170	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	113592913	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T30
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412840103	412021190	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	412840103	107359107	0	0
GntImpliesValid_A	412840103	107359107	0	0
GrantKnown_A	412840103	412021190	0	0
IdxKnown_A	412840103	412021190	0	0
IndexIsCorrect_A	412840103	107359107	0	0
NoReadyValidNoGrant_A	412840103	45665390	0	0
Priority_A	412840103	113592850	0	0
ReadyAndValidImplyGrant_A	412840103	107359107	0	0
ReqAndReadyImplyGrant_A	412840103	107359107	0	0
ReqImpliesValid_A	412840103	113592850	0	0
ValidKnown_A	412840103	412021190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359107	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359107	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359107	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	45665390	0	0
T1	2562	128	0	0
T2	99807	128	0	0
T3	30117	679	0	0
T4	6728	556	0	0
T5	2678	433	0	0
T11	3562	464	0	0
T12	3893	800	0	0
T21	1293	128	0	0
T22	945	128	0	0
T23	68831	139	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	113592850	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359107	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	107359107	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	113592850	0	0
T1	2562	32	0	0
T2	99807	17409	0	0
T3	30117	398	0	0
T4	6728	1234	0	0
T5	2678	202	0	0
T11	3562	128	0	0
T12	3893	200	0	0
T21	1293	32	0	0
T22	945	32	0	0
T23	68831	463	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T30
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412840103	412021190	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	412840103	99748909	0	0
GntImpliesValid_A	412840103	99748909	0	0
GrantKnown_A	412840103	412021190	0	0
IdxKnown_A	412840103	412021190	0	0
IndexIsCorrect_A	412840103	99748909	0	0
NoReadyValidNoGrant_A	412840103	43574158	0	0
Priority_A	412840103	105559148	0	0
ReadyAndValidImplyGrant_A	412840103	99748909	0	0
ReqAndReadyImplyGrant_A	412840103	99748909	0	0
ReqImpliesValid_A	412840103	105559148	0	0
ValidKnown_A	412840103	412021190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748909	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748909	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748909	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	43574158	0	0
T3	30117	714	0	0
T4	6728	208	0	0
T5	2678	58	0	0
T6	0	28118	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T13	1163	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	21	0	0
T29	0	38	0	0
T30	6441	86	0	0
T36	0	3950	0	0
T48	0	21	0	0
T64	0	983	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	105559148	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	21985	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748909	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748909	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	105559148	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	21985	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T30
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T30
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412840103	412021190	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	412840103	99748854	0	0
GntImpliesValid_A	412840103	99748854	0	0
GrantKnown_A	412840103	412021190	0	0
IdxKnown_A	412840103	412021190	0	0
IndexIsCorrect_A	412840103	99748854	0	0
NoReadyValidNoGrant_A	412840103	43574107	0	0
Priority_A	412840103	105559144	0	0
ReadyAndValidImplyGrant_A	412840103	99748854	0	0
ReqAndReadyImplyGrant_A	412840103	99748854	0	0
ReqImpliesValid_A	412840103	105559144	0	0
ValidKnown_A	412840103	412021190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748854	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748854	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748854	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	43574107	0	0
T3	30117	714	0	0
T4	6728	208	0	0
T5	2678	58	0	0
T6	0	28118	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T13	1163	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	21	0	0
T29	0	38	0	0
T30	6441	86	0	0
T36	0	3950	0	0
T48	0	21	0	0
T64	0	983	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	105559144	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	21985	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748854	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	99748854	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	19031	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	105559144	0	0
T2	99807	19860	0	0
T3	30117	472	0	0
T4	6728	1911	0	0
T5	2678	22	0	0
T6	0	21985	0	0
T11	3562	0	0	0
T12	3893	0	0	0
T21	1293	0	0	0
T22	945	0	0	0
T23	68831	65554	0	0
T29	0	13	0	0
T30	6441	1871	0	0
T36	0	90372	0	0
T64	0	322214	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412840103	412021190	0	0
T1	2562	2478	0	0
T2	99807	98856	0	0
T3	30117	30067	0	0
T4	6728	6533	0	0
T5	2678	2532	0	0
T11	3562	2867	0	0
T12	3893	3196	0	0
T21	1293	1200	0	0
T22	945	888	0	0
T23	68831	68757	0	0