Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22992814	1		T1	15		T2	195		T3	14202
full_word	7446439	1		T1	1		T2	47		T3	9843

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30438963	1		T1	16		T2	242		T3	24045
auto[TlIntgErrCmd]	101	1		T97	7		T228	3		T233	4
auto[TlIntgErrData]	98	1		T97	8		T228	3		T233	2
auto[TlIntgErrBoth]	91	1		T97	5		T228	4		T233	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26079001	1		T1	15		T2	191		T3	20063
auto[1]	4360252	1		T1	1		T2	51		T3	3982

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22332368	1		T1	15		T2	190		T3	13119
auto[TlIntgErrNone]	partial	auto[1]	660183	1		T2	5		T3	1083		T4	905
auto[TlIntgErrNone]	full_word	auto[0]	3746503	1		T2	1		T3	6944		T4	8455
auto[TlIntgErrNone]	full_word	auto[1]	3699909	1		T1	1		T2	46		T3	2899
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T97	3		T228	1		T233	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T97	3		T228	2		T233	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T97	1		T270	1		T257	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T362	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1		T97	4		T233	1		T270	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T97	2		T228	3		T233	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T275	1		T262	1		T266	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T97	2		T270	1		T275	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T97	3		T228	2		T233	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T97	1		T233	2		T270	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T228	1		T263	1		T266	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T97	1		T228	1		T233	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20585	1		T95	1189		T99	1132		T96	92
full_word	4000565	1		T3	16360		T4	16574		T5	12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4020881	1		T3	16360		T4	16574		T5	12
auto[TlIntgErrCmd]	107	1		T97	8		T228	6		T233	2
auto[TlIntgErrData]	75	1		T97	6		T228	2		T233	1
auto[TlIntgErrBoth]	87	1		T97	5		T228	2		T233	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3994203	1		T3	16360		T4	16574		T5	12
auto[1]	26947	1		T95	1516		T99	1288		T96	118

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1313	1		T95	45		T99	99		T96	6
auto[TlIntgErrNone]	partial	auto[1]	19021	1		T95	1144		T99	1033		T96	86
auto[TlIntgErrNone]	full_word	auto[0]	3992779	1		T3	16360		T4	16574		T5	12
auto[TlIntgErrNone]	full_word	auto[1]	7768	1		T95	372		T99	255		T96	32
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T97	4		T270	3		T277	2
auto[TlIntgErrCmd]	partial	auto[1]	70	1		T97	4		T228	5		T233	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T363	1		T266	1		T364	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T228	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	33	1		T97	2		T228	1		T233	1
auto[TlIntgErrData]	partial	auto[1]	35	1		T97	4		T228	1		T270	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T363	1		T263	1		T266	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T275	1		T278	1		T362	2
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T97	2		T228	2		T277	3
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T97	2		T233	4		T275	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T363	1		T267	1		T364	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T97	1		T302	1		T262	1