Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1501840688	1498529160	0	0
CheckNGreaterZero_A	4168	4168	0	0
GntImpliesReady_A	1501840688	399654397	0	0
GntImpliesValid_A	1501840688	399654397	0	0
GrantKnown_A	1501840688	1498529160	0	0
IdxKnown_A	1501840688	1498529160	0	0
IndexIsCorrect_A	1501840688	399654397	0	0
NoReadyValidNoGrant_A	1501840688	172862352	0	0
Priority_A	1501840688	423588079	0	0
ReadyAndValidImplyGrant_A	1501840688	399654397	0	0
ReqAndReadyImplyGrant_A	1501840688	399654397	0	0
ReqImpliesValid_A	1501840688	423588079	0	0
ValidKnown_A	1501840688	1498529160	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	1498529160	0	0
T1	5708	5352	0	0
T2	4932	4700	0	0
T3	248364	247968	0	0
T4	234512	234300	0	0
T5	7492	7000	0	0
T6	1148064	1147700	0	0
T11	964808	964268	0	0
T14	54904	54648	0	0
T15	4004	3684	0	0
T16	109740	109060	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4168	4168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T11	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	399654397	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	41570	0	0
T4	234512	46604	0	0
T5	7492	450	0	0
T6	1148064	374446	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	6724	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	83672	0	0
T52	2792	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	399654397	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	41570	0	0
T4	234512	46604	0	0
T5	7492	450	0	0
T6	1148064	374446	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	6724	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	83672	0	0
T52	2792	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	1498529160	0	0
T1	5708	5352	0	0
T2	4932	4700	0	0
T3	248364	247968	0	0
T4	234512	234300	0	0
T5	7492	7000	0	0
T6	1148064	1147700	0	0
T11	964808	964268	0	0
T14	54904	54648	0	0
T15	4004	3684	0	0
T16	109740	109060	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	1498529160	0	0
T1	5708	5352	0	0
T2	4932	4700	0	0
T3	248364	247968	0	0
T4	234512	234300	0	0
T5	7492	7000	0	0
T6	1148064	1147700	0	0
T11	964808	964268	0	0
T14	54904	54648	0	0
T15	4004	3684	0	0
T16	109740	109060	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	399654397	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	41570	0	0
T4	234512	46604	0	0
T5	7492	450	0	0
T6	1148064	374446	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	6724	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	83672	0	0
T52	2792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	172862352	0	0
T1	2854	256	0	0
T2	2466	256	0	0
T3	248364	118670	0	0
T4	234512	61560	0	0
T5	7492	954	0	0
T6	1148064	156602	0	0
T11	964808	256	0	0
T14	54904	3522	0	0
T15	4004	256	0	0
T16	109740	2229	0	0
T18	0	112	0	0
T21	0	194	0	0
T39	260118	65822	0	0
T51	0	93126	0	0
T52	2792	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	423588079	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	44664	0	0
T4	234512	57656	0	0
T5	7492	450	0	0
T6	1148064	427408	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	7047	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	90272	0	0
T52	2792	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	399654397	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	41570	0	0
T4	234512	46604	0	0
T5	7492	450	0	0
T6	1148064	374446	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	6724	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	83672	0	0
T52	2792	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	399654397	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	41570	0	0
T4	234512	46604	0	0
T5	7492	450	0	0
T6	1148064	374446	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	6724	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	83672	0	0
T52	2792	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	423588079	0	0
T1	2854	64	0	0
T2	2466	584	0	0
T3	248364	44664	0	0
T4	234512	57656	0	0
T5	7492	450	0	0
T6	1148064	427408	0	0
T7	0	1174	0	0
T11	964808	846	0	0
T14	54904	2262	0	0
T15	4004	64	0	0
T16	109740	7047	0	0
T21	0	1120	0	0
T22	0	1515290	0	0
T39	260118	90272	0	0
T52	2792	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501840688	1498529160	0	0
T1	5708	5352	0	0
T2	4932	4700	0	0
T3	248364	247968	0	0
T4	234512	234300	0	0
T5	7492	7000	0	0
T6	1148064	1147700	0	0
T11	964808	964268	0	0
T14	54904	54648	0	0
T15	4004	3684	0	0
T16	109740	109060	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375460172	374632290	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	375460172	107925764	0	0
GntImpliesValid_A	375460172	107925764	0	0
GrantKnown_A	375460172	374632290	0	0
IdxKnown_A	375460172	374632290	0	0
IndexIsCorrect_A	375460172	107925764	0	0
NoReadyValidNoGrant_A	375460172	45206616	0	0
Priority_A	375460172	114040552	0	0
ReadyAndValidImplyGrant_A	375460172	107925764	0	0
ReqAndReadyImplyGrant_A	375460172	107925764	0	0
ReqImpliesValid_A	375460172	114040552	0	0
ValidKnown_A	375460172	374632290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925764	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3241	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925764	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3241	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925764	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3241	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	45206616	0	0
T1	1427	128	0	0
T2	1233	128	0	0
T3	62091	28567	0	0
T4	58628	15320	0	0
T5	1873	413	0	0
T6	287016	40912	0	0
T11	241202	128	0	0
T14	13726	729	0	0
T15	1001	128	0	0
T16	27435	1056	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	114040552	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	10815	0	0
T4	58628	14103	0	0
T5	1873	197	0	0
T6	287016	115891	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3283	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925764	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3241	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925764	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3241	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	114040552	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	10815	0	0
T4	58628	14103	0	0
T5	1873	197	0	0
T6	287016	115891	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3283	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375460172	374632290	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	375460172	107925770	0	0
GntImpliesValid_A	375460172	107925770	0	0
GrantKnown_A	375460172	374632290	0	0
IdxKnown_A	375460172	374632290	0	0
IndexIsCorrect_A	375460172	107925770	0	0
NoReadyValidNoGrant_A	375460172	45206549	0	0
Priority_A	375460172	114040625	0	0
ReadyAndValidImplyGrant_A	375460172	107925770	0	0
ReqAndReadyImplyGrant_A	375460172	107925770	0	0
ReqImpliesValid_A	375460172	114040625	0	0
ValidKnown_A	375460172	374632290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925770	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3247	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925770	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3247	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925770	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3247	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	45206549	0	0
T1	1427	128	0	0
T2	1233	128	0	0
T3	62091	28567	0	0
T4	58628	15320	0	0
T5	1873	413	0	0
T6	287016	40912	0	0
T11	241202	128	0	0
T14	13726	729	0	0
T15	1001	128	0	0
T16	27435	989	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	114040625	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	10815	0	0
T4	58628	14103	0	0
T5	1873	197	0	0
T6	287016	115891	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3356	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925770	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3247	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	107925770	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	9993	0	0
T4	58628	11426	0	0
T5	1873	197	0	0
T6	287016	103532	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3247	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	114040625	0	0
T1	1427	32	0	0
T2	1233	292	0	0
T3	62091	10815	0	0
T4	58628	14103	0	0
T5	1873	197	0	0
T6	287016	115891	0	0
T11	241202	423	0	0
T14	13726	438	0	0
T15	1001	32	0	0
T16	27435	3356	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375460172	374632290	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	375460172	91901437	0	0
GntImpliesValid_A	375460172	91901437	0	0
GrantKnown_A	375460172	374632290	0	0
IdxKnown_A	375460172	374632290	0	0
IndexIsCorrect_A	375460172	91901437	0	0
NoReadyValidNoGrant_A	375460172	41224599	0	0
Priority_A	375460172	97753451	0	0
ReadyAndValidImplyGrant_A	375460172	91901437	0	0
ReqAndReadyImplyGrant_A	375460172	91901437	0	0
ReqImpliesValid_A	375460172	97753451	0	0
ValidKnown_A	375460172	374632290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901437	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901437	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901437	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	41224599	0	0
T3	62091	30768	0	0
T4	58628	15460	0	0
T5	1873	64	0	0
T6	287016	37389	0	0
T11	241202	0	0	0
T14	13726	1032	0	0
T15	1001	0	0	0
T16	27435	92	0	0
T18	0	56	0	0
T21	0	97	0	0
T39	130059	32911	0	0
T51	0	46563	0	0
T52	1396	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	97753451	0	0
T3	62091	11517	0	0
T4	58628	14725	0	0
T5	1873	28	0	0
T6	287016	97813	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	204	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	45136	0	0
T52	1396	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901437	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901437	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	97753451	0	0
T3	62091	11517	0	0
T4	58628	14725	0	0
T5	1873	28	0	0
T6	287016	97813	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	204	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	45136	0	0
T52	1396	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375460172	374632290	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	375460172	91901426	0	0
GntImpliesValid_A	375460172	91901426	0	0
GrantKnown_A	375460172	374632290	0	0
IdxKnown_A	375460172	374632290	0	0
IndexIsCorrect_A	375460172	91901426	0	0
NoReadyValidNoGrant_A	375460172	41224588	0	0
Priority_A	375460172	97753451	0	0
ReadyAndValidImplyGrant_A	375460172	91901426	0	0
ReqAndReadyImplyGrant_A	375460172	91901426	0	0
ReqImpliesValid_A	375460172	97753451	0	0
ValidKnown_A	375460172	374632290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901426	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901426	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901426	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	41224588	0	0
T3	62091	30768	0	0
T4	58628	15460	0	0
T5	1873	64	0	0
T6	287016	37389	0	0
T11	241202	0	0	0
T14	13726	1032	0	0
T15	1001	0	0	0
T16	27435	92	0	0
T18	0	56	0	0
T21	0	97	0	0
T39	130059	32911	0	0
T51	0	46563	0	0
T52	1396	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	97753451	0	0
T3	62091	11517	0	0
T4	58628	14725	0	0
T5	1873	28	0	0
T6	287016	97813	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	204	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	45136	0	0
T52	1396	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901426	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	91901426	0	0
T3	62091	10792	0	0
T4	58628	11876	0	0
T5	1873	28	0	0
T6	287016	83691	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	118	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	41836	0	0
T52	1396	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	97753451	0	0
T3	62091	11517	0	0
T4	58628	14725	0	0
T5	1873	28	0	0
T6	287016	97813	0	0
T7	0	587	0	0
T11	241202	0	0	0
T14	13726	693	0	0
T15	1001	0	0	0
T16	27435	204	0	0
T21	0	560	0	0
T22	0	757645	0	0
T39	130059	45136	0	0
T52	1396	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0