Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.06	100.00	92.45		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.74	100.00	85.85		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.87	100.00	91.51		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	85.85		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.36	97.07	92.84	96.90	100.00	99.29	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.33	97.64	93.07	100.00		99.37	96.55
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	97.07	93.53	100.00	100.00	99.29	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.49	100.00	96.92	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.39	97.64	93.39	100.00		99.37	96.55
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	98	92.45
Logical	106	98	92.45
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T7,T213

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T7,T213

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T63
1	1	1	Covered	T4,T5,T6

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T75,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T26

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T63
1	0	Covered	T58,T214,T215

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T58,T214,T215

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T63

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T56
1	0	Covered	T1,T2,T10

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T42
1	0	Covered	T13,T14,T42

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T15

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T15

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T15

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T15

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T1,T2,T10
StCtrlProg	339	Covered	T1,T2,T3
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T10,T11,T12
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T1,T2,T10
StCtrlProg->StIdle	359	Covered	T1,T2,T3
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T1,T2,T10
StIdle->StCtrlProg	339	Covered	T1,T2,T3
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T10,T11,T12

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T26
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T213
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	0	1	-	-	-	Covered	T1,T2,T10
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T2,T3
StCtrl	-	-	-	-	-	-	1	Covered	T1,T2,T10
StCtrl	-	-	-	-	-	-	0	Covered	T1,T2,T10
StDisable	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Covered	T7,T13,T14

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	783949776	2703557	0	0
CtrlPrio_A	783949776	2703552	0	0
HostTransIdleChk_A	783949776	44916941	0	0
NoRemainder_A	2092	2092	0	0
OneHotReqs_A	783949776	782193206	0	0
Pow2Multiple_A	2092	2092	0	0
RdTxnCheck_A	783529688	781773118	0	0
u_state_regs_A	783949776	782193206	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783949776	2703557	0	0
T5	102556	2463	0	0
T6	1122214	0	0	0
T19	84230	0	0	0
T20	0	4548	0	0
T24	0	3986	0	0
T26	236356	86726	0	0
T27	0	5824	0	0
T28	0	72718	0	0
T38	141600	4799	0	0
T46	0	15	0	0
T47	3000	0	0	0
T56	794626	0	0	0
T57	484540	0	0	0
T59	0	27	0	0
T60	2534	0	0	0
T61	8232	0	0	0
T125	0	12691	0	0
T192	0	8284	0	0
T195	0	4848	0	0
T208	0	84460	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783949776	2703552	0	0
T5	102556	2463	0	0
T6	1122214	0	0	0
T19	84230	0	0	0
T20	0	4548	0	0
T24	0	3986	0	0
T26	236356	86726	0	0
T27	0	5824	0	0
T28	0	72718	0	0
T38	141600	4799	0	0
T46	0	15	0	0
T47	3000	0	0	0
T56	794626	0	0	0
T57	484540	0	0	0
T59	0	27	0	0
T60	2534	0	0	0
T61	8232	0	0	0
T125	0	12691	0	0
T192	0	8284	0	0
T195	0	4848	0	0
T208	0	84460	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783949776	44916941	0	0
T5	102556	33661	0	0
T6	1122214	817581	0	0
T19	84230	342	0	0
T20	0	57552	0	0
T26	236356	837522	0	0
T27	0	59490	0	0
T28	0	792387	0	0
T38	141600	59335	0	0
T47	3000	0	0	0
T56	794626	0	0	0
T57	484540	0	0	0
T58	0	20	0	0
T59	0	357	0	0
T60	2534	0	0	0
T61	8232	0	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2092	2092	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783949776	782193206	0	0
T1	293372	293188	0	0
T2	345260	345080	0	0
T3	7736	7626	0	0
T4	880	776	0	0
T10	1688284	1688236	0	0
T11	2942	2556	0	0
T12	8326	7002	0	0
T15	390342	390196	0	0
T16	770520	770496	0	0
T17	1804	1686	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2092	2092	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783529688	781773118	0	0
T1	293372	293188	0	0
T2	345260	345080	0	0
T3	7736	7626	0	0
T4	880	776	0	0
T10	1688284	1688236	0	0
T11	2942	2556	0	0
T12	8326	7002	0	0
T15	390342	390196	0	0
T16	770520	770496	0	0
T17	1804	1686	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783949776	782193206	0	0
T1	293372	293188	0	0
T2	345260	345080	0	0
T3	7736	7626	0	0
T4	880	776	0	0
T10	1688284	1688236	0	0
T11	2942	2556	0	0
T12	8326	7002	0	0
T15	390342	390196	0	0
T16	770520	770496	0	0
T17	1804	1686	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	91	85.85
Logical	106	91	85.85
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T75
1	0	Covered	T1,T3,T10
1	1	Covered	T4,T5,T6

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T10
1	1	Covered	T5,T26,T38

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T15
1	1	Covered	T1,T3,T10

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T16
1	1	Covered	T1,T10,T15

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T15
1	1	Covered	T1,T3,T10

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T10,T15

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T10,T16

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T56
1	0	Covered	T1,T2,T10

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T15
1	1	Covered	T1,T3,T10

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T42
1	0	Covered	T13,T14,T42

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T4,T16
1	0	Covered	T10,T15,T16

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T16,T56
1	0	Covered	T10,T15,T16

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T15,T16

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T15,T16

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T1,T10,T16
StCtrlProg	339	Covered	T1,T10,T15
StCtrlRead	337	Covered	T1,T3,T10
StDisable	335	Covered	T10,T11,T12
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T1,T10,T16
StCtrlProg->StIdle	359	Covered	T1,T10,T15
StCtrlRead->StIdle	349	Covered	T1,T3,T10
StIdle->StCtrl	341	Covered	T1,T10,T16
StIdle->StCtrlProg	339	Covered	T1,T10,T15
StIdle->StCtrlRead	337	Covered	T1,T3,T10
StIdle->StDisable	335	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T10
0	0	1	Covered	T5,T26,T38
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7
0	0	0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	Covered	T1,T3,T10
StIdle	0	0	1	-	-	-	-	Covered	T1,T10,T15
StIdle	0	0	0	1	-	-	-	Covered	T1,T10,T16
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T3,T10
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T3,T10
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T10,T15
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T10,T15
StCtrl	-	-	-	-	-	-	1	Covered	T1,T10,T16
StCtrl	-	-	-	-	-	-	0	Covered	T1,T10,T16
StDisable	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Covered	T7,T13,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	391974888	1230282	0	0
CtrlPrio_A	391974888	1230277	0	0
HostTransIdleChk_A	391974888	22353759	0	0
NoRemainder_A	1046	1046	0	0
OneHotReqs_A	391974888	391096603	0	0
Pow2Multiple_A	1046	1046	0	0
RdTxnCheck_A	391764844	390886559	0	0
u_state_regs_A	391974888	391096603	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	1230282	0	0
T5	51278	610	0	0
T6	561107	0	0	0
T19	42115	0	0	0
T20	0	3025	0	0
T26	118178	43672	0	0
T27	0	2744	0	0
T28	0	27501	0	0
T38	70800	2179	0	0
T46	0	15	0	0
T47	1500	0	0	0
T56	397313	0	0	0
T57	242270	0	0	0
T60	1267	0	0	0
T61	4116	0	0	0
T125	0	12691	0	0
T192	0	8284	0	0
T208	0	32651	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	1230277	0	0
T5	51278	610	0	0
T6	561107	0	0	0
T19	42115	0	0	0
T20	0	3025	0	0
T26	118178	43672	0	0
T27	0	2744	0	0
T28	0	27501	0	0
T38	70800	2179	0	0
T46	0	15	0	0
T47	1500	0	0	0
T56	397313	0	0	0
T57	242270	0	0	0
T60	1267	0	0	0
T61	4116	0	0	0
T125	0	12691	0	0
T192	0	8284	0	0
T208	0	32651	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	22353759	0	0
T5	51278	17230	0	0
T6	561107	408561	0	0
T19	42115	99	0	0
T20	0	28944	0	0
T26	118178	422076	0	0
T27	0	28159	0	0
T28	0	396321	0	0
T38	70800	29534	0	0
T47	1500	0	0	0
T56	397313	0	0	0
T57	242270	0	0	0
T58	0	12	0	0
T59	0	101	0	0
T60	1267	0	0	0
T61	4116	0	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391764844	390886559	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T7,T213

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T7,T213

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T63
1	1	1	Covered	T4,T5,T6

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T76
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T26

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T15
1	0	Covered	T2,T10,T12
1	1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T63
1	0	Covered	T58,T214,T215

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T58,T214,T215

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T63

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T16

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T56
1	0	Covered	T1,T2,T10

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T42
1	0	Covered	T13,T14,T42

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T15

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T15

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T15

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T15

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T2,T10,T12
StCtrlProg	339	Covered	T1,T2,T3
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T10,T12,T16
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T2,T10,T12
StCtrlProg->StIdle	359	Covered	T1,T2,T3
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T2,T10,T12
StIdle->StCtrlProg	339	Covered	T1,T2,T3
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T10,T12,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T26
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T213
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	0	1	-	-	-	Covered	T2,T10,T12
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T2,T3
StCtrl	-	-	-	-	-	-	1	Covered	T2,T10,T16
StCtrl	-	-	-	-	-	-	0	Covered	T2,T10,T12
StDisable	-	-	-	-	-	-	-	Covered	T10,T12,T16
default	-	-	-	-	-	-	-	Covered	T7,T13,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	391974888	1473275	0	0
CtrlPrio_A	391974888	1473275	0	0
HostTransIdleChk_A	391974888	22563182	0	0
NoRemainder_A	1046	1046	0	0
OneHotReqs_A	391974888	391096603	0	0
Pow2Multiple_A	1046	1046	0	0
RdTxnCheck_A	391764844	390886559	0	0
u_state_regs_A	391974888	391096603	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	1473275	0	0
T5	51278	1853	0	0
T6	561107	0	0	0
T19	42115	0	0	0
T20	0	1523	0	0
T24	0	3986	0	0
T26	118178	43054	0	0
T27	0	3080	0	0
T28	0	45217	0	0
T38	70800	2620	0	0
T47	1500	0	0	0
T56	397313	0	0	0
T57	242270	0	0	0
T59	0	27	0	0
T60	1267	0	0	0
T61	4116	0	0	0
T195	0	4848	0	0
T208	0	51809	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	1473275	0	0
T5	51278	1853	0	0
T6	561107	0	0	0
T19	42115	0	0	0
T20	0	1523	0	0
T24	0	3986	0	0
T26	118178	43054	0	0
T27	0	3080	0	0
T28	0	45217	0	0
T38	70800	2620	0	0
T47	1500	0	0	0
T56	397313	0	0	0
T57	242270	0	0	0
T59	0	27	0	0
T60	1267	0	0	0
T61	4116	0	0	0
T195	0	4848	0	0
T208	0	51809	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	22563182	0	0
T5	51278	16431	0	0
T6	561107	409020	0	0
T19	42115	243	0	0
T20	0	28608	0	0
T26	118178	415446	0	0
T27	0	31331	0	0
T28	0	396066	0	0
T38	70800	29801	0	0
T47	1500	0	0	0
T56	397313	0	0	0
T57	242270	0	0	0
T58	0	8	0	0
T59	0	256	0	0
T60	1267	0	0	0
T61	4116	0	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391764844	390886559	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0