Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26552654	1		T1	65		T2	122038		T3	97
full_word	7596259	1		T1	60		T2	21041		T3	45

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34148633	1		T1	125		T2	143079		T3	142
auto[TlIntgErrCmd]	88	1		T72	2		T205	1		T206	3
auto[TlIntgErrData]	112	1		T72	7		T205	4		T206	6
auto[TlIntgErrBoth]	80	1		T72	1		T205	5		T206	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29753840	1		T1	84		T2	142642		T3	91
auto[1]	4395073	1		T1	41		T2	437		T3	51

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25870464	1		T1	60		T2	121990		T3	89
auto[TlIntgErrNone]	partial	auto[1]	681927	1		T1	5		T2	48		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	3883248	1		T1	24		T2	20652		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	3712994	1		T1	36		T2	389		T3	43
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T72	1		T206	1		T222	6
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T72	1		T205	1		T206	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T222	1		T349	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T350	1		T349	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1		T72	1		T205	2		T206	3
auto[TlIntgErrData]	partial	auto[1]	50	1		T72	6		T205	1		T206	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T205	1		T206	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1		T346	1		T258	1		T352	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T72	1		T205	1		T222	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T205	4		T206	1		T222	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T256	1		T345	1		T347	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21973	1		T70	126		T72	8		T98	50
full_word	3887899	1		T3	22		T6	16718		T7	16175

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3909608	1		T3	22		T6	16718		T7	16175
auto[TlIntgErrCmd]	83	1		T72	2		T205	5		T206	4
auto[TlIntgErrData]	90	1		T72	7		T205	4		T206	4
auto[TlIntgErrBoth]	91	1		T72	1		T205	1		T206	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3882417	1		T3	22		T6	16718		T7	16175
auto[1]	27455	1		T70	150		T72	7		T98	67

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1382	1		T70	9		T98	5		T201	7
auto[TlIntgErrNone]	partial	auto[1]	20357	1		T70	117		T98	45		T201	91
auto[TlIntgErrNone]	full_word	auto[0]	3880929	1		T3	22		T6	16718		T7	16175
auto[TlIntgErrNone]	full_word	auto[1]	6940	1		T70	33		T98	22		T201	8
auto[TlIntgErrCmd]	partial	auto[0]	28	1		T72	1		T205	1		T206	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T72	1		T205	3		T206	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T222	1		T353	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T205	1		T257	1		T353	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T72	1		T205	3		T206	2
auto[TlIntgErrData]	partial	auto[1]	37	1		T72	4		T205	1		T206	2
auto[TlIntgErrData]	full_word	auto[0]	8	1		T72	1		T256	1		T346	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T72	1		T222	1		T256	2
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T205	1		T222	1		T345	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T72	1		T206	1		T222	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T222	1		T347	1		T258	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T222	2		T353	1		T349	1