Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1503114172	1499799884	0	0
CheckNGreaterZero_A	4152	4152	0	0
GntImpliesReady_A	1503114172	411445248	0	0
GntImpliesValid_A	1503114172	411445248	0	0
GrantKnown_A	1503114172	1499799884	0	0
IdxKnown_A	1503114172	1499799884	0	0
IndexIsCorrect_A	1503114172	411445248	0	0
NoReadyValidNoGrant_A	1503114172	172936120	0	0
Priority_A	1503114172	435539402	0	0
ReadyAndValidImplyGrant_A	1503114172	411445248	0	0
ReqAndReadyImplyGrant_A	1503114172	411445248	0	0
ReqImpliesValid_A	1503114172	435539402	0	0
ValidKnown_A	1503114172	1499799884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	1499799884	0	0
T1	9964	9612	0	0
T2	753480	753472	0	0
T3	4344	4140	0	0
T4	1678844	1609856	0	0
T5	546900	546864	0	0
T12	13436	10648	0	0
T13	16388	13576	0	0
T17	5208	4876	0	0
T18	13940	13592	0	0
T19	18132	17788	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4152	4152	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	411445248	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	49232	0	0
T7	0	16990	0	0
T8	0	61284	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	332	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	411445248	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	49232	0	0
T7	0	16990	0	0
T8	0	61284	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	332	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	1499799884	0	0
T1	9964	9612	0	0
T2	753480	753472	0	0
T3	4344	4140	0	0
T4	1678844	1609856	0	0
T5	546900	546864	0	0
T12	13436	10648	0	0
T13	16388	13576	0	0
T17	5208	4876	0	0
T18	13940	13592	0	0
T19	18132	17788	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	1499799884	0	0
T1	9964	9612	0	0
T2	753480	753472	0	0
T3	4344	4140	0	0
T4	1678844	1609856	0	0
T5	546900	546864	0	0
T12	13436	10648	0	0
T13	16388	13576	0	0
T17	5208	4876	0	0
T18	13940	13592	0	0
T19	18132	17788	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	411445248	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	49232	0	0
T7	0	16990	0	0
T8	0	61284	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	332	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	172936120	0	0
T1	4982	316	0	0
T2	753480	2110470	0	0
T3	4344	322	0	0
T4	1678844	85168	0	0
T5	546900	11628	0	0
T6	0	1434482	0	0
T7	0	50176	0	0
T8	0	32240	0	0
T12	13436	824	0	0
T13	16388	1600	0	0
T17	5208	256	0	0
T18	13940	256	0	0
T19	18132	256	0	0
T21	0	42	0	0
T32	0	658	0	0
T52	0	1232	0	0
T53	0	569056	0	0
T54	0	228	0	0
T55	2494	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	435539402	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	365638	0	0
T7	0	18930	0	0
T8	0	71544	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	362	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	411445248	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	49232	0	0
T7	0	16990	0	0
T8	0	61284	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	332	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	411445248	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	49232	0	0
T7	0	16990	0	0
T8	0	61284	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	332	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	435539402	0	0
T1	4982	1128	0	0
T2	753480	1702564	0	0
T3	4344	230	0	0
T4	1678844	298458	0	0
T5	546900	1904992	0	0
T6	0	365638	0	0
T7	0	18930	0	0
T8	0	71544	0	0
T12	13436	208	0	0
T13	16388	432	0	0
T17	5208	64	0	0
T18	13940	64	0	0
T19	18132	64	0	0
T21	0	144	0	0
T32	0	362	0	0
T52	0	428004	0	0
T55	2494	0	0	0
T59	0	154944	0	0
T62	0	119112	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503114172	1499799884	0	0
T1	9964	9612	0	0
T2	753480	753472	0	0
T3	4344	4140	0	0
T4	1678844	1609856	0	0
T5	546900	546864	0	0
T12	13436	10648	0	0
T13	16388	13576	0	0
T17	5208	4876	0	0
T18	13940	13592	0	0
T19	18132	17788	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375778543	374949971	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375778543	109732611	0	0
GntImpliesValid_A	375778543	109732611	0	0
GrantKnown_A	375778543	374949971	0	0
IdxKnown_A	375778543	374949971	0	0
IndexIsCorrect_A	375778543	109732611	0	0
NoReadyValidNoGrant_A	375778543	44769392	0	0
Priority_A	375778543	115674210	0	0
ReadyAndValidImplyGrant_A	375778543	109732611	0	0
ReqAndReadyImplyGrant_A	375778543	109732611	0	0
ReqImpliesValid_A	375778543	115674210	0	0
ValidKnown_A	375778543	374949971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732611	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732611	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732611	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	44769392	0	0
T1	2491	158	0	0
T2	188370	530814	0	0
T3	1086	161	0	0
T4	419711	42584	0	0
T5	136725	4125	0	0
T12	3359	412	0	0
T13	4097	800	0	0
T17	1302	128	0	0
T18	3485	128	0	0
T19	4533	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	115674210	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732611	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732611	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	115674210	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375778543	374949971	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375778543	109732534	0	0
GntImpliesValid_A	375778543	109732534	0	0
GrantKnown_A	375778543	374949971	0	0
IdxKnown_A	375778543	374949971	0	0
IndexIsCorrect_A	375778543	109732534	0	0
NoReadyValidNoGrant_A	375778543	44769328	0	0
Priority_A	375778543	115674197	0	0
ReadyAndValidImplyGrant_A	375778543	109732534	0	0
ReqAndReadyImplyGrant_A	375778543	109732534	0	0
ReqImpliesValid_A	375778543	115674197	0	0
ValidKnown_A	375778543	374949971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732534	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732534	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732534	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	44769328	0	0
T1	2491	158	0	0
T2	188370	530814	0	0
T3	1086	161	0	0
T4	419711	42584	0	0
T5	136725	4125	0	0
T12	3359	412	0	0
T13	4097	800	0	0
T17	1302	128	0	0
T18	3485	128	0	0
T19	4533	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	115674197	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732534	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	109732534	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	115674197	0	0
T1	2491	564	0	0
T2	188370	418271	0	0
T3	1086	115	0	0
T4	419711	149229	0	0
T5	136725	721086	0	0
T12	3359	104	0	0
T13	4097	216	0	0
T17	1302	32	0	0
T18	3485	32	0	0
T19	4533	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T6,T7,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T21
1	0	Covered	T2,T5,T6
1	1	Covered	T6,T7,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T2,T5,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375778543	374949971	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375778543	95990020	0	0
GntImpliesValid_A	375778543	95990020	0	0
GrantKnown_A	375778543	374949971	0	0
IdxKnown_A	375778543	374949971	0	0
IndexIsCorrect_A	375778543	95990020	0	0
NoReadyValidNoGrant_A	375778543	41698704	0	0
Priority_A	375778543	102095462	0	0
ReadyAndValidImplyGrant_A	375778543	95990020	0	0
ReqAndReadyImplyGrant_A	375778543	95990020	0	0
ReqImpliesValid_A	375778543	102095462	0	0
ValidKnown_A	375778543	374949971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990020	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990020	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990020	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	41698704	0	0
T2	188370	524421	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	1689	0	0
T6	0	717241	0	0
T7	0	25088	0	0
T8	0	16120	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	21	0	0
T32	0	329	0	0
T52	0	616	0	0
T53	0	284528	0	0
T54	0	114	0	0
T55	1247	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	102095462	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	182819	0	0
T7	0	9465	0	0
T8	0	35772	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	181	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990020	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990020	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	102095462	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	182819	0	0
T7	0	9465	0	0
T8	0	35772	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	181	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T6,T7,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T21
1	0	Covered	T2,T5,T6
1	1	Covered	T6,T7,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T2,T5,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T21
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375778543	374949971	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375778543	95990083	0	0
GntImpliesValid_A	375778543	95990083	0	0
GrantKnown_A	375778543	374949971	0	0
IdxKnown_A	375778543	374949971	0	0
IndexIsCorrect_A	375778543	95990083	0	0
NoReadyValidNoGrant_A	375778543	41698696	0	0
Priority_A	375778543	102095533	0	0
ReadyAndValidImplyGrant_A	375778543	95990083	0	0
ReqAndReadyImplyGrant_A	375778543	95990083	0	0
ReqImpliesValid_A	375778543	102095533	0	0
ValidKnown_A	375778543	374949971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990083	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990083	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990083	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	41698696	0	0
T2	188370	524421	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	1689	0	0
T6	0	717241	0	0
T7	0	25088	0	0
T8	0	16120	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	21	0	0
T32	0	329	0	0
T52	0	616	0	0
T53	0	284528	0	0
T54	0	114	0	0
T55	1247	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	102095533	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	182819	0	0
T7	0	9465	0	0
T8	0	35772	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	181	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990083	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	95990083	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	24616	0	0
T7	0	8495	0	0
T8	0	30642	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	166	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	102095533	0	0
T2	188370	433011	0	0
T3	1086	0	0	0
T4	419711	0	0	0
T5	136725	231410	0	0
T6	0	182819	0	0
T7	0	9465	0	0
T8	0	35772	0	0
T12	3359	0	0	0
T13	4097	0	0	0
T17	1302	0	0	0
T18	3485	0	0	0
T19	4533	0	0	0
T21	0	72	0	0
T32	0	181	0	0
T52	0	214002	0	0
T55	1247	0	0	0
T59	0	77472	0	0
T62	0	59556	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375778543	374949971	0	0
T1	2491	2403	0	0
T2	188370	188368	0	0
T3	1086	1035	0	0
T4	419711	402464	0	0
T5	136725	136716	0	0
T12	3359	2662	0	0
T13	4097	3394	0	0
T17	1302	1219	0	0
T18	3485	3398	0	0
T19	4533	4447	0	0