Line Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Line Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T4,T42,T35 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T4,T42,T35 |
1 | 1 | 0 | Covered | T3,T4,T16 |
1 | 1 | 1 | Unreachable | T3,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T16 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 51 | 49 | 96.08 |
Logical | 51 | 49 | 96.08 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T116 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T116 |
1 | 0 | 1 | Covered | T116 |
1 | 1 | 0 | Covered | T3,T4,T16 |
1 | 1 | 1 | Covered | T3,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T16 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T116 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T52,T54,T182 |
1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T4,T42,T35 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T2,T4,T16 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T23 |
1 | 0 | Covered | T2,T4,T16 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T42 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
Branch Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_arbiter_tree
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8244 |
7368 |
0 |
0 |
T2 |
271644 |
271068 |
0 |
0 |
T3 |
2407362 |
2407266 |
0 |
0 |
T4 |
417426 |
416706 |
0 |
0 |
T5 |
7404 |
7098 |
0 |
0 |
T6 |
1480092 |
1409940 |
0 |
0 |
T7 |
436182 |
435786 |
0 |
0 |
T11 |
5412 |
5022 |
0 |
0 |
T16 |
16488 |
15630 |
0 |
0 |
T17 |
2612844 |
2612424 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6234 |
6234 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
T16 |
6 |
6 |
0 |
0 |
T17 |
6 |
6 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69733306 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
271644 |
580 |
0 |
0 |
T3 |
2407362 |
1582336 |
0 |
0 |
T4 |
417426 |
98898 |
0 |
0 |
T5 |
7404 |
128 |
0 |
0 |
T6 |
1480092 |
30500 |
0 |
0 |
T7 |
436182 |
265 |
0 |
0 |
T11 |
5412 |
194 |
0 |
0 |
T16 |
16488 |
389 |
0 |
0 |
T17 |
2612844 |
586 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
489118 |
956 |
0 |
0 |
T42 |
0 |
43214 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69733306 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
271644 |
580 |
0 |
0 |
T3 |
2407362 |
1582336 |
0 |
0 |
T4 |
417426 |
98898 |
0 |
0 |
T5 |
7404 |
128 |
0 |
0 |
T6 |
1480092 |
30500 |
0 |
0 |
T7 |
436182 |
265 |
0 |
0 |
T11 |
5412 |
194 |
0 |
0 |
T16 |
16488 |
389 |
0 |
0 |
T17 |
2612844 |
586 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
489118 |
956 |
0 |
0 |
T42 |
0 |
43214 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8244 |
7368 |
0 |
0 |
T2 |
271644 |
271068 |
0 |
0 |
T3 |
2407362 |
2407266 |
0 |
0 |
T4 |
417426 |
416706 |
0 |
0 |
T5 |
7404 |
7098 |
0 |
0 |
T6 |
1480092 |
1409940 |
0 |
0 |
T7 |
436182 |
435786 |
0 |
0 |
T11 |
5412 |
5022 |
0 |
0 |
T16 |
16488 |
15630 |
0 |
0 |
T17 |
2612844 |
2612424 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8244 |
7368 |
0 |
0 |
T2 |
271644 |
271068 |
0 |
0 |
T3 |
2407362 |
2407266 |
0 |
0 |
T4 |
417426 |
416706 |
0 |
0 |
T5 |
7404 |
7098 |
0 |
0 |
T6 |
1480092 |
1409940 |
0 |
0 |
T7 |
436182 |
435786 |
0 |
0 |
T11 |
5412 |
5022 |
0 |
0 |
T16 |
16488 |
15630 |
0 |
0 |
T17 |
2612844 |
2612424 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69733306 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
271644 |
580 |
0 |
0 |
T3 |
2407362 |
1582336 |
0 |
0 |
T4 |
417426 |
98898 |
0 |
0 |
T5 |
7404 |
128 |
0 |
0 |
T6 |
1480092 |
30500 |
0 |
0 |
T7 |
436182 |
265 |
0 |
0 |
T11 |
5412 |
194 |
0 |
0 |
T16 |
16488 |
389 |
0 |
0 |
T17 |
2612844 |
586 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
489118 |
956 |
0 |
0 |
T42 |
0 |
43214 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
64783910 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
181096 |
128 |
0 |
0 |
T3 |
1604908 |
1582336 |
0 |
0 |
T4 |
278284 |
78086 |
0 |
0 |
T5 |
4936 |
128 |
0 |
0 |
T6 |
986728 |
29888 |
0 |
0 |
T7 |
290788 |
128 |
0 |
0 |
T11 |
3608 |
184 |
0 |
0 |
T16 |
10992 |
368 |
0 |
0 |
T17 |
1741896 |
128 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1960861807 |
0 |
0 |
T1 |
8244 |
6784 |
0 |
0 |
T2 |
271644 |
183928 |
0 |
0 |
T3 |
2407362 |
2064424 |
0 |
0 |
T4 |
417426 |
122674 |
0 |
0 |
T5 |
7404 |
6810 |
0 |
0 |
T6 |
1480092 |
1251006 |
0 |
0 |
T7 |
436182 |
356641 |
0 |
0 |
T11 |
5412 |
4538 |
0 |
0 |
T16 |
16488 |
13441 |
0 |
0 |
T17 |
2612844 |
2150169 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69733306 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
271644 |
580 |
0 |
0 |
T3 |
2407362 |
1582336 |
0 |
0 |
T4 |
417426 |
98898 |
0 |
0 |
T5 |
7404 |
128 |
0 |
0 |
T6 |
1480092 |
30500 |
0 |
0 |
T7 |
436182 |
265 |
0 |
0 |
T11 |
5412 |
194 |
0 |
0 |
T16 |
16488 |
389 |
0 |
0 |
T17 |
2612844 |
586 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
489118 |
956 |
0 |
0 |
T42 |
0 |
43214 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
69733306 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
271644 |
580 |
0 |
0 |
T3 |
2407362 |
1582336 |
0 |
0 |
T4 |
417426 |
98898 |
0 |
0 |
T5 |
7404 |
128 |
0 |
0 |
T6 |
1480092 |
30500 |
0 |
0 |
T7 |
436182 |
265 |
0 |
0 |
T11 |
5412 |
194 |
0 |
0 |
T16 |
16488 |
389 |
0 |
0 |
T17 |
2612844 |
586 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
489118 |
956 |
0 |
0 |
T42 |
0 |
43214 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
328880475 |
0 |
0 |
T1 |
5496 |
520 |
0 |
0 |
T2 |
271644 |
87100 |
0 |
0 |
T3 |
2407362 |
3164672 |
0 |
0 |
T4 |
417426 |
293976 |
0 |
0 |
T5 |
7404 |
256 |
0 |
0 |
T6 |
1480092 |
152954 |
0 |
0 |
T7 |
436182 |
79101 |
0 |
0 |
T11 |
5412 |
448 |
0 |
0 |
T16 |
16488 |
2119 |
0 |
0 |
T17 |
2612844 |
462195 |
0 |
0 |
T19 |
0 |
352604 |
0 |
0 |
T21 |
0 |
584 |
0 |
0 |
T23 |
0 |
616394 |
0 |
0 |
T34 |
0 |
1860 |
0 |
0 |
T35 |
0 |
354457 |
0 |
0 |
T39 |
489118 |
63947 |
0 |
0 |
T40 |
0 |
803 |
0 |
0 |
T42 |
0 |
879961 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
64783840 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
181096 |
128 |
0 |
0 |
T3 |
1604908 |
1582336 |
0 |
0 |
T4 |
278284 |
78086 |
0 |
0 |
T5 |
4936 |
128 |
0 |
0 |
T6 |
986728 |
29888 |
0 |
0 |
T7 |
290788 |
128 |
0 |
0 |
T11 |
3608 |
184 |
0 |
0 |
T16 |
10992 |
368 |
0 |
0 |
T17 |
1741896 |
128 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
6204 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
8244 |
7368 |
0 |
0 |
T2 |
271644 |
271068 |
0 |
0 |
T3 |
2407362 |
2407266 |
0 |
0 |
T4 |
417426 |
416706 |
0 |
0 |
T5 |
7404 |
7098 |
0 |
0 |
T6 |
1480092 |
1409940 |
0 |
0 |
T7 |
436182 |
435786 |
0 |
0 |
T11 |
5412 |
5022 |
0 |
0 |
T16 |
16488 |
15630 |
0 |
0 |
T17 |
2612844 |
2612424 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1536441312 |
64783952 |
0 |
0 |
T1 |
5496 |
260 |
0 |
0 |
T2 |
181096 |
128 |
0 |
0 |
T3 |
1604908 |
1582336 |
0 |
0 |
T4 |
278284 |
78086 |
0 |
0 |
T5 |
4936 |
128 |
0 |
0 |
T6 |
986728 |
29888 |
0 |
0 |
T7 |
290788 |
128 |
0 |
0 |
T11 |
3608 |
184 |
0 |
0 |
T16 |
10992 |
368 |
0 |
0 |
T17 |
1741896 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T52,T54,T183 |
1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T4,T16 |
1 | 1 | 0 | Covered | T2,T4,T16 |
1 | 1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T16 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T35,T36 |
1 | 0 | Covered | T4,T42,T35 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T2,T4,T16 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T23 |
1 | 0 | Covered | T2,T4,T16 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T16 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T2,T4,T16 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T42 |
1 | 0 | Covered | T2,T4,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T16 |
1 | 0 | Covered | T2,T4,T16 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2497095 |
0 |
0 |
T2 |
45274 |
230 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
12637 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
612 |
0 |
0 |
T7 |
72697 |
74 |
0 |
0 |
T11 |
902 |
10 |
0 |
0 |
T16 |
2748 |
21 |
0 |
0 |
T17 |
435474 |
261 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T39 |
244559 |
956 |
0 |
0 |
T42 |
0 |
22004 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2497095 |
0 |
0 |
T2 |
45274 |
230 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
12637 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
612 |
0 |
0 |
T7 |
72697 |
74 |
0 |
0 |
T11 |
902 |
10 |
0 |
0 |
T16 |
2748 |
21 |
0 |
0 |
T17 |
435474 |
261 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T39 |
244559 |
956 |
0 |
0 |
T42 |
0 |
22004 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2497095 |
0 |
0 |
T2 |
45274 |
230 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
12637 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
612 |
0 |
0 |
T7 |
72697 |
74 |
0 |
0 |
T11 |
902 |
10 |
0 |
0 |
T16 |
2748 |
21 |
0 |
0 |
T17 |
435474 |
261 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T39 |
244559 |
956 |
0 |
0 |
T42 |
0 |
22004 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
278964635 |
0 |
0 |
T1 |
1374 |
1164 |
0 |
0 |
T2 |
45274 |
804 |
0 |
0 |
T3 |
401227 |
387944 |
0 |
0 |
T4 |
69571 |
499 |
0 |
0 |
T5 |
1234 |
1151 |
0 |
0 |
T6 |
246682 |
135832 |
0 |
0 |
T7 |
72697 |
377 |
0 |
0 |
T11 |
902 |
721 |
0 |
0 |
T16 |
2748 |
1154 |
0 |
0 |
T17 |
435474 |
133756 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2497095 |
0 |
0 |
T2 |
45274 |
230 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
12637 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
612 |
0 |
0 |
T7 |
72697 |
74 |
0 |
0 |
T11 |
902 |
10 |
0 |
0 |
T16 |
2748 |
21 |
0 |
0 |
T17 |
435474 |
261 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T39 |
244559 |
956 |
0 |
0 |
T42 |
0 |
22004 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2497095 |
0 |
0 |
T2 |
45274 |
230 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
12637 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
612 |
0 |
0 |
T7 |
72697 |
74 |
0 |
0 |
T11 |
902 |
10 |
0 |
0 |
T16 |
2748 |
21 |
0 |
0 |
T17 |
435474 |
261 |
0 |
0 |
T34 |
0 |
70 |
0 |
0 |
T39 |
244559 |
956 |
0 |
0 |
T42 |
0 |
22004 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
99066765 |
0 |
0 |
T2 |
45274 |
44338 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
68900 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
93178 |
0 |
0 |
T7 |
72697 |
72218 |
0 |
0 |
T11 |
902 |
80 |
0 |
0 |
T16 |
2748 |
1383 |
0 |
0 |
T17 |
435474 |
301608 |
0 |
0 |
T34 |
0 |
1860 |
0 |
0 |
T39 |
244559 |
63947 |
0 |
0 |
T42 |
0 |
439974 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
1034 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T17,T42,T35 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T17,T42 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T17 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T52,T54,T182 |
1 | 1 | Covered | T2,T4,T7 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T7 |
1 | 1 | 0 | Covered | T2,T4,T7 |
1 | 1 | 1 | Covered | T2,T4,T7 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T7 |
1 | 1 | 0 | Covered | T2,T4,T7 |
1 | 1 | 1 | Covered | T2,T4,T7 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T4,T7 |
1 | 1 | 0 | Covered | T2,T4,T7 |
1 | 1 | 1 | Covered | T2,T4,T7 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T2,T4,T7 |
1 | 1 | 0 | Covered | T2,T4,T7 |
1 | 1 | 1 | Covered | T2,T4,T7 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T7 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T4,T42,T35 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T2,T4,T7 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T2,T4,T7 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T7 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T7 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T7 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T7 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T7 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T4,T7 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T4,T7 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T2,T4,T7 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T2,T4,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T2,T4,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2452259 |
0 |
0 |
T2 |
45274 |
222 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
8175 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
63 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
197 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T42 |
0 |
21210 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2452259 |
0 |
0 |
T2 |
45274 |
222 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
8175 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
63 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
197 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T42 |
0 |
21210 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2452259 |
0 |
0 |
T2 |
45274 |
222 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
8175 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
63 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
197 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T42 |
0 |
21210 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
278407405 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
2668 |
0 |
0 |
T3 |
401227 |
388104 |
0 |
0 |
T4 |
69571 |
545 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
65996 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2603 |
0 |
0 |
T17 |
435474 |
275053 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2452259 |
0 |
0 |
T2 |
45274 |
222 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
8175 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
63 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
197 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T42 |
0 |
21210 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
2452259 |
0 |
0 |
T2 |
45274 |
222 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
8175 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
63 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
197 |
0 |
0 |
T19 |
0 |
134396 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
0 |
14735 |
0 |
0 |
T23 |
0 |
8451 |
0 |
0 |
T35 |
0 |
22477 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T42 |
0 |
21210 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
100245775 |
0 |
0 |
T2 |
45274 |
42506 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
68902 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
6627 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
160331 |
0 |
0 |
T19 |
0 |
352604 |
0 |
0 |
T21 |
0 |
584 |
0 |
0 |
T23 |
0 |
616394 |
0 |
0 |
T35 |
0 |
354457 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T40 |
0 |
803 |
0 |
0 |
T42 |
0 |
439987 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
1034 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 51 | 45 | 88.24 |
Logical | 51 | 45 | 88.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T116 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T3,T4,T16 |
1 | 1 | 1 | Covered | T3,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T16 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110236 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
351878999 |
0 |
0 |
T1 |
1374 |
1098 |
0 |
0 |
T2 |
45274 |
45114 |
0 |
0 |
T3 |
401227 |
322094 |
0 |
0 |
T4 |
69571 |
30408 |
0 |
0 |
T5 |
1234 |
1119 |
0 |
0 |
T6 |
246682 |
220046 |
0 |
0 |
T7 |
72697 |
72567 |
0 |
0 |
T11 |
902 |
745 |
0 |
0 |
T16 |
2748 |
2421 |
0 |
0 |
T17 |
435474 |
435340 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
31385393 |
0 |
0 |
T1 |
1374 |
130 |
0 |
0 |
T2 |
45274 |
64 |
0 |
0 |
T3 |
401227 |
791168 |
0 |
0 |
T4 |
69571 |
39043 |
0 |
0 |
T5 |
1234 |
64 |
0 |
0 |
T6 |
246682 |
14944 |
0 |
0 |
T7 |
72697 |
64 |
0 |
0 |
T11 |
902 |
92 |
0 |
0 |
T16 |
2748 |
184 |
0 |
0 |
T17 |
435474 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384068257 |
15692659 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
1034 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 51 | 49 | 96.08 |
Logical | 51 | 49 | 96.08 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T116 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T116 |
1 | 0 | 1 | Covered | T116 |
1 | 1 | 0 | Covered | T3,T4,T16 |
1 | 1 | 1 | Covered | T3,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T16 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T116 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692738 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692738 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692738 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110236 |
15692694 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
351878954 |
0 |
0 |
T1 |
1374 |
1098 |
0 |
0 |
T2 |
45274 |
45114 |
0 |
0 |
T3 |
401227 |
322094 |
0 |
0 |
T4 |
69571 |
30408 |
0 |
0 |
T5 |
1234 |
1119 |
0 |
0 |
T6 |
246682 |
220046 |
0 |
0 |
T7 |
72697 |
72567 |
0 |
0 |
T11 |
902 |
745 |
0 |
0 |
T16 |
2748 |
2421 |
0 |
0 |
T17 |
435474 |
435340 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692738 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692738 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
31385482 |
0 |
0 |
T1 |
1374 |
130 |
0 |
0 |
T2 |
45274 |
64 |
0 |
0 |
T3 |
401227 |
791168 |
0 |
0 |
T4 |
69571 |
39043 |
0 |
0 |
T5 |
1234 |
64 |
0 |
0 |
T6 |
246682 |
14944 |
0 |
0 |
T7 |
72697 |
64 |
0 |
0 |
T11 |
902 |
92 |
0 |
0 |
T16 |
2748 |
184 |
0 |
0 |
T17 |
435474 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384068257 |
15692659 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
1034 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
15692738 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19521 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
|
unreachable |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T4,T42,T35 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T4,T42,T35 |
1 | 1 | 0 | Covered | T3,T4,T16 |
1 | 1 | 1 | Unreachable | T3,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T16 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110329 |
16699261 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
349865907 |
0 |
0 |
T1 |
1374 |
1098 |
0 |
0 |
T2 |
45274 |
45114 |
0 |
0 |
T3 |
401227 |
322094 |
0 |
0 |
T4 |
69571 |
30407 |
0 |
0 |
T5 |
1234 |
1119 |
0 |
0 |
T6 |
246682 |
220046 |
0 |
0 |
T7 |
72697 |
72567 |
0 |
0 |
T11 |
902 |
745 |
0 |
0 |
T16 |
2748 |
2421 |
0 |
0 |
T17 |
435474 |
435340 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
33398530 |
0 |
0 |
T1 |
1374 |
130 |
0 |
0 |
T2 |
45274 |
64 |
0 |
0 |
T3 |
401227 |
791168 |
0 |
0 |
T4 |
69571 |
39044 |
0 |
0 |
T5 |
1234 |
64 |
0 |
0 |
T6 |
246682 |
14944 |
0 |
0 |
T7 |
72697 |
64 |
0 |
0 |
T11 |
902 |
92 |
0 |
0 |
T16 |
2748 |
184 |
0 |
0 |
T17 |
435474 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110329 |
16699261 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
1034 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
|
unreachable |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T4,T42,T35 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T4,T42,T35 |
1 | 1 | 0 | Covered | T3,T4,T16 |
1 | 1 | 1 | Unreachable | T3,T4,T16 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T16 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T3,T4,T16 |
1 | 1 | Covered | T3,T4,T16 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T42,T35 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T16 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T16 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110329 |
16699261 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
349865907 |
0 |
0 |
T1 |
1374 |
1098 |
0 |
0 |
T2 |
45274 |
45114 |
0 |
0 |
T3 |
401227 |
322094 |
0 |
0 |
T4 |
69571 |
30407 |
0 |
0 |
T5 |
1234 |
1119 |
0 |
0 |
T6 |
246682 |
220046 |
0 |
0 |
T7 |
72697 |
72567 |
0 |
0 |
T11 |
902 |
745 |
0 |
0 |
T16 |
2748 |
2421 |
0 |
0 |
T17 |
435474 |
435340 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
33398530 |
0 |
0 |
T1 |
1374 |
130 |
0 |
0 |
T2 |
45274 |
64 |
0 |
0 |
T3 |
401227 |
791168 |
0 |
0 |
T4 |
69571 |
39044 |
0 |
0 |
T5 |
1234 |
64 |
0 |
0 |
T6 |
246682 |
14944 |
0 |
0 |
T7 |
72697 |
64 |
0 |
0 |
T11 |
902 |
92 |
0 |
0 |
T16 |
2748 |
184 |
0 |
0 |
T17 |
435474 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110329 |
16699261 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
0 |
0 |
1034 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
16699260 |
0 |
0 |
T1 |
1374 |
65 |
0 |
0 |
T2 |
45274 |
32 |
0 |
0 |
T3 |
401227 |
395584 |
0 |
0 |
T4 |
69571 |
19522 |
0 |
0 |
T5 |
1234 |
32 |
0 |
0 |
T6 |
246682 |
7472 |
0 |
0 |
T7 |
72697 |
32 |
0 |
0 |
T11 |
902 |
46 |
0 |
0 |
T16 |
2748 |
92 |
0 |
0 |
T17 |
435474 |
32 |
0 |
0 |