Line Coverage for Module :
flash_phy_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 133 | 133 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 257 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
ALWAYS | 360 | 12 | 12 | 100.00 |
CONT_ASSIGN | 377 | 1 | 1 | 100.00 |
CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 505 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
ALWAYS | 600 | 6 | 6 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
CONT_ASSIGN | 624 | 1 | 1 | 100.00 |
CONT_ASSIGN | 628 | 1 | 1 | 100.00 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 659 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
ALWAYS | 670 | 8 | 8 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
CONT_ASSIGN | 736 | 1 | 1 | 100.00 |
CONT_ASSIGN | 738 | 1 | 1 | 100.00 |
CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
CONT_ASSIGN | 762 | 1 | 1 | 100.00 |
CONT_ASSIGN | 775 | 1 | 1 | 100.00 |
CONT_ASSIGN | 787 | 1 | 1 | 100.00 |
CONT_ASSIGN | 790 | 1 | 1 | 100.00 |
CONT_ASSIGN | 794 | 1 | 1 | 100.00 |
CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
137 |
1 |
1 |
140 |
4 |
4 |
141 |
4 |
4 |
146 |
4 |
4 |
152 |
1 |
1 |
154 |
3 |
3 |
186 |
1 |
1 |
193 |
4 |
4 |
194 |
4 |
4 |
196 |
4 |
4 |
212 |
4 |
4 |
218 |
4 |
4 |
222 |
4 |
4 |
229 |
1 |
1 |
232 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
260 |
1 |
1 |
|
|
|
MISSING_ELSE |
291 |
1 |
1 |
292 |
1 |
1 |
302 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
326 |
1 |
1 |
331 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
371 |
1 |
1 |
372 |
1 |
1 |
|
|
|
MISSING_ELSE |
377 |
1 |
1 |
382 |
1 |
1 |
393 |
1 |
1 |
399 |
1 |
1 |
407 |
1 |
1 |
428 |
1 |
1 |
432 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
451 |
1 |
1 |
456 |
1 |
1 |
459 |
1 |
1 |
491 |
1 |
1 |
494 |
1 |
1 |
497 |
1 |
1 |
501 |
1 |
1 |
503 |
1 |
1 |
504 |
1 |
1 |
505 |
1 |
1 |
513 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
600 |
1 |
1 |
601 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
|
|
|
MISSING_ELSE |
610 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
624 |
1 |
1 |
628 |
1 |
1 |
636 |
1 |
1 |
654 |
1 |
1 |
659 |
1 |
1 |
664 |
4 |
4 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
|
|
|
MISSING_ELSE |
683 |
1 |
1 |
704 |
1 |
1 |
724 |
1 |
1 |
736 |
1 |
1 |
738 |
1 |
1 |
744 |
1 |
1 |
745 |
1 |
1 |
747 |
1 |
1 |
751 |
1 |
1 |
762 |
1 |
1 |
775 |
1 |
1 |
787 |
1 |
1 |
790 |
1 |
1 |
794 |
1 |
1 |
797 |
1 |
1 |
800 |
1 |
1 |
Cond Coverage for Module :
flash_phy_rd
| Total | Covered | Percent |
Conditions | 458 | 421 | 91.92 |
Logical | 458 | 421 | 91.92 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Module :
flash_phy_rd
| Line No. | Total | Covered | Percent |
Branches |
|
43 |
43 |
100.00 |
TERNARY |
186 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
302 |
2 |
2 |
100.00 |
TERNARY |
451 |
2 |
2 |
100.00 |
TERNARY |
513 |
3 |
3 |
100.00 |
TERNARY |
624 |
3 |
3 |
100.00 |
TERNARY |
628 |
3 |
3 |
100.00 |
TERNARY |
654 |
3 |
3 |
100.00 |
TERNARY |
683 |
2 |
2 |
100.00 |
TERNARY |
736 |
2 |
2 |
100.00 |
TERNARY |
747 |
2 |
2 |
100.00 |
TERNARY |
775 |
2 |
2 |
100.00 |
TERNARY |
167 |
2 |
2 |
100.00 |
IF |
257 |
3 |
3 |
100.00 |
IF |
360 |
4 |
4 |
100.00 |
IF |
600 |
4 |
4 |
100.00 |
IF |
674 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 186 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 232 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 302 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 451 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T34,T21 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 513 (hint_descram) ?
-2-: 513 (hint_dropmsk) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T42,T178,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (forward) ?
-2-: 624 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T4,T7 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 628 (forward) ?
-2-: 628 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T4,T7 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 654 (forward) ?
-2-: 654 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T4,T7 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 683 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 736 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T95,T21 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 747 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 257 if ((!rst_ni))
-2-: 259 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 360 if ((!rst_ni))
-2-: 364 if (rd_start)
-3-: 371 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 600 if ((!rst_ni))
-2-: 602 if (calc_req_start)
-3-: 604 if (calc_req_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 674 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
1607048 |
0 |
0 |
T2 |
90548 |
392 |
0 |
0 |
T3 |
802454 |
0 |
0 |
0 |
T4 |
139142 |
2901 |
0 |
0 |
T5 |
2468 |
0 |
0 |
0 |
T6 |
493364 |
1840 |
0 |
0 |
T7 |
145394 |
116 |
0 |
0 |
T11 |
1804 |
13 |
0 |
0 |
T16 |
5496 |
22 |
0 |
0 |
T17 |
870948 |
425 |
0 |
0 |
T19 |
0 |
134400 |
0 |
0 |
T21 |
0 |
4 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T34 |
0 |
72 |
0 |
0 |
T35 |
0 |
975 |
0 |
0 |
T39 |
489118 |
2528 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T42 |
0 |
2074 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
3812217 |
0 |
0 |
T2 |
90548 |
460 |
0 |
0 |
T3 |
802454 |
0 |
0 |
0 |
T4 |
139142 |
1346 |
0 |
0 |
T5 |
2468 |
0 |
0 |
0 |
T6 |
493364 |
0 |
0 |
0 |
T7 |
145394 |
149 |
0 |
0 |
T11 |
1804 |
0 |
0 |
0 |
T16 |
5496 |
0 |
0 |
0 |
T17 |
870948 |
486 |
0 |
0 |
T19 |
0 |
134400 |
0 |
0 |
T21 |
0 |
12 |
0 |
0 |
T22 |
0 |
29814 |
0 |
0 |
T23 |
0 |
18173 |
0 |
0 |
T35 |
0 |
5325 |
0 |
0 |
T39 |
489118 |
0 |
0 |
0 |
T40 |
0 |
14 |
0 |
0 |
T42 |
0 |
42795 |
0 |
0 |
T178 |
0 |
10126 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
102902368 |
0 |
0 |
T1 |
1374 |
256 |
0 |
0 |
T2 |
90548 |
1440 |
0 |
0 |
T3 |
802454 |
1054976 |
0 |
0 |
T4 |
139142 |
74128 |
0 |
0 |
T5 |
2468 |
128 |
0 |
0 |
T6 |
493364 |
28208 |
0 |
0 |
T7 |
145394 |
695 |
0 |
0 |
T11 |
1804 |
197 |
0 |
0 |
T16 |
5496 |
386 |
0 |
0 |
T17 |
870948 |
1525 |
0 |
0 |
T19 |
0 |
403200 |
0 |
0 |
T23 |
0 |
431215 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
T42 |
0 |
86624 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2078 |
2078 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T11 |
2 |
2 |
0 |
0 |
T16 |
2 |
2 |
0 |
0 |
T17 |
2 |
2 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
768220656 |
766528874 |
0 |
0 |
T1 |
2748 |
2456 |
0 |
0 |
T2 |
90548 |
90356 |
0 |
0 |
T3 |
802454 |
802422 |
0 |
0 |
T4 |
139142 |
138902 |
0 |
0 |
T5 |
2468 |
2366 |
0 |
0 |
T6 |
493364 |
469980 |
0 |
0 |
T7 |
145394 |
145262 |
0 |
0 |
T11 |
1804 |
1674 |
0 |
0 |
T16 |
5496 |
5210 |
0 |
0 |
T17 |
870948 |
870808 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 133 | 133 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 257 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
ALWAYS | 360 | 12 | 12 | 100.00 |
CONT_ASSIGN | 377 | 1 | 1 | 100.00 |
CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 505 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
ALWAYS | 600 | 6 | 6 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
CONT_ASSIGN | 624 | 1 | 1 | 100.00 |
CONT_ASSIGN | 628 | 1 | 1 | 100.00 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 659 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
ALWAYS | 670 | 8 | 8 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
CONT_ASSIGN | 736 | 1 | 1 | 100.00 |
CONT_ASSIGN | 738 | 1 | 1 | 100.00 |
CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
CONT_ASSIGN | 762 | 1 | 1 | 100.00 |
CONT_ASSIGN | 775 | 1 | 1 | 100.00 |
CONT_ASSIGN | 787 | 1 | 1 | 100.00 |
CONT_ASSIGN | 790 | 1 | 1 | 100.00 |
CONT_ASSIGN | 794 | 1 | 1 | 100.00 |
CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
137 |
1 |
1 |
140 |
4 |
4 |
141 |
4 |
4 |
146 |
4 |
4 |
152 |
1 |
1 |
154 |
3 |
3 |
186 |
1 |
1 |
193 |
4 |
4 |
194 |
4 |
4 |
196 |
4 |
4 |
212 |
4 |
4 |
218 |
4 |
4 |
222 |
4 |
4 |
229 |
1 |
1 |
232 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
260 |
1 |
1 |
|
|
|
MISSING_ELSE |
291 |
1 |
1 |
292 |
1 |
1 |
302 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
326 |
1 |
1 |
331 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
371 |
1 |
1 |
372 |
1 |
1 |
|
|
|
MISSING_ELSE |
377 |
1 |
1 |
382 |
1 |
1 |
393 |
1 |
1 |
399 |
1 |
1 |
407 |
1 |
1 |
428 |
1 |
1 |
432 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
451 |
1 |
1 |
456 |
1 |
1 |
459 |
1 |
1 |
491 |
1 |
1 |
494 |
1 |
1 |
497 |
1 |
1 |
501 |
1 |
1 |
503 |
1 |
1 |
504 |
1 |
1 |
505 |
1 |
1 |
513 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
600 |
1 |
1 |
601 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
|
|
|
MISSING_ELSE |
610 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
624 |
1 |
1 |
628 |
1 |
1 |
636 |
1 |
1 |
654 |
1 |
1 |
659 |
1 |
1 |
664 |
4 |
4 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
|
|
|
MISSING_ELSE |
683 |
1 |
1 |
704 |
1 |
1 |
724 |
1 |
1 |
736 |
1 |
1 |
738 |
1 |
1 |
744 |
1 |
1 |
745 |
1 |
1 |
747 |
1 |
1 |
751 |
1 |
1 |
762 |
1 |
1 |
775 |
1 |
1 |
787 |
1 |
1 |
790 |
1 |
1 |
794 |
1 |
1 |
797 |
1 |
1 |
800 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Total | Covered | Percent |
Conditions | 458 | 417 | 91.05 |
Logical | 458 | 417 | 91.05 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Line No. | Total | Covered | Percent |
Branches |
|
43 |
43 |
100.00 |
TERNARY |
186 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
302 |
2 |
2 |
100.00 |
TERNARY |
451 |
2 |
2 |
100.00 |
TERNARY |
513 |
3 |
3 |
100.00 |
TERNARY |
624 |
3 |
3 |
100.00 |
TERNARY |
628 |
3 |
3 |
100.00 |
TERNARY |
654 |
3 |
3 |
100.00 |
TERNARY |
683 |
2 |
2 |
100.00 |
TERNARY |
736 |
2 |
2 |
100.00 |
TERNARY |
747 |
2 |
2 |
100.00 |
TERNARY |
775 |
2 |
2 |
100.00 |
TERNARY |
167 |
2 |
2 |
100.00 |
IF |
257 |
3 |
3 |
100.00 |
IF |
360 |
4 |
4 |
100.00 |
IF |
600 |
4 |
4 |
100.00 |
IF |
674 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 186 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 232 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 302 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 451 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T34,T21,T35 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 513 (hint_descram) ?
-2-: 513 (hint_dropmsk) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T42,T178,T78 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (forward) ?
-2-: 624 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T4,T7 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 628 (forward) ?
-2-: 628 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T4,T7 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 654 (forward) ?
-2-: 654 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T4,T7 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 683 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 736 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T95,T21,T52 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 747 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 257 if ((!rst_ni))
-2-: 259 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 360 if ((!rst_ni))
-2-: 364 if (rd_start)
-3-: 371 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 600 if ((!rst_ni))
-2-: 602 if (calc_req_start)
-3-: 604 if (calc_req_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 674 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
834753 |
0 |
0 |
T2 |
45274 |
201 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
2897 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
1840 |
0 |
0 |
T7 |
72697 |
63 |
0 |
0 |
T11 |
902 |
13 |
0 |
0 |
T16 |
2748 |
22 |
0 |
0 |
T17 |
435474 |
233 |
0 |
0 |
T34 |
0 |
72 |
0 |
0 |
T39 |
244559 |
2528 |
0 |
0 |
T42 |
0 |
1288 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
1985517 |
0 |
0 |
T2 |
45274 |
234 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
1346 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
78 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
269 |
0 |
0 |
T21 |
0 |
12 |
0 |
0 |
T22 |
0 |
15075 |
0 |
0 |
T23 |
0 |
9718 |
0 |
0 |
T35 |
0 |
216 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
T42 |
0 |
21699 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
52975304 |
0 |
0 |
T1 |
1374 |
256 |
0 |
0 |
T2 |
45274 |
797 |
0 |
0 |
T3 |
401227 |
530688 |
0 |
0 |
T4 |
69571 |
44745 |
0 |
0 |
T5 |
1234 |
128 |
0 |
0 |
T6 |
246682 |
28208 |
0 |
0 |
T7 |
72697 |
447 |
0 |
0 |
T11 |
902 |
197 |
0 |
0 |
T16 |
2748 |
378 |
0 |
0 |
T17 |
435474 |
899 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 133 | 133 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 257 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
ALWAYS | 360 | 12 | 12 | 100.00 |
CONT_ASSIGN | 377 | 1 | 1 | 100.00 |
CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 505 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
ALWAYS | 600 | 6 | 6 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
CONT_ASSIGN | 624 | 1 | 1 | 100.00 |
CONT_ASSIGN | 628 | 1 | 1 | 100.00 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 659 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
ALWAYS | 670 | 8 | 8 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
CONT_ASSIGN | 736 | 1 | 1 | 100.00 |
CONT_ASSIGN | 738 | 1 | 1 | 100.00 |
CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
CONT_ASSIGN | 762 | 1 | 1 | 100.00 |
CONT_ASSIGN | 775 | 1 | 1 | 100.00 |
CONT_ASSIGN | 787 | 1 | 1 | 100.00 |
CONT_ASSIGN | 790 | 1 | 1 | 100.00 |
CONT_ASSIGN | 794 | 1 | 1 | 100.00 |
CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
137 |
1 |
1 |
140 |
4 |
4 |
141 |
4 |
4 |
146 |
4 |
4 |
152 |
1 |
1 |
154 |
3 |
3 |
186 |
1 |
1 |
193 |
4 |
4 |
194 |
4 |
4 |
196 |
4 |
4 |
212 |
4 |
4 |
218 |
4 |
4 |
222 |
4 |
4 |
229 |
1 |
1 |
232 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
260 |
1 |
1 |
|
|
|
MISSING_ELSE |
291 |
1 |
1 |
292 |
1 |
1 |
302 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
326 |
1 |
1 |
331 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
371 |
1 |
1 |
372 |
1 |
1 |
|
|
|
MISSING_ELSE |
377 |
1 |
1 |
382 |
1 |
1 |
393 |
1 |
1 |
399 |
1 |
1 |
407 |
1 |
1 |
428 |
1 |
1 |
432 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
451 |
1 |
1 |
456 |
1 |
1 |
459 |
1 |
1 |
491 |
1 |
1 |
494 |
1 |
1 |
497 |
1 |
1 |
501 |
1 |
1 |
503 |
1 |
1 |
504 |
1 |
1 |
505 |
1 |
1 |
513 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
600 |
1 |
1 |
601 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
|
|
|
MISSING_ELSE |
610 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
624 |
1 |
1 |
628 |
1 |
1 |
636 |
1 |
1 |
654 |
1 |
1 |
659 |
1 |
1 |
664 |
4 |
4 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
|
|
|
MISSING_ELSE |
683 |
1 |
1 |
704 |
1 |
1 |
724 |
1 |
1 |
736 |
1 |
1 |
738 |
1 |
1 |
744 |
1 |
1 |
745 |
1 |
1 |
747 |
1 |
1 |
751 |
1 |
1 |
762 |
1 |
1 |
775 |
1 |
1 |
787 |
1 |
1 |
790 |
1 |
1 |
794 |
1 |
1 |
797 |
1 |
1 |
800 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Total | Covered | Percent |
Conditions | 458 | 417 | 91.05 |
Logical | 458 | 417 | 91.05 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Line No. | Total | Covered | Percent |
Branches |
|
43 |
43 |
100.00 |
TERNARY |
186 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
302 |
2 |
2 |
100.00 |
TERNARY |
451 |
2 |
2 |
100.00 |
TERNARY |
513 |
3 |
3 |
100.00 |
TERNARY |
624 |
3 |
3 |
100.00 |
TERNARY |
628 |
3 |
3 |
100.00 |
TERNARY |
654 |
3 |
3 |
100.00 |
TERNARY |
683 |
2 |
2 |
100.00 |
TERNARY |
736 |
2 |
2 |
100.00 |
TERNARY |
747 |
2 |
2 |
100.00 |
TERNARY |
775 |
2 |
2 |
100.00 |
TERNARY |
167 |
2 |
2 |
100.00 |
IF |
257 |
3 |
3 |
100.00 |
IF |
360 |
4 |
4 |
100.00 |
IF |
600 |
4 |
4 |
100.00 |
IF |
674 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 186 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 232 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T16 |
LineNo. Expression
-1-: 302 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 451 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T35,T36 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 513 (hint_descram) ?
-2-: 513 (hint_dropmsk) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T3,T4,T16 |
0 |
1 |
Covered |
T42,T59,T137 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (forward) ?
-2-: 624 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T7,T17 |
0 |
1 |
Covered |
T3,T4,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 628 (forward) ?
-2-: 628 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T7,T17 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T7,T17 |
LineNo. Expression
-1-: 654 (forward) ?
-2-: 654 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T7,T17 |
0 |
1 |
Covered |
T3,T4,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 683 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 736 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T52,T53 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 747 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T4,T7 |
LineNo. Expression
-1-: 257 if ((!rst_ni))
-2-: 259 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 360 if ((!rst_ni))
-2-: 364 if (rd_start)
-3-: 371 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 600 if ((!rst_ni))
-2-: 602 if (calc_req_start)
-3-: 604 if (calc_req_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T4,T16 |
0 |
0 |
1 |
Covered |
T3,T4,T16 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 674 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
772295 |
0 |
0 |
T2 |
45274 |
191 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
4 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
53 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
192 |
0 |
0 |
T19 |
0 |
134400 |
0 |
0 |
T21 |
0 |
4 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T35 |
0 |
975 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T42 |
0 |
786 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
1826700 |
0 |
0 |
T2 |
45274 |
226 |
0 |
0 |
T3 |
401227 |
0 |
0 |
0 |
T4 |
69571 |
0 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
71 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
0 |
0 |
0 |
T17 |
435474 |
217 |
0 |
0 |
T19 |
0 |
134400 |
0 |
0 |
T22 |
0 |
14739 |
0 |
0 |
T23 |
0 |
8455 |
0 |
0 |
T35 |
0 |
5109 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T42 |
0 |
21096 |
0 |
0 |
T178 |
0 |
10126 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
49927064 |
0 |
0 |
T2 |
45274 |
643 |
0 |
0 |
T3 |
401227 |
524288 |
0 |
0 |
T4 |
69571 |
29383 |
0 |
0 |
T5 |
1234 |
0 |
0 |
0 |
T6 |
246682 |
0 |
0 |
0 |
T7 |
72697 |
248 |
0 |
0 |
T11 |
902 |
0 |
0 |
0 |
T16 |
2748 |
8 |
0 |
0 |
T17 |
435474 |
626 |
0 |
0 |
T19 |
0 |
403200 |
0 |
0 |
T23 |
0 |
431215 |
0 |
0 |
T39 |
244559 |
0 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
T42 |
0 |
86624 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1039 |
1039 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384110328 |
383264437 |
0 |
0 |
T1 |
1374 |
1228 |
0 |
0 |
T2 |
45274 |
45178 |
0 |
0 |
T3 |
401227 |
401211 |
0 |
0 |
T4 |
69571 |
69451 |
0 |
0 |
T5 |
1234 |
1183 |
0 |
0 |
T6 |
246682 |
234990 |
0 |
0 |
T7 |
72697 |
72631 |
0 |
0 |
T11 |
902 |
837 |
0 |
0 |
T16 |
2748 |
2605 |
0 |
0 |
T17 |
435474 |
435404 |
0 |
0 |