Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	29438871	1		T1	32187		T2	503		T3	30235
full_word	8061762	1		T1	39341		T2	2		T3	16607

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37500313	1		T1	71528		T2	505		T3	46842
auto[TlIntgErrCmd]	117	1		T98	5		T100	8		T236	2
auto[TlIntgErrData]	102	1		T98	7		T100	5		T236	6
auto[TlIntgErrBoth]	101	1		T98	8		T100	7		T236	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32872983	1		T1	54524		T2	497		T3	34332
auto[1]	4627650	1		T1	17004		T2	8		T3	12510

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28724406	1		T1	21446		T2	497		T3	28647
auto[TlIntgErrNone]	partial	auto[1]	714178	1		T1	10741		T2	6		T3	1588
auto[TlIntgErrNone]	full_word	auto[0]	4148438	1		T1	33078		T3	5685		T10	2
auto[TlIntgErrNone]	full_word	auto[1]	3913291	1		T1	6263		T2	2		T3	10922
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T98	2		T100	5		T236	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T98	3		T100	3		T236	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T255	2		T259	1		T339	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T259	1		T264	1		T263	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T98	1		T100	2		T236	4
auto[TlIntgErrData]	partial	auto[1]	47	1		T98	6		T100	3		T236	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T255	2		T340	1		T264	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T236	1		T341	1		T264	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T98	3		T236	1		T341	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T98	5		T100	6		T255	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T100	1		T263	1		T338	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T236	1		T259	3		T338	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18013	1		T96	693		T97	847		T98	17
full_word	4249605	1		T1	16656		T4	6		T5	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4267319	1		T1	16656		T4	6		T5	5
auto[TlIntgErrCmd]	94	1		T98	6		T100	3		T236	3
auto[TlIntgErrData]	106	1		T98	6		T100	8		T236	3
auto[TlIntgErrBoth]	99	1		T98	5		T100	7		T236	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4244289	1		T1	16656		T4	6		T5	5
auto[1]	23329	1		T96	857		T97	1164		T98	10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	956	1		T96	62		T97	105		T99	3
auto[TlIntgErrNone]	partial	auto[1]	16786	1		T96	631		T97	742		T99	65
auto[TlIntgErrNone]	full_word	auto[0]	4243215	1		T1	16656		T4	6		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	6362	1		T96	226		T97	422		T99	55
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T98	2		T100	1		T236	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T98	4		T100	2		T236	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T264	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T259	1		T342	1		T343	2
auto[TlIntgErrData]	partial	auto[0]	42	1		T98	1		T100	1		T255	4
auto[TlIntgErrData]	partial	auto[1]	52	1		T98	5		T100	7		T236	1
auto[TlIntgErrData]	full_word	auto[0]	8	1		T255	1		T267	1		T259	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T236	2		T342	1		T344	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T98	4		T100	1		T236	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T98	1		T100	5		T236	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T264	2		T345	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T100	1		T267	1		T259	1