Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.74 100.00 85.85 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 97.07 93.19 96.90 100.00 99.29 97.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.65 100.00 96.92 95.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.06 97.64 93.48 100.00 99.37 94.83
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.06 100.00 95.28 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.96 97.07 94.01 100.00 100.00 99.65 97.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 99.49 100.00 96.92 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.10 97.64 93.64 100.00 99.37 94.83
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS22966100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions10610296.23
Logical10610296.23
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT4,T8,T221

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T8,T221

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T6
110Not Covered
111CoveredT1,T4,T5

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T6
101CoveredT1,T4,T5
110CoveredT55
111CoveredT1,T4,T5

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT220,T209
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT64,T65,T66
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T10
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT3,T10,T4
10CoveredT2,T3,T10
11CoveredT3,T10,T4

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT55
10CoveredT120,T222,T223

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT120,T222,T223

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT55

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T10,T4
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT3,T10,T4
10CoveredT1,T2,T3
11CoveredT3,T10,T4

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T2,T3
11CoveredT3,T10,T25

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT43,T44,T62
10CoveredT2,T3,T10

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT4
11CoveredT4

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T10
11CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T5
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T45
10CoveredT14,T15,T45

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T5

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T5

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 341 Covered T2,T3,T10
StCtrlProg 339 Covered T3,T10,T4
StCtrlRead 337 Covered T1,T2,T3
StDisable 335 Covered T2,T10,T11
StIdle 349 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 369 Covered T2,T3,T10
StCtrlProg->StIdle 359 Covered T3,T10,T4
StCtrlRead->StIdle 349 Covered T1,T2,T3
StIdle->StCtrl 341 Covered T2,T3,T10
StIdle->StCtrlProg 339 Covered T3,T10,T4
StIdle->StCtrlRead 337 Covered T1,T2,T3
StIdle->StDisable 335 Covered T2,T10,T11



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 46 100.00
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 2 100.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 4 100.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T8,T221
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T8
0 0 0 Covered T1,T4,T5


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T2,T10,T11
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T3,T10,T4
StIdle 0 0 0 1 - - - Covered T2,T3,T10
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T3,T10,T4
StCtrlProg - - - - - 0 - Covered T3,T10,T4
StCtrl - - - - - - 1 Covered T3,T10,T25
StCtrl - - - - - - 0 Covered T2,T3,T10
StDisable - - - - - - - Covered T2,T10,T11
default - - - - - - - Covered T8,T14,T15


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 751738644 3035653 0 0
CtrlPrio_A 751738644 3035653 0 0
HostTransIdleChk_A 751738644 45352159 0 0
NoRemainder_A 2104 2104 0 0
OneHotReqs_A 751738644 750191292 0 0
Pow2Multiple_A 2104 2104 0 0
RdTxnCheck_A 751417462 749870110 0 0
u_state_regs_A 751738644 750191292 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 751738644 3035653 0 0
T1 241086 84357 0 0
T2 6902 0 0 0
T3 713698 0 0 0
T4 1010 0 0 0
T5 3166 0 0 0
T6 704944 9876 0 0
T10 1001834 0 0 0
T11 7682 0 0 0
T16 3626 0 0 0
T17 7016 0 0 0
T21 0 7387 0 0
T26 0 3792 0 0
T34 0 82297 0 0
T37 0 5886 0 0
T39 0 13835 0 0
T46 0 8517 0 0
T122 0 18047 0 0
T123 0 2270 0 0
T219 0 886 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 751738644 3035653 0 0
T1 241086 84357 0 0
T2 6902 0 0 0
T3 713698 0 0 0
T4 1010 0 0 0
T5 3166 0 0 0
T6 704944 9876 0 0
T10 1001834 0 0 0
T11 7682 0 0 0
T16 3626 0 0 0
T17 7016 0 0 0
T21 0 7387 0 0
T26 0 3792 0 0
T34 0 82297 0 0
T37 0 5886 0 0
T39 0 13835 0 0
T46 0 8517 0 0
T122 0 18047 0 0
T123 0 2270 0 0
T219 0 886 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 751738644 45352159 0 0
T1 241086 849406 0 0
T2 6902 0 0 0
T3 713698 0 0 0
T4 1010 14 0 0
T5 3166 20 0 0
T6 704944 144576 0 0
T10 1001834 0 0 0
T11 7682 0 0 0
T16 3626 0 0 0
T17 7016 0 0 0
T19 0 842778 0 0
T20 0 220 0 0
T21 0 72556 0 0
T26 0 41791 0 0
T46 0 41500 0 0
T47 0 14 0 0
T49 0 554 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2104 2104 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 751738644 750191292 0 0
T1 241086 241054 0 0
T2 6902 5622 0 0
T3 713698 680750 0 0
T4 1010 836 0 0
T5 3166 2874 0 0
T6 704944 704804 0 0
T10 1001834 1001568 0 0
T11 7682 6202 0 0
T16 3626 3338 0 0
T17 7016 5696 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2104 2104 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 751417462 749870110 0 0
T1 241086 241054 0 0
T2 6902 5622 0 0
T3 713698 680750 0 0
T4 1010 836 0 0
T5 3166 2874 0 0
T6 704944 704804 0 0
T10 1001834 1001568 0 0
T11 7682 6202 0 0
T16 3626 3338 0 0
T17 7016 5696 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 751738644 750191292 0 0
T1 241086 241054 0 0
T2 6902 5622 0 0
T3 713698 680750 0 0
T4 1010 836 0 0
T5 3166 2874 0 0
T6 704944 704804 0 0
T10 1001834 1001568 0 0
T11 7682 6202 0 0
T16 3626 3338 0 0
T17 7016 5696 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS22966100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1069185.85
Logical1069185.85
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T4,T5
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T16,T5
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T6
110Not Covered
111CoveredT1,T4,T5

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T6
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T4,T5

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT220,T209
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT66
10CoveredT1,T16,T5
11CoveredT1,T4,T5

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T16,T5
11CoveredT1,T6,T26

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T6,T23
11CoveredT1,T5,T6

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT3,T10,T4
10CoveredT13,T31,T44
11CoveredT16,T6,T23

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T6,T23
11CoveredT1,T5,T6

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT3,T10,T4
10CoveredT1,T5,T6
11CoveredT16,T6,T23

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T16,T5
11CoveredT13,T31,T44

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT43,T44,T62
10CoveredT2,T3,T10

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T4,T5
10Not Covered
11Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T6,T23
11CoveredT1,T4,T5

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T5
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T45
10CoveredT14,T15,T45

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT23,T20,T13

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T26
10CoveredT23,T20,T13

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T20,T13

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T20,T13

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 341 Covered T13,T31,T44
StCtrlProg 339 Covered T16,T6,T23
StCtrlRead 337 Covered T1,T5,T6
StDisable 335 Covered T2,T10,T11
StIdle 349 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 369 Covered T13,T31,T44
StCtrlProg->StIdle 359 Covered T16,T6,T23
StCtrlRead->StIdle 349 Covered T1,T5,T6
StIdle->StCtrl 341 Covered T13,T31,T44
StIdle->StCtrlProg 339 Covered T16,T6,T23
StIdle->StCtrlRead 337 Covered T1,T5,T6
StIdle->StDisable 335 Covered T2,T10,T11



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 1 50.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 4 100.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T23,T20,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T23,T20,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T16,T5
0 0 1 Covered T1,T6,T26
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T8
0 0 0 Covered T1,T4,T5


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T8
0 0 0 Covered T1,T4,T16


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T2,T10,T11
StIdle 0 1 - - - - - Covered T1,T5,T6
StIdle 0 0 1 - - - - Covered T16,T6,T23
StIdle 0 0 0 1 - - - Covered T13,T31,T44
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T5,T6
StCtrlRead - - - - 0 - - Covered T1,T5,T6
StCtrlProg - - - - - 1 - Covered T16,T6,T23
StCtrlProg - - - - - 0 - Covered T16,T6,T23
StCtrl - - - - - - 1 Covered T13,T31,T44
StCtrl - - - - - - 0 Covered T13,T31,T44
StDisable - - - - - - - Covered T2,T10,T11
default - - - - - - - Covered T8,T14,T15


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 375869322 1495693 0 0
CtrlPrio_A 375869322 1495693 0 0
HostTransIdleChk_A 375869322 22743426 0 0
NoRemainder_A 1052 1052 0 0
OneHotReqs_A 375869322 375095646 0 0
Pow2Multiple_A 1052 1052 0 0
RdTxnCheck_A 375708731 374935055 0 0
u_state_regs_A 375869322 375095646 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 1495693 0 0
T1 120543 23793 0 0
T2 3451 0 0 0
T3 356849 0 0 0
T4 505 0 0 0
T5 1583 0 0 0
T6 352472 5362 0 0
T10 500917 0 0 0
T11 3841 0 0 0
T16 1813 0 0 0
T17 3508 0 0 0
T21 0 3885 0 0
T26 0 1728 0 0
T34 0 35329 0 0
T39 0 4881 0 0
T46 0 5259 0 0
T122 0 8284 0 0
T123 0 1110 0 0
T219 0 886 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 1495693 0 0
T1 120543 23793 0 0
T2 3451 0 0 0
T3 356849 0 0 0
T4 505 0 0 0
T5 1583 0 0 0
T6 352472 5362 0 0
T10 500917 0 0 0
T11 3841 0 0 0
T16 1813 0 0 0
T17 3508 0 0 0
T21 0 3885 0 0
T26 0 1728 0 0
T34 0 35329 0 0
T39 0 4881 0 0
T46 0 5259 0 0
T122 0 8284 0 0
T123 0 1110 0 0
T219 0 886 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 22743426 0 0
T1 120543 406573 0 0
T2 3451 0 0 0
T3 356849 0 0 0
T4 505 8 0 0
T5 1583 12 0 0
T6 352472 66193 0 0
T10 500917 0 0 0
T11 3841 0 0 0
T16 1813 0 0 0
T17 3508 0 0 0
T19 0 460941 0 0
T20 0 142 0 0
T21 0 35548 0 0
T26 0 20758 0 0
T47 0 14 0 0
T49 0 352 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 375095646 0 0
T1 120543 120527 0 0
T2 3451 2811 0 0
T3 356849 340375 0 0
T4 505 418 0 0
T5 1583 1437 0 0
T6 352472 352402 0 0
T10 500917 500784 0 0
T11 3841 3101 0 0
T16 1813 1669 0 0
T17 3508 2848 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375708731 374935055 0 0
T1 120543 120527 0 0
T2 3451 2811 0 0
T3 356849 340375 0 0
T4 505 418 0 0
T5 1583 1437 0 0
T6 352472 352402 0 0
T10 500917 500784 0 0
T11 3841 3101 0 0
T16 1813 1669 0 0
T17 3508 2848 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 375095646 0 0
T1 120543 120527 0 0
T2 3451 2811 0 0
T3 356849 340375 0 0
T4 505 418 0 0
T5 1583 1437 0 0
T6 352472 352402 0 0
T10 500917 500784 0 0
T11 3841 3101 0 0
T16 1813 1669 0 0
T17 3508 2848 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS22966100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions10610195.28
Logical10610195.28
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT4,T8,T221

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T8,T221

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T6
110Not Covered
111CoveredT1,T4,T5

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T6
101CoveredT1,T4,T5
110CoveredT55
111CoveredT1,T4,T5

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT64,T65
10CoveredT1,T2,T3
11CoveredT1,T4,T5

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT2,T3,T10
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT4,T16,T6
10CoveredT2,T3,T10
11CoveredT3,T10,T4

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT55
10CoveredT120,T222,T223

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT120,T222,T223

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT55

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T10,T4
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT3,T10,T4
10CoveredT1,T2,T3
11CoveredT3,T10,T4

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T2,T3
11CoveredT3,T10,T25

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT43,T44,T62
10CoveredT2,T3,T10

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT4
11CoveredT4

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T10
11CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T5
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T45
10CoveredT14,T15,T45

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T5

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT3,T4,T5

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 341 Covered T2,T3,T10
StCtrlProg 339 Covered T3,T10,T4
StCtrlRead 337 Covered T1,T2,T3
StDisable 335 Covered T2,T10,T11
StIdle 349 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 369 Covered T2,T3,T10
StCtrlProg->StIdle 359 Covered T3,T10,T4
StCtrlRead->StIdle 349 Covered T1,T2,T3
StIdle->StCtrl 341 Covered T2,T3,T10
StIdle->StCtrlProg 339 Covered T3,T10,T4
StIdle->StCtrlRead 337 Covered T1,T2,T3
StIdle->StDisable 335 Covered T2,T10,T11



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 46 100.00
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 2 100.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 4 100.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T8,T221
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T8
0 0 0 Covered T1,T4,T5


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T2,T10,T11
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T3,T10,T4
StIdle 0 0 0 1 - - - Covered T2,T3,T10
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T3,T10,T4
StCtrlProg - - - - - 0 - Covered T3,T10,T4
StCtrl - - - - - - 1 Covered T3,T10,T25
StCtrl - - - - - - 0 Covered T2,T3,T10
StDisable - - - - - - - Covered T2,T10,T11
default - - - - - - - Covered T8,T14,T15


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 375869322 1539960 0 0
CtrlPrio_A 375869322 1539960 0 0
HostTransIdleChk_A 375869322 22608733 0 0
NoRemainder_A 1052 1052 0 0
OneHotReqs_A 375869322 375095646 0 0
Pow2Multiple_A 1052 1052 0 0
RdTxnCheck_A 375708731 374935055 0 0
u_state_regs_A 375869322 375095646 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 1539960 0 0
T1 120543 60564 0 0
T2 3451 0 0 0
T3 356849 0 0 0
T4 505 0 0 0
T5 1583 0 0 0
T6 352472 4514 0 0
T10 500917 0 0 0
T11 3841 0 0 0
T16 1813 0 0 0
T17 3508 0 0 0
T21 0 3502 0 0
T26 0 2064 0 0
T34 0 46968 0 0
T37 0 5886 0 0
T39 0 8954 0 0
T46 0 3258 0 0
T122 0 9763 0 0
T123 0 1160 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 1539960 0 0
T1 120543 60564 0 0
T2 3451 0 0 0
T3 356849 0 0 0
T4 505 0 0 0
T5 1583 0 0 0
T6 352472 4514 0 0
T10 500917 0 0 0
T11 3841 0 0 0
T16 1813 0 0 0
T17 3508 0 0 0
T21 0 3502 0 0
T26 0 2064 0 0
T34 0 46968 0 0
T37 0 5886 0 0
T39 0 8954 0 0
T46 0 3258 0 0
T122 0 9763 0 0
T123 0 1160 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 22608733 0 0
T1 120543 442833 0 0
T2 3451 0 0 0
T3 356849 0 0 0
T4 505 6 0 0
T5 1583 8 0 0
T6 352472 78383 0 0
T10 500917 0 0 0
T11 3841 0 0 0
T16 1813 0 0 0
T17 3508 0 0 0
T19 0 381837 0 0
T20 0 78 0 0
T21 0 37008 0 0
T26 0 21033 0 0
T46 0 41500 0 0
T49 0 202 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 375095646 0 0
T1 120543 120527 0 0
T2 3451 2811 0 0
T3 356849 340375 0 0
T4 505 418 0 0
T5 1583 1437 0 0
T6 352472 352402 0 0
T10 500917 500784 0 0
T11 3841 3101 0 0
T16 1813 1669 0 0
T17 3508 2848 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375708731 374935055 0 0
T1 120543 120527 0 0
T2 3451 2811 0 0
T3 356849 340375 0 0
T4 505 418 0 0
T5 1583 1437 0 0
T6 352472 352402 0 0
T10 500917 500784 0 0
T11 3841 3101 0 0
T16 1813 1669 0 0
T17 3508 2848 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375869322 375095646 0 0
T1 120543 120527 0 0
T2 3451 2811 0 0
T3 356849 340375 0 0
T4 505 418 0 0
T5 1583 1437 0 0
T6 352472 352402 0 0
T10 500917 500784 0 0
T11 3841 3101 0 0
T16 1813 1669 0 0
T17 3508 2848 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%