Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1503477288	1500382584	0	0
CheckNGreaterZero_A	4208	4208	0	0
GntImpliesReady_A	1503477288	414635700	0	0
GntImpliesValid_A	1503477288	414635700	0	0
GrantKnown_A	1503477288	1500382584	0	0
IdxKnown_A	1503477288	1500382584	0	0
IndexIsCorrect_A	1503477288	414635700	0	0
NoReadyValidNoGrant_A	1503477288	183169348	0	0
Priority_A	1503477288	439261808	0	0
ReadyAndValidImplyGrant_A	1503477288	414635700	0	0
ReqAndReadyImplyGrant_A	1503477288	414635700	0	0
ReqImpliesValid_A	1503477288	439261808	0	0
ValidKnown_A	1503477288	1500382584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	1500382584	0	0
T1	482172	482108	0	0
T2	13804	11244	0	0
T3	1427396	1361500	0	0
T4	2020	1672	0	0
T5	6332	5748	0	0
T6	1409888	1409608	0	0
T10	2003668	2003136	0	0
T11	15364	12404	0	0
T16	7252	6676	0	0
T17	14032	11392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4208	4208	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	414635700	0	0
T1	482172	85834	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	102	0	0
T5	6332	356	0	0
T6	1409888	460750	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	18082	0	0
T20	0	44918	0	0
T23	0	197832	0	0
T26	0	43830	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	414635700	0	0
T1	482172	85834	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	102	0	0
T5	6332	356	0	0
T6	1409888	460750	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	18082	0	0
T20	0	44918	0	0
T23	0	197832	0	0
T26	0	43830	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	1500382584	0	0
T1	482172	482108	0	0
T2	13804	11244	0	0
T3	1427396	1361500	0	0
T4	2020	1672	0	0
T5	6332	5748	0	0
T6	1409888	1409608	0	0
T10	2003668	2003136	0	0
T11	15364	12404	0	0
T16	7252	6676	0	0
T17	14032	11392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	1500382584	0	0
T1	482172	482108	0	0
T2	13804	11244	0	0
T3	1427396	1361500	0	0
T4	2020	1672	0	0
T5	6332	5748	0	0
T6	1409888	1409608	0	0
T10	2003668	2003136	0	0
T11	15364	12404	0	0
T16	7252	6676	0	0
T17	14032	11392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	414635700	0	0
T1	482172	85834	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	102	0	0
T5	6332	356	0	0
T6	1409888	460750	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	18082	0	0
T20	0	44918	0	0
T23	0	197832	0	0
T26	0	43830	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	183169348	0	0
T1	482172	2629046	0	0
T2	13804	1628	0	0
T3	1427396	81000	0	0
T4	2020	274	0	0
T5	6332	770	0	0
T6	1409888	190662	0	0
T10	2003668	256	0	0
T11	15364	1148	0	0
T13	0	1048576	0	0
T16	7252	512	0	0
T17	14032	1052	0	0
T19	0	595646	0	0
T20	0	3554	0	0
T26	0	71382	0	0
T31	0	3340	0	0
T38	0	5348	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	439261808	0	0
T1	482172	580618	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	112	0	0
T5	6332	356	0	0
T6	1409888	537210	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	335790	0	0
T20	0	44942	0	0
T23	0	197832	0	0
T26	0	48222	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	414635700	0	0
T1	482172	85834	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	102	0	0
T5	6332	356	0	0
T6	1409888	460750	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	18082	0	0
T20	0	44918	0	0
T23	0	197832	0	0
T26	0	43830	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	414635700	0	0
T1	482172	85834	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	102	0	0
T5	6332	356	0	0
T6	1409888	460750	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	18082	0	0
T20	0	44918	0	0
T23	0	197832	0	0
T26	0	43830	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	439261808	0	0
T1	482172	580618	0	0
T2	13804	432	0	0
T3	1427396	307932	0	0
T4	2020	112	0	0
T5	6332	356	0	0
T6	1409888	537210	0	0
T10	2003668	1104	0	0
T11	15364	290	0	0
T13	0	255794	0	0
T16	7252	138	0	0
T17	14032	294	0	0
T19	0	335790	0	0
T20	0	44942	0	0
T23	0	197832	0	0
T26	0	48222	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503477288	1500382584	0	0
T1	482172	482108	0	0
T2	13804	11244	0	0
T3	1427396	1361500	0	0
T4	2020	1672	0	0
T5	6332	5748	0	0
T6	1409888	1409608	0	0
T10	2003668	2003136	0	0
T11	15364	12404	0	0
T16	7252	6676	0	0
T17	14032	11392	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375869322	375095646	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375869322	112312106	0	0
GntImpliesValid_A	375869322	112312106	0	0
GrantKnown_A	375869322	375095646	0	0
IdxKnown_A	375869322	375095646	0	0
IndexIsCorrect_A	375869322	112312106	0	0
NoReadyValidNoGrant_A	375869322	47705164	0	0
Priority_A	375869322	118305895	0	0
ReadyAndValidImplyGrant_A	375869322	112312106	0	0
ReqAndReadyImplyGrant_A	375869322	112312106	0	0
ReqImpliesValid_A	375869322	118305895	0	0
ValidKnown_A	375869322	375095646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112312106	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112312106	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112312106	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	47705164	0	0
T1	120543	661745	0	0
T2	3451	814	0	0
T3	356849	40500	0	0
T4	505	132	0	0
T5	1583	328	0	0
T6	352472	47616	0	0
T10	500917	128	0	0
T11	3841	574	0	0
T16	1813	256	0	0
T17	3508	526	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	118305895	0	0
T1	120543	161674	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	49	0	0
T5	1583	157	0	0
T6	352472	175152	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112312106	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112312106	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	118305895	0	0
T1	120543	161674	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	49	0	0
T5	1583	157	0	0
T6	352472	175152	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375869322	375095646	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375869322	112311960	0	0
GntImpliesValid_A	375869322	112311960	0	0
GrantKnown_A	375869322	375095646	0	0
IdxKnown_A	375869322	375095646	0	0
IndexIsCorrect_A	375869322	112311960	0	0
NoReadyValidNoGrant_A	375869322	47705165	0	0
Priority_A	375869322	118305748	0	0
ReadyAndValidImplyGrant_A	375869322	112311960	0	0
ReqAndReadyImplyGrant_A	375869322	112311960	0	0
ReqImpliesValid_A	375869322	118305748	0	0
ValidKnown_A	375869322	375095646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112311960	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112311960	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112311960	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	47705165	0	0
T1	120543	661745	0	0
T2	3451	814	0	0
T3	356849	40500	0	0
T4	505	132	0	0
T5	1583	328	0	0
T6	352472	47616	0	0
T10	500917	128	0	0
T11	3841	574	0	0
T16	1813	256	0	0
T17	3508	526	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	118305748	0	0
T1	120543	161674	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	49	0	0
T5	1583	157	0	0
T6	352472	175152	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112311960	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	112311960	0	0
T1	120543	21616	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	47	0	0
T5	1583	157	0	0
T6	352472	148386	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	118305748	0	0
T1	120543	161674	0	0
T2	3451	216	0	0
T3	356849	153966	0	0
T4	505	49	0	0
T5	1583	157	0	0
T6	352472	175152	0	0
T10	500917	552	0	0
T11	3841	145	0	0
T16	1813	64	0	0
T17	3508	147	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T16,T5
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T16,T5
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T16,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375869322	375095646	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375869322	95005811	0	0
GntImpliesValid_A	375869322	95005811	0	0
GrantKnown_A	375869322	375095646	0	0
IdxKnown_A	375869322	375095646	0	0
IndexIsCorrect_A	375869322	95005811	0	0
NoReadyValidNoGrant_A	375869322	43879532	0	0
Priority_A	375869322	101325054	0	0
ReadyAndValidImplyGrant_A	375869322	95005811	0	0
ReqAndReadyImplyGrant_A	375869322	95005811	0	0
ReqImpliesValid_A	375869322	101325054	0	0
ValidKnown_A	375869322	375095646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005811	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005811	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005811	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	43879532	0	0
T1	120543	652778	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	5	0	0
T5	1583	57	0	0
T6	352472	47715	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	524288	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	297823	0	0
T20	0	1777	0	0
T26	0	35691	0	0
T31	0	1670	0	0
T38	0	2674	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	101325054	0	0
T1	120543	128635	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	7	0	0
T5	1583	21	0	0
T6	352472	93453	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	167895	0	0
T20	0	22471	0	0
T23	0	98916	0	0
T26	0	24111	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005811	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005811	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	101325054	0	0
T1	120543	128635	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	7	0	0
T5	1583	21	0	0
T6	352472	93453	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	167895	0	0
T20	0	22471	0	0
T23	0	98916	0	0
T26	0	24111	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T16,T5
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T16,T5
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T16,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375869322	375095646	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375869322	95005823	0	0
GntImpliesValid_A	375869322	95005823	0	0
GrantKnown_A	375869322	375095646	0	0
IdxKnown_A	375869322	375095646	0	0
IndexIsCorrect_A	375869322	95005823	0	0
NoReadyValidNoGrant_A	375869322	43879487	0	0
Priority_A	375869322	101325111	0	0
ReadyAndValidImplyGrant_A	375869322	95005823	0	0
ReqAndReadyImplyGrant_A	375869322	95005823	0	0
ReqImpliesValid_A	375869322	101325111	0	0
ValidKnown_A	375869322	375095646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005823	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005823	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005823	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	43879487	0	0
T1	120543	652778	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	5	0	0
T5	1583	57	0	0
T6	352472	47715	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	524288	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	297823	0	0
T20	0	1777	0	0
T26	0	35691	0	0
T31	0	1670	0	0
T38	0	2674	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	101325111	0	0
T1	120543	128635	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	7	0	0
T5	1583	21	0	0
T6	352472	93453	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	167895	0	0
T20	0	22471	0	0
T23	0	98916	0	0
T26	0	24111	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005823	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95005823	0	0
T1	120543	21301	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	21	0	0
T6	352472	81989	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	9041	0	0
T20	0	22459	0	0
T23	0	98916	0	0
T26	0	21915	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	101325111	0	0
T1	120543	128635	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	7	0	0
T5	1583	21	0	0
T6	352472	93453	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	127897	0	0
T16	1813	5	0	0
T17	3508	0	0	0
T19	0	167895	0	0
T20	0	22471	0	0
T23	0	98916	0	0
T26	0	24111	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0