SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[2].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[2].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.19 | 100.00 | 68.75 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.36 | 100.00 | 75.00 | 94.44 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
83.96 | 100.00 | 65.52 | 85.71 | 84.62 | u_to_prog_fifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 90.30 | 100.00 | 80.00 | 90.91 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
67.47 | 85.71 | 38.46 | 85.71 | 60.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
72.63 | 94.44 | 54.84 | 81.25 | 60.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
83.96 | 100.00 | 65.52 | 85.71 | 84.62 | u_to_prog_fifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 81.48 | 100.00 | 66.67 | 77.78 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 378381112 | 4107582 | 0 | 0 |
DepthKnown_A | 378381112 | 377518828 | 0 | 0 |
RvalidKnown_A | 378381112 | 377518828 | 0 | 0 |
WreadyKnown_A | 378381112 | 377518828 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1267 | 1267 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 4107582 | 0 | 0 |
T1 | 120543 | 26224 | 0 | 0 |
T2 | 3451 | 0 | 0 | 0 |
T3 | 356849 | 5056 | 0 | 0 |
T4 | 505 | 0 | 0 | 0 |
T5 | 1583 | 44 | 0 | 0 |
T6 | 352472 | 5717 | 0 | 0 |
T10 | 500917 | 0 | 0 | 0 |
T11 | 3841 | 0 | 0 | 0 |
T16 | 1813 | 0 | 0 | 0 |
T17 | 3508 | 0 | 0 | 0 |
T20 | 0 | 2178 | 0 | 0 |
T25 | 0 | 8662 | 0 | 0 |
T26 | 0 | 27360 | 0 | 0 |
T31 | 0 | 31558 | 0 | 0 |
T38 | 0 | 2721 | 0 | 0 |
T49 | 0 | 693 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1267 | 1267 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 378381112 | 32595996 | 0 | 0 |
DepthKnown_A | 378381112 | 377518828 | 0 | 0 |
RvalidKnown_A | 378381112 | 377518828 | 0 | 0 |
WreadyKnown_A | 378381112 | 377518828 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1267 | 1267 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 32595996 | 0 | 0 |
T1 | 120543 | 45304 | 0 | 0 |
T2 | 3451 | 505 | 0 | 0 |
T3 | 356849 | 39226 | 0 | 0 |
T4 | 505 | 109 | 0 | 0 |
T5 | 1583 | 381 | 0 | 0 |
T6 | 352472 | 179742 | 0 | 0 |
T10 | 500917 | 161 | 0 | 0 |
T11 | 3841 | 114 | 0 | 0 |
T16 | 1813 | 108 | 0 | 0 |
T17 | 3508 | 505 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1267 | 1267 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 378381112 | 36243858 | 0 | 0 |
DepthKnown_A | 378381112 | 377518828 | 0 | 0 |
RvalidKnown_A | 378381112 | 377518828 | 0 | 0 |
WreadyKnown_A | 378381112 | 377518828 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 1267 | 1267 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 36243858 | 0 | 0 |
T1 | 120543 | 45304 | 0 | 0 |
T2 | 3451 | 505 | 0 | 0 |
T3 | 356849 | 39226 | 0 | 0 |
T4 | 505 | 109 | 0 | 0 |
T5 | 1583 | 381 | 0 | 0 |
T6 | 352472 | 158116 | 0 | 0 |
T10 | 500917 | 161 | 0 | 0 |
T11 | 3841 | 476 | 0 | 0 |
T16 | 1813 | 108 | 0 | 0 |
T17 | 3508 | 505 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 378381112 | 377518828 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1267 | 1267 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T3,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T16 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T16 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T16 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T3,T4,T16 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T3,T4,T16 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T3,T4,T16 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 375869322 | 2620017 | 0 | 0 |
DepthKnown_A | 375869322 | 375095646 | 0 | 0 |
RvalidKnown_A | 375869322 | 375095646 | 0 | 0 |
WreadyKnown_A | 375869322 | 375095646 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 375869322 | 2620017 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 2620017 | 0 | 0 |
T3 | 356849 | 2560 | 0 | 0 |
T4 | 505 | 4 | 0 | 0 |
T5 | 1583 | 2 | 0 | 0 |
T6 | 352472 | 10532 | 0 | 0 |
T10 | 500917 | 0 | 0 | 0 |
T11 | 3841 | 0 | 0 | 0 |
T16 | 1813 | 2 | 0 | 0 |
T17 | 3508 | 0 | 0 | 0 |
T19 | 584196 | 0 | 0 | 0 |
T20 | 0 | 2008 | 0 | 0 |
T23 | 0 | 7630 | 0 | 0 |
T25 | 217136 | 4182 | 0 | 0 |
T31 | 0 | 54344 | 0 | 0 |
T38 | 0 | 1236 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 375095646 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 375095646 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 375095646 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 2620017 | 0 | 0 |
T3 | 356849 | 2560 | 0 | 0 |
T4 | 505 | 4 | 0 | 0 |
T5 | 1583 | 2 | 0 | 0 |
T6 | 352472 | 10532 | 0 | 0 |
T10 | 500917 | 0 | 0 | 0 |
T11 | 3841 | 0 | 0 | 0 |
T16 | 1813 | 2 | 0 | 0 |
T17 | 3508 | 0 | 0 | 0 |
T19 | 584196 | 0 | 0 | 0 |
T20 | 0 | 2008 | 0 | 0 |
T23 | 0 | 7630 | 0 | 0 |
T25 | 217136 | 4182 | 0 | 0 |
T31 | 0 | 54344 | 0 | 0 |
T38 | 0 | 1236 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 12 | 85.71 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 0 | 0 | |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | unreachable | ||
108 | 0 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 0 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 13 | 5 | 38.46 |
Logical | 13 | 5 | 38.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 6 | 85.71 | |
TERNARY | 138 | 2 | 1 | 50.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Not Covered |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T8 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 3 | 60.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 3 | 60.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 375869322 | 0 | 0 | 0 |
DepthKnown_A | 375869322 | 375095646 | 0 | 0 |
RvalidKnown_A | 375869322 | 375095646 | 0 | 0 |
WreadyKnown_A | 375869322 | 375095646 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 375869322 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 375095646 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 375095646 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 375095646 | 0 | 0 |
T1 | 120543 | 120527 | 0 | 0 |
T2 | 3451 | 2811 | 0 | 0 |
T3 | 356849 | 340375 | 0 | 0 |
T4 | 505 | 418 | 0 | 0 |
T5 | 1583 | 1437 | 0 | 0 |
T6 | 352472 | 352402 | 0 | 0 |
T10 | 500917 | 500784 | 0 | 0 |
T11 | 3841 | 3101 | 0 | 0 |
T16 | 1813 | 1669 | 0 | 0 |
T17 | 3508 | 2848 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 375869322 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |