Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.u_bank_sequence_fifo

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.09	100.00	92.86		87.50	100.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.45	100.00	87.23	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.93	100.00	91.70			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (1'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375869322	33599175	0	0
DepthKnown_A	375869322	375095646	0	0
RvalidKnown_A	375869322	375095646	0	0
WreadyKnown_A	375869322	375095646	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375869322	33599175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	33599175	0	0
T1	120543	608756	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	12	0	0
T5	1583	20	0	0
T6	352472	131067	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	577128	0	0
T20	0	200	0	0
T21	0	60843	0	0
T26	0	35740	0	0
T47	0	14	0	0
T49	0	554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	33599175	0	0
T1	120543	608756	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	12	0	0
T5	1583	20	0	0
T6	352472	131067	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	577128	0	0
T20	0	200	0	0
T21	0	60843	0	0
T26	0	35740	0	0
T47	0	14	0	0
T49	0	554	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T25
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (101'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375869322	95707400	0	0
DepthKnown_A	375869322	375095646	0	0
RvalidKnown_A	375869322	375095646	0	0
WreadyKnown_A	375869322	375095646	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375869322	95707400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95707400	0	0
T1	120543	15678	0	0
T2	3451	214	0	0
T3	356849	161148	0	0
T4	505	37	0	0
T5	1583	133	0	0
T6	352472	174322	0	0
T10	500917	544	0	0
T11	3841	144	0	0
T16	1813	64	0	0
T17	3508	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	95707400	0	0
T1	120543	15678	0	0
T2	3451	214	0	0
T3	356849	161148	0	0
T4	505	37	0	0
T5	1583	133	0	0
T6	352472	174322	0	0
T10	500917	544	0	0
T11	3841	144	0	0
T16	1813	64	0	0
T17	3508	142	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T23,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T23,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (101'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375869322	79090268	0	0
DepthKnown_A	375869322	375095646	0	0
RvalidKnown_A	375869322	375095646	0	0
WreadyKnown_A	375869322	375095646	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375869322	79090268	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	79090268	0	0
T1	120543	14842	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	12	0	0
T6	352472	88099	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	786944	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	9038	0	0
T20	0	20184	0	0
T23	0	90180	0	0
T26	0	15402	0	0
T38	0	11480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	375095646	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375869322	79090268	0	0
T1	120543	14842	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	4	0	0
T5	1583	12	0	0
T6	352472	88099	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T13	0	786944	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	9038	0	0
T20	0	20184	0	0
T23	0	90180	0	0
T26	0	15402	0	0
T38	0	11480	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T26,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T55
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T26,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T26,T20
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375708731	2882693	0	0
DepthKnown_A	375708731	374935055	0	0
RvalidKnown_A	375708731	374935055	0	0
WreadyKnown_A	375708731	374935055	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375708731	2882693	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	2882693	0	0
T1	120543	8683	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	2	0	0
T5	1583	2	0	0
T6	352472	32491	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	7487	0	0
T20	0	50	0	0
T21	0	11289	0	0
T26	0	8936	0	0
T46	0	18211	0	0
T49	0	130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	374935055	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	374935055	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	374935055	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	2882693	0	0
T1	120543	8683	0	0
T2	3451	0	0	0
T3	356849	0	0	0
T4	505	2	0	0
T5	1583	2	0	0
T6	352472	32491	0	0
T10	500917	0	0	0
T11	3841	0	0	0
T16	1813	0	0	0
T17	3508	0	0	0
T19	0	7487	0	0
T20	0	50	0	0
T21	0	11289	0	0
T26	0	8936	0	0
T46	0	18211	0	0
T49	0	130	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T26,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (6'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375708731	54390312	0	0
DepthKnown_A	375708731	374935055	0	0
RvalidKnown_A	375708731	374935055	0	0
WreadyKnown_A	375708731	374935055	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375708731	54390312	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	54390312	0	0
T1	120543	805547	0	0
T2	3451	814	0	0
T3	356849	40500	0	0
T4	505	134	0	0
T5	1583	328	0	0
T6	352472	81230	0	0
T10	500917	128	0	0
T11	3841	574	0	0
T16	1813	256	0	0
T17	3508	526	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	374935055	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	374935055	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	374935055	0	0
T1	120543	120527	0	0
T2	3451	2811	0	0
T3	356849	340375	0	0
T4	505	418	0	0
T5	1583	1437	0	0
T6	352472	352402	0	0
T10	500917	500784	0	0
T11	3841	3101	0	0
T16	1813	1669	0	0
T17	3508	2848	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375708731	54390312	0	0
T1	120543	805547	0	0
T2	3451	814	0	0
T3	356849	40500	0	0
T4	505	134	0	0
T5	1583	328	0	0
T6	352472	81230	0	0
T10	500917	128	0	0
T11	3841	574	0	0
T16	1813	256	0	0
T17	3508	526	0	0