Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T54 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (76'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
14503181 |
0 |
0 |
T1 |
120543 |
15713 |
0 |
0 |
T2 |
3451 |
406 |
0 |
0 |
T3 |
356849 |
18936 |
0 |
0 |
T4 |
505 |
67 |
0 |
0 |
T5 |
1583 |
158 |
0 |
0 |
T6 |
352472 |
22723 |
0 |
0 |
T10 |
500917 |
64 |
0 |
0 |
T11 |
3841 |
286 |
0 |
0 |
T16 |
1813 |
128 |
0 |
0 |
T17 |
3508 |
262 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
14503181 |
0 |
0 |
T1 |
120543 |
15713 |
0 |
0 |
T2 |
3451 |
406 |
0 |
0 |
T3 |
356849 |
18936 |
0 |
0 |
T4 |
505 |
67 |
0 |
0 |
T5 |
1583 |
158 |
0 |
0 |
T6 |
352472 |
22723 |
0 |
0 |
T10 |
500917 |
64 |
0 |
0 |
T11 |
3841 |
286 |
0 |
0 |
T16 |
1813 |
128 |
0 |
0 |
T17 |
3508 |
262 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T6,T19 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (64'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
13511916 |
0 |
0 |
T1 |
120543 |
1844 |
0 |
0 |
T2 |
3451 |
406 |
0 |
0 |
T3 |
356849 |
18936 |
0 |
0 |
T4 |
505 |
66 |
0 |
0 |
T5 |
1583 |
158 |
0 |
0 |
T6 |
352472 |
360 |
0 |
0 |
T10 |
500917 |
64 |
0 |
0 |
T11 |
3841 |
286 |
0 |
0 |
T16 |
1813 |
128 |
0 |
0 |
T17 |
3508 |
262 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
375095646 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
375095646 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
375095646 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
13511916 |
0 |
0 |
T1 |
120543 |
1844 |
0 |
0 |
T2 |
3451 |
406 |
0 |
0 |
T3 |
356849 |
18936 |
0 |
0 |
T4 |
505 |
66 |
0 |
0 |
T5 |
1583 |
158 |
0 |
0 |
T6 |
352472 |
360 |
0 |
0 |
T10 |
500917 |
64 |
0 |
0 |
T11 |
3841 |
286 |
0 |
0 |
T16 |
1813 |
128 |
0 |
0 |
T17 |
3508 |
262 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T26,T20 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (16'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
54390312 |
0 |
0 |
T1 |
120543 |
805547 |
0 |
0 |
T2 |
3451 |
814 |
0 |
0 |
T3 |
356849 |
40500 |
0 |
0 |
T4 |
505 |
134 |
0 |
0 |
T5 |
1583 |
328 |
0 |
0 |
T6 |
352472 |
81230 |
0 |
0 |
T10 |
500917 |
128 |
0 |
0 |
T11 |
3841 |
574 |
0 |
0 |
T16 |
1813 |
256 |
0 |
0 |
T17 |
3508 |
526 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
375095646 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
375095646 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
375095646 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375869322 |
54390312 |
0 |
0 |
T1 |
120543 |
805547 |
0 |
0 |
T2 |
3451 |
814 |
0 |
0 |
T3 |
356849 |
40500 |
0 |
0 |
T4 |
505 |
134 |
0 |
0 |
T5 |
1583 |
328 |
0 |
0 |
T6 |
352472 |
81230 |
0 |
0 |
T10 |
500917 |
128 |
0 |
0 |
T11 |
3841 |
574 |
0 |
0 |
T16 |
1813 |
256 |
0 |
0 |
T17 |
3508 |
526 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T26 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T6,T26 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T26 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
2840114 |
0 |
0 |
T1 |
120543 |
8023 |
0 |
0 |
T2 |
3451 |
0 |
0 |
0 |
T3 |
356849 |
0 |
0 |
0 |
T4 |
505 |
4 |
0 |
0 |
T5 |
1583 |
3 |
0 |
0 |
T6 |
352472 |
38327 |
0 |
0 |
T10 |
500917 |
0 |
0 |
0 |
T11 |
3841 |
0 |
0 |
0 |
T16 |
1813 |
0 |
0 |
0 |
T17 |
3508 |
0 |
0 |
0 |
T19 |
0 |
9041 |
0 |
0 |
T20 |
0 |
80 |
0 |
0 |
T21 |
0 |
12693 |
0 |
0 |
T26 |
0 |
9441 |
0 |
0 |
T47 |
0 |
9 |
0 |
0 |
T49 |
0 |
230 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
2840114 |
0 |
0 |
T1 |
120543 |
8023 |
0 |
0 |
T2 |
3451 |
0 |
0 |
0 |
T3 |
356849 |
0 |
0 |
0 |
T4 |
505 |
4 |
0 |
0 |
T5 |
1583 |
3 |
0 |
0 |
T6 |
352472 |
38327 |
0 |
0 |
T10 |
500917 |
0 |
0 |
0 |
T11 |
3841 |
0 |
0 |
0 |
T16 |
1813 |
0 |
0 |
0 |
T17 |
3508 |
0 |
0 |
0 |
T19 |
0 |
9041 |
0 |
0 |
T20 |
0 |
80 |
0 |
0 |
T21 |
0 |
12693 |
0 |
0 |
T26 |
0 |
9441 |
0 |
0 |
T47 |
0 |
9 |
0 |
0 |
T49 |
0 |
230 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T26,T20 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (6'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
50907228 |
0 |
0 |
T1 |
120543 |
763401 |
0 |
0 |
T2 |
3451 |
0 |
0 |
0 |
T3 |
356849 |
0 |
0 |
0 |
T4 |
505 |
8 |
0 |
0 |
T5 |
1583 |
57 |
0 |
0 |
T6 |
352472 |
68591 |
0 |
0 |
T10 |
500917 |
0 |
0 |
0 |
T11 |
3841 |
0 |
0 |
0 |
T13 |
0 |
524288 |
0 |
0 |
T16 |
1813 |
0 |
0 |
0 |
T17 |
3508 |
0 |
0 |
0 |
T19 |
0 |
460941 |
0 |
0 |
T20 |
0 |
1815 |
0 |
0 |
T26 |
0 |
41503 |
0 |
0 |
T31 |
0 |
1670 |
0 |
0 |
T38 |
0 |
2674 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
374935055 |
0 |
0 |
T1 |
120543 |
120527 |
0 |
0 |
T2 |
3451 |
2811 |
0 |
0 |
T3 |
356849 |
340375 |
0 |
0 |
T4 |
505 |
418 |
0 |
0 |
T5 |
1583 |
1437 |
0 |
0 |
T6 |
352472 |
352402 |
0 |
0 |
T10 |
500917 |
500784 |
0 |
0 |
T11 |
3841 |
3101 |
0 |
0 |
T16 |
1813 |
1669 |
0 |
0 |
T17 |
3508 |
2848 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375708731 |
50907228 |
0 |
0 |
T1 |
120543 |
763401 |
0 |
0 |
T2 |
3451 |
0 |
0 |
0 |
T3 |
356849 |
0 |
0 |
0 |
T4 |
505 |
8 |
0 |
0 |
T5 |
1583 |
57 |
0 |
0 |
T6 |
352472 |
68591 |
0 |
0 |
T10 |
500917 |
0 |
0 |
0 |
T11 |
3841 |
0 |
0 |
0 |
T13 |
0 |
524288 |
0 |
0 |
T16 |
1813 |
0 |
0 |
0 |
T17 |
3508 |
0 |
0 |
0 |
T19 |
0 |
460941 |
0 |
0 |
T20 |
0 |
1815 |
0 |
0 |
T26 |
0 |
41503 |
0 |
0 |
T31 |
0 |
1670 |
0 |
0 |
T38 |
0 |
2674 |
0 |
0 |