Line Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Module :
flash_phy_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T19,T38 |
1 | 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T19,T38 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T2,T3,T4 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805089048 |
6961772 |
0 |
0 |
T2 |
11458 |
175 |
0 |
0 |
T3 |
1118556 |
15932 |
0 |
0 |
T4 |
144262 |
79 |
0 |
0 |
T5 |
495478 |
512 |
0 |
0 |
T6 |
0 |
21181 |
0 |
0 |
T7 |
0 |
8097 |
0 |
0 |
T11 |
2204 |
6 |
0 |
0 |
T12 |
7246 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T16 |
5588 |
0 |
0 |
0 |
T17 |
6754 |
0 |
0 |
0 |
T18 |
432560 |
0 |
0 |
0 |
T19 |
12476 |
500 |
0 |
0 |
T20 |
0 |
108 |
0 |
0 |
T26 |
0 |
20431 |
0 |
0 |
T38 |
0 |
1420 |
0 |
0 |
T42 |
0 |
16 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805089048 |
803354878 |
0 |
0 |
T1 |
457496 |
457308 |
0 |
0 |
T2 |
11458 |
11128 |
0 |
0 |
T3 |
1118556 |
1118250 |
0 |
0 |
T4 |
144262 |
144156 |
0 |
0 |
T11 |
2204 |
2088 |
0 |
0 |
T12 |
7246 |
5930 |
0 |
0 |
T16 |
5588 |
5448 |
0 |
0 |
T17 |
6754 |
5348 |
0 |
0 |
T18 |
432560 |
432392 |
0 |
0 |
T19 |
12476 |
11516 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805089048 |
6961777 |
0 |
0 |
T2 |
11458 |
175 |
0 |
0 |
T3 |
1118556 |
15932 |
0 |
0 |
T4 |
144262 |
79 |
0 |
0 |
T5 |
495478 |
512 |
0 |
0 |
T6 |
0 |
21181 |
0 |
0 |
T7 |
0 |
8097 |
0 |
0 |
T11 |
2204 |
6 |
0 |
0 |
T12 |
7246 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T16 |
5588 |
0 |
0 |
0 |
T17 |
6754 |
0 |
0 |
0 |
T18 |
432560 |
0 |
0 |
0 |
T19 |
12476 |
500 |
0 |
0 |
T20 |
0 |
108 |
0 |
0 |
T26 |
0 |
20431 |
0 |
0 |
T38 |
0 |
1420 |
0 |
0 |
T42 |
0 |
16 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805089049 |
16637441 |
0 |
0 |
T1 |
228748 |
32 |
0 |
0 |
T2 |
11458 |
239 |
0 |
0 |
T3 |
1118556 |
15969 |
0 |
0 |
T4 |
144262 |
111 |
0 |
0 |
T5 |
247739 |
0 |
0 |
0 |
T6 |
0 |
10210 |
0 |
0 |
T7 |
0 |
8097 |
0 |
0 |
T11 |
2204 |
38 |
0 |
0 |
T12 |
7246 |
192 |
0 |
0 |
T16 |
5588 |
32 |
0 |
0 |
T17 |
6754 |
116 |
0 |
0 |
T18 |
432560 |
32 |
0 |
0 |
T19 |
12476 |
692 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
0 |
20431 |
0 |
0 |
T38 |
0 |
404 |
0 |
0 |
T42 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T19,T38 |
1 | 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T19,T38 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T2,T3,T4 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
3257786 |
0 |
0 |
T2 |
5729 |
141 |
0 |
0 |
T3 |
559278 |
8014 |
0 |
0 |
T4 |
72131 |
55 |
0 |
0 |
T5 |
247739 |
512 |
0 |
0 |
T6 |
0 |
10971 |
0 |
0 |
T11 |
1102 |
6 |
0 |
0 |
T12 |
3623 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T16 |
2794 |
0 |
0 |
0 |
T17 |
3377 |
0 |
0 |
0 |
T18 |
216280 |
0 |
0 |
0 |
T19 |
6238 |
300 |
0 |
0 |
T20 |
0 |
104 |
0 |
0 |
T38 |
0 |
1016 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
401677439 |
0 |
0 |
T1 |
228748 |
228654 |
0 |
0 |
T2 |
5729 |
5564 |
0 |
0 |
T3 |
559278 |
559125 |
0 |
0 |
T4 |
72131 |
72078 |
0 |
0 |
T11 |
1102 |
1044 |
0 |
0 |
T12 |
3623 |
2965 |
0 |
0 |
T16 |
2794 |
2724 |
0 |
0 |
T17 |
3377 |
2674 |
0 |
0 |
T18 |
216280 |
216196 |
0 |
0 |
T19 |
6238 |
5758 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
3257788 |
0 |
0 |
T2 |
5729 |
141 |
0 |
0 |
T3 |
559278 |
8014 |
0 |
0 |
T4 |
72131 |
55 |
0 |
0 |
T5 |
247739 |
512 |
0 |
0 |
T6 |
0 |
10971 |
0 |
0 |
T11 |
1102 |
6 |
0 |
0 |
T12 |
3623 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T16 |
2794 |
0 |
0 |
0 |
T17 |
3377 |
0 |
0 |
0 |
T18 |
216280 |
0 |
0 |
0 |
T19 |
6238 |
300 |
0 |
0 |
T20 |
0 |
104 |
0 |
0 |
T38 |
0 |
1016 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
8418637 |
0 |
0 |
T1 |
228748 |
32 |
0 |
0 |
T2 |
5729 |
205 |
0 |
0 |
T3 |
559278 |
8051 |
0 |
0 |
T4 |
72131 |
87 |
0 |
0 |
T11 |
1102 |
38 |
0 |
0 |
T12 |
3623 |
192 |
0 |
0 |
T16 |
2794 |
32 |
0 |
0 |
T17 |
3377 |
116 |
0 |
0 |
T18 |
216280 |
32 |
0 |
0 |
T19 |
6238 |
492 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T69,T107,T108 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T19,T38,T24 |
1 | 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T38,T24 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T2,T3,T4 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
3703986 |
0 |
0 |
T2 |
5729 |
34 |
0 |
0 |
T3 |
559278 |
7918 |
0 |
0 |
T4 |
72131 |
24 |
0 |
0 |
T5 |
247739 |
0 |
0 |
0 |
T6 |
0 |
10210 |
0 |
0 |
T7 |
0 |
8097 |
0 |
0 |
T11 |
1102 |
0 |
0 |
0 |
T12 |
3623 |
0 |
0 |
0 |
T16 |
2794 |
0 |
0 |
0 |
T17 |
3377 |
0 |
0 |
0 |
T18 |
216280 |
0 |
0 |
0 |
T19 |
6238 |
200 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
0 |
20431 |
0 |
0 |
T38 |
0 |
404 |
0 |
0 |
T42 |
0 |
16 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
401677439 |
0 |
0 |
T1 |
228748 |
228654 |
0 |
0 |
T2 |
5729 |
5564 |
0 |
0 |
T3 |
559278 |
559125 |
0 |
0 |
T4 |
72131 |
72078 |
0 |
0 |
T11 |
1102 |
1044 |
0 |
0 |
T12 |
3623 |
2965 |
0 |
0 |
T16 |
2794 |
2724 |
0 |
0 |
T17 |
3377 |
2674 |
0 |
0 |
T18 |
216280 |
216196 |
0 |
0 |
T19 |
6238 |
5758 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544524 |
3703989 |
0 |
0 |
T2 |
5729 |
34 |
0 |
0 |
T3 |
559278 |
7918 |
0 |
0 |
T4 |
72131 |
24 |
0 |
0 |
T5 |
247739 |
0 |
0 |
0 |
T6 |
0 |
10210 |
0 |
0 |
T7 |
0 |
8097 |
0 |
0 |
T11 |
1102 |
0 |
0 |
0 |
T12 |
3623 |
0 |
0 |
0 |
T16 |
2794 |
0 |
0 |
0 |
T17 |
3377 |
0 |
0 |
0 |
T18 |
216280 |
0 |
0 |
0 |
T19 |
6238 |
200 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
0 |
20431 |
0 |
0 |
T38 |
0 |
404 |
0 |
0 |
T42 |
0 |
16 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402544525 |
8218804 |
0 |
0 |
T2 |
5729 |
34 |
0 |
0 |
T3 |
559278 |
7918 |
0 |
0 |
T4 |
72131 |
24 |
0 |
0 |
T5 |
247739 |
0 |
0 |
0 |
T6 |
0 |
10210 |
0 |
0 |
T7 |
0 |
8097 |
0 |
0 |
T11 |
1102 |
0 |
0 |
0 |
T12 |
3623 |
0 |
0 |
0 |
T16 |
2794 |
0 |
0 |
0 |
T17 |
3377 |
0 |
0 |
0 |
T18 |
216280 |
0 |
0 |
0 |
T19 |
6238 |
200 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T26 |
0 |
20431 |
0 |
0 |
T38 |
0 |
404 |
0 |
0 |
T42 |
0 |
16 |
0 |
0 |