Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.93	100.00	91.70			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.65	100.00	90.61			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.87	100.00	91.48			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.65	100.00	90.61			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.02	97.64	93.24	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.48			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.08	97.64	93.56	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	458	420	91.70
Logical	458	420	91.70
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	91.81
790-794	83.33

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T38,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T44,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T57
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	805089048	1637617	0	0
ExclusiveOps_A	805089048	803354878	0	0
ExclusiveProgHazard_A	805089048	803354878	0	0
ExclusiveState_A	805089048	803354878	0	0
ForwardCheck_A	805089048	3875515	0	0
IdleCheck_A	805089048	101671166	0	0
MaxBufs_A	2088	2088	0	0
OneHotAlloc_A	805089048	803354878	0	0
OneHotMatch_A	805089048	803354878	0	0
OneHotRspMatch_A	805089048	803354878	0	0
OneHotUpdate_A	805089048	803354878	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	1637617	0	0
T2	11458	81	0	0
T3	1118556	0	0	0
T4	144262	32	0	0
T5	495478	256	0	0
T6	0	1486	0	0
T7	0	11	0	0
T11	2204	3	0	0
T12	7246	0	0	0
T13	0	1	0	0
T16	5588	0	0	0
T17	6754	0	0	0
T18	432560	0	0	0
T19	12476	372	0	0
T20	0	52	0	0
T24	0	27	0	0
T26	0	5898	0	0
T38	0	710	0	0
T42	0	6	0	0
T44	0	714	0	0
T57	0	46	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	3875515	0	0
T2	11458	31	0	0
T3	1118556	15932	0	0
T4	144262	47	0	0
T5	495478	0	0	0
T7	0	16093	0	0
T11	2204	0	0	0
T12	7246	0	0	0
T16	5588	0	0	0
T17	6754	0	0	0
T18	432560	0	0	0
T19	12476	0	0	0
T20	0	12	0	0
T23	0	5	0	0
T24	0	31	0	0
T26	0	30444	0	0
T38	0	710	0	0
T42	0	10	0	0
T44	0	19900	0	0
T57	0	54	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	101671166	0	0
T1	228748	128	0	0
T2	11458	651	0	0
T3	1118556	814450	0	0
T4	144262	254	0	0
T5	247739	0	0	0
T6	0	34749	0	0
T7	0	412397	0	0
T11	2204	143	0	0
T12	7246	768	0	0
T16	5588	128	0	0
T17	6754	462	0	0
T18	432560	128	0	0
T19	12476	1652	0	0
T20	0	8	0	0
T26	0	747081	0	0
T38	0	606	0	0
T42	0	26	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2088	2088	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805089048	803354878	0	0
T1	457496	457308	0	0
T2	11458	11128	0	0
T3	1118556	1118250	0	0
T4	144262	144156	0	0
T11	2204	2088	0	0
T12	7246	5930	0	0
T16	5588	5448	0	0
T17	6754	5348	0	0
T18	432560	432392	0	0
T19	12476	11516	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	458	415	90.61
Logical	458	415	90.61
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	90.71
790-794	83.33

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T6,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T19,T6
0	1	Covered	T2,T8,T209
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T19,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T19,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T55,T56
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T19,T6
0	0	1	Covered	T2,T19,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	402544524	932335	0	0
ExclusiveOps_A	402544524	401677439	0	0
ExclusiveProgHazard_A	402544524	401677439	0	0
ExclusiveState_A	402544524	401677439	0	0
ForwardCheck_A	402544524	1973806	0	0
IdleCheck_A	402544524	49844384	0	0
MaxBufs_A	1044	1044	0	0
OneHotAlloc_A	402544524	401677439	0	0
OneHotMatch_A	402544524	401677439	0	0
OneHotRspMatch_A	402544524	401677439	0	0
OneHotUpdate_A	402544524	401677439	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	932335	0	0
T2	5729	14	0	0
T3	559278	0	0	0
T4	72131	9	0	0
T5	247739	0	0	0
T6	0	599	0	0
T7	0	11	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	148	0	0
T24	0	27	0	0
T26	0	5898	0	0
T38	0	202	0	0
T42	0	6	0	0
T44	0	714	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	1973806	0	0
T2	5729	9	0	0
T3	559278	7918	0	0
T4	72131	15	0	0
T5	247739	0	0	0
T7	0	8086	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	0	0	0
T20	0	4	0	0
T24	0	31	0	0
T26	0	14533	0	0
T38	0	202	0	0
T42	0	10	0	0
T44	0	9216	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	49844384	0	0
T2	5729	76	0	0
T3	559278	403818	0	0
T4	72131	39	0	0
T5	247739	0	0	0
T6	0	34749	0	0
T7	0	412397	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	356	0	0
T20	0	8	0	0
T26	0	747081	0	0
T38	0	606	0	0
T42	0	26	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	458	419	91.48
Logical	458	419	91.48
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	91.59
790-794	83.33

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T38,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T44,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T57
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	402544524	705282	0	0
ExclusiveOps_A	402544524	401677439	0	0
ExclusiveProgHazard_A	402544524	401677439	0	0
ExclusiveState_A	402544524	401677439	0	0
ForwardCheck_A	402544524	1901709	0	0
IdleCheck_A	402544524	51826782	0	0
MaxBufs_A	1044	1044	0	0
OneHotAlloc_A	402544524	401677439	0	0
OneHotMatch_A	402544524	401677439	0	0
OneHotRspMatch_A	402544524	401677439	0	0
OneHotUpdate_A	402544524	401677439	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	705282	0	0
T2	5729	67	0	0
T3	559278	0	0	0
T4	72131	23	0	0
T5	247739	256	0	0
T6	0	887	0	0
T11	1102	3	0	0
T12	3623	0	0	0
T13	0	1	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	224	0	0
T20	0	52	0	0
T38	0	508	0	0
T57	0	46	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	1901709	0	0
T2	5729	22	0	0
T3	559278	8014	0	0
T4	72131	32	0	0
T5	247739	0	0	0
T7	0	8007	0	0
T11	1102	0	0	0
T12	3623	0	0	0
T16	2794	0	0	0
T17	3377	0	0	0
T18	216280	0	0	0
T19	6238	0	0	0
T20	0	8	0	0
T23	0	5	0	0
T26	0	15911	0	0
T38	0	508	0	0
T44	0	10684	0	0
T57	0	54	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	51826782	0	0
T1	228748	128	0	0
T2	5729	575	0	0
T3	559278	410632	0	0
T4	72131	215	0	0
T11	1102	143	0	0
T12	3623	768	0	0
T16	2794	128	0	0
T17	3377	462	0	0
T18	216280	128	0	0
T19	6238	1296	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402544524	401677439	0	0
T1	228748	228654	0	0
T2	5729	5564	0	0
T3	559278	559125	0	0
T4	72131	72078	0	0
T11	1102	1044	0	0
T12	3623	2965	0	0
T16	2794	2724	0	0
T17	3377	2674	0	0
T18	216280	216196	0	0
T19	6238	5758	0	0