Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18844	1		T66	60		T115	820		T113	68
full_word	3964450	1		T1	8		T3	16584		T4	229

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3983038	1		T1	8		T3	16584		T4	229
auto[TlIntgErrCmd]	83	1		T114	2		T225	5		T228	6
auto[TlIntgErrData]	87	1		T114	4		T225	2		T228	5
auto[TlIntgErrBoth]	86	1		T114	4		T225	2		T228	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3958538	1		T1	8		T3	16584		T4	229
auto[1]	24756	1		T66	78		T115	1148		T113	79

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1019	1		T66	5		T115	45		T113	1
auto[TlIntgErrNone]	partial	auto[1]	17589	1		T66	55		T115	775		T113	67
auto[TlIntgErrNone]	full_word	auto[0]	3957413	1		T1	8		T3	16584		T4	229
auto[TlIntgErrNone]	full_word	auto[1]	7017	1		T66	23		T115	373		T113	12
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T225	2		T228	2		T251	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T114	2		T225	3		T228	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T228	1		T251	1		T347	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T251	1		T349	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1		T114	3		T228	2		T227	1
auto[TlIntgErrData]	partial	auto[1]	36	1		T114	1		T225	2		T228	3
auto[TlIntgErrData]	full_word	auto[0]	9	1		T227	2		T349	1		T345	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T251	1		T351	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T114	2		T228	1		T251	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T114	2		T225	2		T228	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T349	1		T257	1		T345	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24192732	1		T1	418		T2	17		T3	7821
full_word	7704200	1		T1	189		T2	1		T3	33784

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31896652	1		T1	607		T2	18		T3	41605
auto[TlIntgErrCmd]	117	1		T114	6		T225	3		T228	10
auto[TlIntgErrData]	84	1		T114	2		T225	3		T228	7
auto[TlIntgErrBoth]	79	1		T114	2		T225	4		T228	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27539004	1		T1	511		T2	17		T3	34658
auto[1]	4357928	1		T1	96		T2	1		T3	6947

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23532921	1		T1	399		T2	16		T3	5337
auto[TlIntgErrNone]	partial	auto[1]	659559	1		T1	19		T2	1		T3	2484
auto[TlIntgErrNone]	full_word	auto[0]	4005959	1		T1	112		T2	1		T3	29321
auto[TlIntgErrNone]	full_word	auto[1]	3698213	1		T1	77		T3	4463		T4	865
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T114	2		T228	2		T227	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T114	4		T225	3		T228	8
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T249	1		T352	1		T353	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T227	1		T251	1		T257	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T114	1		T225	1		T228	2
auto[TlIntgErrData]	partial	auto[1]	36	1		T225	2		T228	5		T227	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T114	1		T250	1		T345	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T249	1		T346	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T114	2		T225	2		T228	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1		T225	2		T228	1		T227	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T227	1		T250	1		T257	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T228	1		T349	1		T257	1