Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1581295700	1577942668	0	0
CheckNGreaterZero_A	4168	4168	0	0
GntImpliesReady_A	1581295700	394180943	0	0
GntImpliesValid_A	1581295700	394180943	0	0
GrantKnown_A	1581295700	1577942668	0	0
IdxKnown_A	1581295700	1577942668	0	0
IndexIsCorrect_A	1581295700	394180943	0	0
NoReadyValidNoGrant_A	1581295700	174773151	0	0
Priority_A	1581295700	418003926	0	0
ReadyAndValidImplyGrant_A	1581295700	394180943	0	0
ReqAndReadyImplyGrant_A	1581295700	394180943	0	0
ReqImpliesValid_A	1581295700	418003926	0	0
ValidKnown_A	1581295700	1577942668	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	1577942668	0	0
T1	8116	7648	0	0
T2	6180	5836	0	0
T3	780828	780420	0	0
T4	291380	291172	0	0
T5	1522860	1455224	0	0
T6	237924	237416	0	0
T16	779000	778972	0	0
T17	7064	6496	0	0
T18	14576	12032	0	0
T19	13100	12472	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4168	4168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	394180943	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	88472	0	0
T4	291380	138002	0	0
T5	1522860	329724	0	0
T6	237924	50382	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	1862	0	0
T27	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	394180943	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	88472	0	0
T4	291380	138002	0	0
T5	1522860	329724	0	0
T6	237924	50382	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	1862	0	0
T27	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	1577942668	0	0
T1	8116	7648	0	0
T2	6180	5836	0	0
T3	780828	780420	0	0
T4	291380	291172	0	0
T5	1522860	1455224	0	0
T6	237924	237416	0	0
T16	779000	778972	0	0
T17	7064	6496	0	0
T18	14576	12032	0	0
T19	13100	12472	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	1577942668	0	0
T1	8116	7648	0	0
T2	6180	5836	0	0
T3	780828	780420	0	0
T4	291380	291172	0	0
T5	1522860	1455224	0	0
T6	237924	237416	0	0
T16	779000	778972	0	0
T17	7064	6496	0	0
T18	14576	12032	0	0
T19	13100	12472	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	394180943	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	88472	0	0
T4	291380	138002	0	0
T5	1522860	329724	0	0
T6	237924	50382	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	1862	0	0
T27	0	8	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	174773151	0	0
T1	8116	1074	0	0
T2	6180	256	0	0
T3	780828	237638	0	0
T4	291380	1256	0	0
T5	1522860	84584	0	0
T6	237924	83310	0	0
T16	779000	3392	0	0
T17	7064	936	0	0
T18	14576	1144	0	0
T19	13100	974	0	0
T20	0	440	0	0
T26	0	282	0	0
T27	0	10	0	0
T34	0	48	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	418003926	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	91960	0	0
T4	291380	138080	0	0
T5	1522860	329724	0	0
T6	237924	61370	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	2036	0	0
T27	0	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	394180943	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	88472	0	0
T4	291380	138002	0	0
T5	1522860	329724	0	0
T6	237924	50382	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	1862	0	0
T27	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	394180943	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	88472	0	0
T4	291380	138002	0	0
T5	1522860	329724	0	0
T6	237924	50382	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	1862	0	0
T27	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	418003926	0	0
T1	8116	474	0	0
T2	6180	64	0	0
T3	780828	91960	0	0
T4	291380	138080	0	0
T5	1522860	329724	0	0
T6	237924	61370	0	0
T16	779000	1990354	0	0
T17	7064	420	0	0
T18	14576	300	0	0
T19	13100	728	0	0
T20	0	7260	0	0
T26	0	2036	0	0
T27	0	10	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1581295700	1577942668	0	0
T1	8116	7648	0	0
T2	6180	5836	0	0
T3	780828	780420	0	0
T4	291380	291172	0	0
T5	1522860	1455224	0	0
T6	237924	237416	0	0
T16	779000	778972	0	0
T17	7064	6496	0	0
T18	14576	12032	0	0
T19	13100	12472	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395323925	394485667	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	395323925	106225375	0	0
GntImpliesValid_A	395323925	106225375	0	0
GrantKnown_A	395323925	394485667	0	0
IdxKnown_A	395323925	394485667	0	0
IndexIsCorrect_A	395323925	106225375	0	0
NoReadyValidNoGrant_A	395323925	45618254	0	0
Priority_A	395323925	112045074	0	0
ReadyAndValidImplyGrant_A	395323925	106225375	0	0
ReqAndReadyImplyGrant_A	395323925	106225375	0	0
ReqImpliesValid_A	395323925	112045074	0	0
ValidKnown_A	395323925	394485667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	45618254	0	0
T1	2029	463	0	0
T2	1545	128	0	0
T3	195207	59710	0	0
T4	72845	440	0	0
T5	380715	42292	0	0
T6	59481	29881	0	0
T16	194750	1696	0	0
T17	1766	416	0	0
T18	3644	572	0	0
T19	3275	428	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	112045074	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22897	0	0
T4	72845	67437	0	0
T5	380715	164862	0	0
T6	59481	20113	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	112045074	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22897	0	0
T4	72845	67437	0	0
T5	380715	164862	0	0
T6	59481	20113	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395323925	394485667	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	395323925	106225375	0	0
GntImpliesValid_A	395323925	106225375	0	0
GrantKnown_A	395323925	394485667	0	0
IdxKnown_A	395323925	394485667	0	0
IndexIsCorrect_A	395323925	106225375	0	0
NoReadyValidNoGrant_A	395323925	45618254	0	0
Priority_A	395323925	112045074	0	0
ReadyAndValidImplyGrant_A	395323925	106225375	0	0
ReqAndReadyImplyGrant_A	395323925	106225375	0	0
ReqImpliesValid_A	395323925	112045074	0	0
ValidKnown_A	395323925	394485667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	45618254	0	0
T1	2029	463	0	0
T2	1545	128	0	0
T3	195207	59710	0	0
T4	72845	440	0	0
T5	380715	42292	0	0
T6	59481	29881	0	0
T16	194750	1696	0	0
T17	1766	416	0	0
T18	3644	572	0	0
T19	3275	428	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	112045074	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22897	0	0
T4	72845	67437	0	0
T5	380715	164862	0	0
T6	59481	20113	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	106225375	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22125	0	0
T4	72845	67414	0	0
T5	380715	164862	0	0
T6	59481	16740	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	112045074	0	0
T1	2029	145	0	0
T2	1545	32	0	0
T3	195207	22897	0	0
T4	72845	67437	0	0
T5	380715	164862	0	0
T6	59481	20113	0	0
T16	194750	102593	0	0
T17	1766	191	0	0
T18	3644	150	0	0
T19	3275	211	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395323925	394485667	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	395323925	90865103	0	0
GntImpliesValid_A	395323925	90865103	0	0
GrantKnown_A	395323925	394485667	0	0
IdxKnown_A	395323925	394485667	0	0
IndexIsCorrect_A	395323925	90865103	0	0
NoReadyValidNoGrant_A	395323925	41768329	0	0
Priority_A	395323925	96956888	0	0
ReadyAndValidImplyGrant_A	395323925	90865103	0	0
ReqAndReadyImplyGrant_A	395323925	90865103	0	0
ReqImpliesValid_A	395323925	96956888	0	0
ValidKnown_A	395323925	394485667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865103	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865103	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865103	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	41768329	0	0
T1	2029	74	0	0
T2	1545	0	0	0
T3	195207	59109	0	0
T4	72845	188	0	0
T5	380715	0	0	0
T6	59481	11774	0	0
T16	194750	0	0	0
T17	1766	52	0	0
T18	3644	0	0	0
T19	3275	59	0	0
T20	0	220	0	0
T26	0	141	0	0
T27	0	5	0	0
T34	0	24	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	96956888	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	23083	0	0
T4	72845	1603	0	0
T5	380715	0	0	0
T6	59481	10572	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	1018	0	0
T27	0	5	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865103	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865103	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	96956888	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	23083	0	0
T4	72845	1603	0	0
T5	380715	0	0	0
T6	59481	10572	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	1018	0	0
T27	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395323925	394485667	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	395323925	90865090	0	0
GntImpliesValid_A	395323925	90865090	0	0
GrantKnown_A	395323925	394485667	0	0
IdxKnown_A	395323925	394485667	0	0
IndexIsCorrect_A	395323925	90865090	0	0
NoReadyValidNoGrant_A	395323925	41768314	0	0
Priority_A	395323925	96956890	0	0
ReadyAndValidImplyGrant_A	395323925	90865090	0	0
ReqAndReadyImplyGrant_A	395323925	90865090	0	0
ReqImpliesValid_A	395323925	96956890	0	0
ValidKnown_A	395323925	394485667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865090	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865090	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865090	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	41768314	0	0
T1	2029	74	0	0
T2	1545	0	0	0
T3	195207	59109	0	0
T4	72845	188	0	0
T5	380715	0	0	0
T6	59481	11774	0	0
T16	194750	0	0	0
T17	1766	52	0	0
T18	3644	0	0	0
T19	3275	59	0	0
T20	0	220	0	0
T26	0	141	0	0
T27	0	5	0	0
T34	0	24	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	96956890	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	23083	0	0
T4	72845	1603	0	0
T5	380715	0	0	0
T6	59481	10572	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	1018	0	0
T27	0	5	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865090	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	90865090	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	22111	0	0
T4	72845	1587	0	0
T5	380715	0	0	0
T6	59481	8451	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	931	0	0
T27	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	96956890	0	0
T1	2029	92	0	0
T2	1545	0	0	0
T3	195207	23083	0	0
T4	72845	1603	0	0
T5	380715	0	0	0
T6	59481	10572	0	0
T16	194750	892584	0	0
T17	1766	19	0	0
T18	3644	0	0	0
T19	3275	153	0	0
T20	0	3630	0	0
T26	0	1018	0	0
T27	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0