Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	98.04	100.00	93.85		100.00	96.36	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	98.04	100.00	93.85		100.00	96.36	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.85	100.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	97.75	90.57		100.00	93.48	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	93.85	95.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.76	96.63	85.85		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T170,T8,T9
1	0	Covered	T170,T8,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T170,T8,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T170,T8,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T26,T20

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T26,T20

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T26,T20

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T26,T20

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T26,T20

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T16,T19
1	Covered	T1,T5,T17

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T4,T5

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T4,T5,T16

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T1,T4,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T5,T17

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T5,T17

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T5,T17
StCalcMask	237	Covered	T1,T5,T17
StCalcPlainEcc	215	Covered	T1,T4,T5
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T5
StPostPack	218	Covered	T4,T26,T20
StPrePack	195	Covered	T4,T26,T20
StReqFlash	237	Covered	T1,T4,T5
StScrambleData	244	Covered	T1,T5,T17
StWaitFlash	270	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T5,T17
StCalcMask->StScrambleData	244	Covered	T1,T5,T17
StCalcPlainEcc->StCalcMask	237	Covered	T1,T5,T17
StCalcPlainEcc->StReqFlash	237	Covered	T4,T16,T19
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T4,T5
StIdle->StPrePack	195	Covered	T4,T26,T20
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T5
StPackData->StPostPack	218	Covered	T4,T26,T20
StPostPack->StCalcPlainEcc	231	Covered	T4,T26,T20
StPrePack->StPackData	205	Covered	T4,T26,T20
StReqFlash->StIdle	273	Covered	T4,T5,T16
StReqFlash->StWaitFlash	270	Covered	T1,T4,T5
StScrambleData->StCalcEcc	252	Covered	T1,T5,T17
StWaitFlash->StIdle	280	Covered	T1,T4,T5

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T5,T17
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T16,T19
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T5,T17
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T5,T17
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T5,T17
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T5,T17
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T4,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T5
0	0	1	-	-	Covered	T1,T5,T17
0	0	0	1	-	Covered	T1,T5,T17
0	0	0	0	1	Covered	T1,T4,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	790647850	2433009	0	0
PostPackRule_A	790647850	1887	0	0
PrePackRule_A	790647850	1346	0	0
WidthCheck_A	2084	2084	0	0
u_state_regs_A	790647850	788971334	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790647850	2433009	0	0
T1	2029	1	0	0
T2	1545	0	0	0
T3	195207	0	0	0
T4	145690	5	0	0
T5	761430	343	0	0
T6	118962	0	0	0
T10	0	32774	0	0
T11	0	32800	0	0
T16	389500	1520	0	0
T17	3532	1	0	0
T18	7288	0	0	0
T19	6550	3	0	0
T20	0	19	0	0
T21	0	32	0	0
T26	3975	4	0	0
T27	942	0	0	0
T28	0	689	0	0
T34	0	1	0	0
T38	1988	0	0	0
T61	0	1	0	0
T95	0	66	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790647850	1887	0	0
T4	145690	4	0	0
T5	761430	0	0	0
T6	118962	0	0	0
T10	0	7	0	0
T16	389500	0	0	0
T17	3532	0	0	0
T18	7288	0	0	0
T19	6550	0	0	0
T20	0	9	0	0
T25	0	39	0	0
T26	7950	3	0	0
T27	1884	0	0	0
T38	3976	0	0	0
T69	0	47	0	0
T95	0	73	0	0
T110	0	2	0	0
T196	0	7	0	0
T200	0	25	0	0
T215	0	3	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790647850	1346	0	0
T4	145690	3	0	0
T5	761430	0	0	0
T6	118962	0	0	0
T10	0	3	0	0
T16	389500	0	0	0
T17	3532	0	0	0
T18	7288	0	0	0
T19	6550	0	0	0
T20	0	8	0	0
T25	0	23	0	0
T26	7950	4	0	0
T27	1884	0	0	0
T38	3976	0	0	0
T69	0	26	0	0
T95	0	58	0	0
T110	0	1	0	0
T196	0	6	0	0
T200	0	23	0	0
T215	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2084	2084	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790647850	788971334	0	0
T1	4058	3824	0	0
T2	3090	2918	0	0
T3	390414	390210	0	0
T4	145690	145586	0	0
T5	761430	727612	0	0
T6	118962	118708	0	0
T16	389500	389486	0	0
T17	3532	3248	0	0
T18	7288	6016	0	0
T19	6550	6236	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T170,T8,T9
1	0	Covered	T170,T8,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T170,T8,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T170,T8,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T4,T26,T20

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T16

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T26,T20

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T26,T20

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T16

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T4,T5,T16

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T16
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T26,T20

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T26,T20

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T16,T19
1	Covered	T5,T17,T34

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T4,T5,T16

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T4,T5,T16

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T16

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T17,T34
1	1	Covered	T5,T17,T34

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T17,T34
1	1	Covered	T5,T17,T34

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T16
1	1	0	Covered	T4,T5,T16
1	1	1	Covered	T4,T5,T16

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T17,T34
StCalcMask	237	Covered	T5,T17,T34
StCalcPlainEcc	215	Covered	T4,T5,T16
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T16
StPostPack	218	Covered	T4,T26,T20
StPrePack	195	Covered	T4,T26,T20
StReqFlash	237	Covered	T4,T5,T16
StScrambleData	244	Covered	T5,T17,T34
StWaitFlash	270	Covered	T4,T5,T16

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T17,T34
StCalcMask->StScrambleData	244	Covered	T5,T17,T34
StCalcPlainEcc->StCalcMask	237	Covered	T5,T17,T34
StCalcPlainEcc->StReqFlash	237	Covered	T4,T16,T19
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T4,T5,T16
StIdle->StPrePack	195	Covered	T4,T26,T20
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T16
StPackData->StPostPack	218	Covered	T4,T26,T20
StPostPack->StCalcPlainEcc	231	Covered	T4,T26,T20
StPrePack->StPackData	205	Covered	T4,T26,T20
StReqFlash->StIdle	273	Covered	T4,T5,T16
StReqFlash->StWaitFlash	270	Covered	T4,T5,T16
StScrambleData->StCalcEcc	252	Covered	T5,T17,T34
StWaitFlash->StIdle	280	Covered	T4,T5,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T16
0	0	1	Covered	T4,T5,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T16
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T16
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T16
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T16
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T17,T34
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T16,T19
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T17,T34
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T17,T34
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T17,T34
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T17,T34
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T34
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T16
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T16
0	0	1	-	-	Covered	T5,T17,T34
0	0	0	1	-	Covered	T5,T17,T34
0	0	0	0	1	Covered	T4,T5,T16
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	395323925	1245208	0	0
PostPackRule_A	395323925	945	0	0
PrePackRule_A	395323925	660	0	0
WidthCheck_A	1042	1042	0	0
u_state_regs_A	395323925	394485667	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	1245208	0	0
T4	72845	2	0	0
T5	380715	343	0	0
T6	59481	0	0	0
T16	194750	803	0	0
T17	1766	1	0	0
T18	3644	0	0	0
T19	3275	1	0	0
T20	0	7	0	0
T21	0	32	0	0
T26	3975	1	0	0
T27	942	0	0	0
T34	0	1	0	0
T38	1988	0	0	0
T61	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	945	0	0
T4	72845	1	0	0
T5	380715	0	0	0
T6	59481	0	0	0
T10	0	4	0	0
T16	194750	0	0	0
T17	1766	0	0	0
T18	3644	0	0	0
T19	3275	0	0	0
T20	0	3	0	0
T25	0	22	0	0
T26	3975	1	0	0
T27	942	0	0	0
T38	1988	0	0	0
T69	0	25	0	0
T95	0	43	0	0
T110	0	1	0	0
T196	0	2	0	0
T200	0	25	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	660	0	0
T4	72845	1	0	0
T5	380715	0	0	0
T6	59481	0	0	0
T10	0	1	0	0
T16	194750	0	0	0
T17	1766	0	0	0
T18	3644	0	0	0
T19	3275	0	0	0
T20	0	2	0	0
T25	0	8	0	0
T26	3975	1	0	0
T27	942	0	0	0
T38	1988	0	0	0
T69	0	15	0	0
T95	0	27	0	0
T110	0	1	0	0
T196	0	1	0	0
T200	0	15	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T16

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T16

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T22
1	0	Covered	T8,T9,T22

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T8,T9,T22

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T22
1	0	Covered	T1,T3,T4

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T16

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T4,T26,T20

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T4,T16

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T16

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T16
1	1	Covered	T4,T26,T20

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T26,T20

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T4,T16

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T1,T4,T16

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T19
1	0	Covered	T1,T4,T16
1	1	Covered	T4,T26,T20

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T26,T20

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T16,T19
1	Covered	T1,T19,T10

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T16,T26
1	Covered	T1,T4,T16

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T16,T26
1	Covered	T4,T16,T26

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T26
1	1	Covered	T1,T4,T16

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T19,T10
1	1	Covered	T1,T19,T10

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T19,T10
1	1	Covered	T1,T19,T10

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T16
1	1	0	Covered	T1,T4,T16
1	1	1	Covered	T1,T4,T16

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T16

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T19,T40
StCalcMask	237	Covered	T1,T19,T40
StCalcPlainEcc	215	Covered	T1,T4,T16
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T16
StPostPack	218	Covered	T4,T26,T20
StPrePack	195	Covered	T4,T26,T20
StReqFlash	237	Covered	T1,T4,T16
StScrambleData	244	Covered	T1,T19,T40
StWaitFlash	270	Covered	T1,T4,T16

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T19,T40
StCalcMask->StScrambleData	244	Covered	T1,T19,T40
StCalcPlainEcc->StCalcMask	237	Covered	T1,T19,T40
StCalcPlainEcc->StReqFlash	237	Covered	T4,T16,T19
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T4,T16
StIdle->StPrePack	195	Covered	T4,T26,T20
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T16
StPackData->StPostPack	218	Covered	T4,T26,T20
StPostPack->StCalcPlainEcc	231	Covered	T4,T26,T20
StPrePack->StPackData	205	Covered	T4,T26,T20
StReqFlash->StIdle	273	Covered	T4,T16,T26
StReqFlash->StWaitFlash	270	Covered	T1,T4,T16
StScrambleData->StCalcEcc	252	Covered	T1,T19,T40
StWaitFlash->StIdle	280	Covered	T1,T4,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T16
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T16
0	0	1	Covered	T1,T4,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T26,T20
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T19,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T16,T19
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T19,T10
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T19,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T19,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T19,T10
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T4,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T16,T26
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T16,T26
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T16,T26
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T16
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T16
0	0	1	-	-	Covered	T1,T19,T10
0	0	0	1	-	Covered	T1,T19,T10
0	0	0	0	1	Covered	T1,T4,T16
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	395323925	1187801	0	0
PostPackRule_A	395323925	942	0	0
PrePackRule_A	395323925	686	0	0
WidthCheck_A	1042	1042	0	0
u_state_regs_A	395323925	394485667	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	1187801	0	0
T1	2029	1	0	0
T2	1545	0	0	0
T3	195207	0	0	0
T4	72845	3	0	0
T5	380715	0	0	0
T6	59481	0	0	0
T10	0	32774	0	0
T11	0	32800	0	0
T16	194750	717	0	0
T17	1766	0	0	0
T18	3644	0	0	0
T19	3275	2	0	0
T20	0	12	0	0
T26	0	3	0	0
T28	0	689	0	0
T95	0	66	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	942	0	0
T4	72845	3	0	0
T5	380715	0	0	0
T6	59481	0	0	0
T10	0	3	0	0
T16	194750	0	0	0
T17	1766	0	0	0
T18	3644	0	0	0
T19	3275	0	0	0
T20	0	6	0	0
T25	0	17	0	0
T26	3975	2	0	0
T27	942	0	0	0
T38	1988	0	0	0
T69	0	22	0	0
T95	0	30	0	0
T110	0	1	0	0
T196	0	5	0	0
T215	0	3	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	686	0	0
T4	72845	2	0	0
T5	380715	0	0	0
T6	59481	0	0	0
T10	0	2	0	0
T16	194750	0	0	0
T17	1766	0	0	0
T18	3644	0	0	0
T19	3275	0	0	0
T20	0	6	0	0
T25	0	15	0	0
T26	3975	3	0	0
T27	942	0	0	0
T38	1988	0	0	0
T69	0	11	0	0
T95	0	31	0	0
T196	0	5	0	0
T200	0	8	0	0
T215	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0