Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_phy_rd
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.82 100.00 91.27 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd 97.71 100.00 90.83 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd 97.71 100.00 90.83 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.71 100.00 90.83 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.03 97.64 93.32 100.00 99.37 94.83


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 97.75 90.57 100.00 93.48 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg 100.00 100.00
u_addr_xor_storage 96.53 100.00 86.11 100.00 100.00
u_bus_inv_data_intg 0.00 0.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 93.75 100.00 80.56 94.44 100.00
u_plain_enc 100.00 100.00
u_prim_buf_data_xor_out 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 97.44 100.00 87.18 100.00 100.00 100.00
u_rsp_order_fifo 97.44 100.00 87.18 100.00 100.00 100.00
u_valid_random 92.50 92.31 97.69 100.00 80.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.71 100.00 90.83 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.03 97.64 93.32 100.00 99.37 94.83


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.76 96.63 85.85 100.00 91.30 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg 100.00 100.00
u_addr_xor_storage 96.53 100.00 86.11 100.00 100.00
u_bus_inv_data_intg 0.00 0.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 93.75 100.00 80.56 94.44 100.00
u_plain_enc 100.00 100.00
u_prim_buf_data_xor_out 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 97.44 100.00 87.18 100.00 100.00 100.00
u_rsp_order_fifo 97.44 100.00 87.18 100.00 100.00 100.00
u_valid_random 92.50 92.31 97.69 100.00 80.00

Line Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23211100.00
ALWAYS25744100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
ALWAYS3601212100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
ALWAYS60066100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61411100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
ALWAYS67088100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN78711100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN80011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
137 1 1
140 4 4
141 4 4
146 4 4
152 1 1
154 3 3
186 1 1
193 4 4
194 4 4
196 4 4
212 4 4
218 4 4
222 4 4
229 1 1
232 1 1
257 1 1
258 1 1
259 1 1
260 1 1
MISSING_ELSE
291 1 1
292 1 1
302 1 1
305 1 1
308 1 1
326 1 1
331 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
MISSING_ELSE
377 1 1
382 1 1
393 1 1
399 1 1
407 1 1
428 1 1
432 1 1
442 1 1
445 1 1
451 1 1
456 1 1
459 1 1
491 1 1
494 1 1
497 1 1
501 1 1
503 1 1
504 1 1
505 1 1
513 1 1
521 1 1
523 1 1
597 1 1
598 1 1
600 1 1
601 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
614 1 1
617 1 1
624 1 1
628 1 1
636 1 1
654 1 1
659 1 1
664 4 4
670 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
MISSING_ELSE
683 1 1
704 1 1
724 1 1
736 1 1
738 1 1
744 1 1
745 1 1
747 1 1
751 1 1
762 1 1
775 1 1
787 1 1
790 1 1
794 1 1
797 1 1
800 1 1

Cond Coverage for Module : flash_phy_rd
TotalCoveredPercent
Conditions45841891.27
Logical45841891.27
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
140-79091.21
794100.00
Branch Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 186 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 302 2 2 100.00
TERNARY 451 2 2 100.00
TERNARY 513 3 3 100.00
TERNARY 624 3 3 100.00
TERNARY 628 3 3 100.00
TERNARY 654 3 3 100.00
TERNARY 683 2 2 100.00
TERNARY 736 2 2 100.00
TERNARY 747 2 2 100.00
TERNARY 775 2 2 100.00
TERNARY 167 2 2 100.00
IF 257 3 3 100.00
IF 360 4 4 100.00
IF 600 4 4 100.00
IF 674 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	232	(no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	302	((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T17,T19
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T39,T92
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T4,T6,T19 



	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	736	(data_err_o) ?

Branches:
-1-StatusTests
1 Covered T1,T17,T19
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 790647850 1590447 0 0
ExclusiveOps_A 790647850 788971334 0 0
ExclusiveProgHazard_A 790647850 788971334 0 0
ExclusiveState_A 790647850 788971334 0 0
ForwardCheck_A 790647850 3597746 0 0
IdleCheck_A 790647850 100552040 0 0
MaxBufs_A 2084 2084 0 0
OneHotAlloc_A 790647850 788971334 0 0
OneHotMatch_A 790647850 788971334 0 0
OneHotRspMatch_A 790647850 788971334 0 0
OneHotUpdate_A 790647850 788971334 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 1590447 0 0
T1 4058 49 0 0
T2 3090 0 0 0
T3 390414 13226 0 0
T4 145690 136 0 0
T5 761430 2852 0 0
T6 118962 3611 0 0
T10 0 54 0 0
T16 389500 0 0 0
T17 3532 36 0 0
T18 7288 0 0 0
T19 6550 51 0 0
T20 0 99 0 0
T26 0 51 0 0
T27 0 6 0 0
T39 0 961 0 0
T43 0 290 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 3597746 0 0
T4 145690 169 0 0
T5 761430 0 0 0
T6 118962 16570 0 0
T10 0 78 0 0
T16 389500 0 0 0
T17 3532 0 0 0
T18 7288 0 0 0
T19 6550 32 0 0
T20 0 122 0 0
T21 0 288 0 0
T26 7950 58 0 0
T27 1884 17 0 0
T38 3976 0 0 0
T39 0 19689 0 0
T43 0 342 0 0
T54 0 15 0 0
T61 0 11 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 100552040 0 0
T1 4058 537 0 0
T2 3090 128 0 0
T3 390414 128623 0 0
T4 145690 655 0 0
T5 761430 42292 0 0
T6 118962 55288 0 0
T16 389500 1696 0 0
T17 3532 468 0 0
T18 7288 572 0 0
T19 6550 487 0 0
T20 0 220 0 0
T26 0 141 0 0
T27 0 8 0 0
T34 0 24 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2084 2084 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 790647850 788971334 0 0
T1 4058 3824 0 0
T2 3090 2918 0 0
T3 390414 390210 0 0
T4 145690 145586 0 0
T5 761430 727612 0 0
T6 118962 118708 0 0
T16 389500 389486 0 0
T17 3532 3248 0 0
T18 7288 6016 0 0
T19 6550 6236 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23211100.00
ALWAYS25744100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
ALWAYS3601212100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
ALWAYS60066100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61411100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
ALWAYS67088100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN78711100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN80011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
137 1 1
140 4 4
141 4 4
146 4 4
152 1 1
154 3 3
186 1 1
193 4 4
194 4 4
196 4 4
212 4 4
218 4 4
222 4 4
229 1 1
232 1 1
257 1 1
258 1 1
259 1 1
260 1 1
MISSING_ELSE
291 1 1
292 1 1
302 1 1
305 1 1
308 1 1
326 1 1
331 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
MISSING_ELSE
377 1 1
382 1 1
393 1 1
399 1 1
407 1 1
428 1 1
432 1 1
442 1 1
445 1 1
451 1 1
456 1 1
459 1 1
491 1 1
494 1 1
497 1 1
501 1 1
503 1 1
504 1 1
505 1 1
513 1 1
521 1 1
523 1 1
597 1 1
598 1 1
600 1 1
601 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
614 1 1
617 1 1
624 1 1
628 1 1
636 1 1
654 1 1
659 1 1
664 4 4
670 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
MISSING_ELSE
683 1 1
704 1 1
724 1 1
736 1 1
738 1 1
744 1 1
745 1 1
747 1 1
751 1 1
762 1 1
775 1 1
787 1 1
790 1 1
794 1 1
797 1 1
800 1 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalCoveredPercent
Conditions45841690.83
Logical45841690.83
Non-Logical00
Event00

 LINE       140
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       140
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       140
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       140
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT49,T51,T201
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110CoveredT202
111CoveredT49,T51,T201 

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT49,T51,T201
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110CoveredT202
111CoveredT49,T51,T201 

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT61,T49,T51
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT61,T49,T51 

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT49,T51,T201
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT49,T51,T201 

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       154
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       154
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       154
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       167
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       167
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T3,T4
01Not Covered
10CoveredT1,T2,T3 

 LINE       167
 EXPRESSION (req_o & ack_i & no_match)
             --1--   --2--   ----3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T26,T40
110Not Covered
111CoveredT1,T2,T3 

 LINE       186
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT5,T19,T54
1110111CoveredT1,T3,T4
1111011CoveredT51,T201,T204
1111101Not Covered
1111110CoveredT63,T64,T138
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT5,T17,T54
1110111CoveredT1,T3,T4
1111011CoveredT49,T201,T198
1111101Not Covered
1111110CoveredT63,T64,T138
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT5,T34,T54
1110111CoveredT1,T3,T4
1111011CoveredT49,T51,T201
1111101Not Covered
1111110CoveredT63,T205,T206
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT4,T5,T54
1110111CoveredT1,T3,T4
1111011CoveredT49,T51,T201
1111101Not Covered
1111110CoveredT138,T205,T206
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T63,T64
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T63,T64
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T63,T205
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T138,T205
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T44,T63
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T44,T63
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T44,T63
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T44,T138
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       222
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T19
10CoveredT1,T3,T4
11CoveredT4,T5,T19 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T21,T10
010CoveredT5,T19,T10
100CoveredT4,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T16
11CoveredT5,T19,T10 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T18
11CoveredT5,T21,T10 

 LINE       222
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T17
10CoveredT1,T3,T4
11CoveredT4,T5,T17 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T21,T10
010CoveredT5,T17,T26
100CoveredT4,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T16
11CoveredT5,T17,T26 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T18
11CoveredT5,T21,T10 

 LINE       222
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T34
10CoveredT1,T3,T4
11CoveredT4,T5,T34 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T21,T10
010CoveredT5,T34,T61
100CoveredT4,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T16
11CoveredT5,T34,T61 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T18
11CoveredT5,T21,T10 

 LINE       222
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T21
10CoveredT1,T3,T4
11CoveredT4,T5,T21 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T21,T10
010CoveredT5,T10,T30
100CoveredT4,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T16
11CoveredT5,T10,T30 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T18
11CoveredT5,T21,T10 

 LINE       232
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       239
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT49,T51,T201
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       239
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T6,T27
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       239
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT6,T27,T39
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       239
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT6,T27,T63
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       291
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T26,T40
11CoveredT1,T2,T3 

 LINE       292
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT4,T5,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       302
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       305
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3 

 LINE       308
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       377
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       382
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT14,T15,T59
10CoveredT14,T15,T59
11CoveredT1,T2,T3 

 LINE       393
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       399
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T3,T6
1111CoveredT1,T2,T3 

 LINE       399
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       399
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T26
111CoveredT1,T2,T3 

 LINE       399
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       407
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111Not Covered
110111CoveredT6,T27,T40
111011Not Covered
111101CoveredT1,T3,T4
111110CoveredT3,T39,T63
111111CoveredT1,T2,T3 

 LINE       407
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       428
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T19
11CoveredT1,T2,T3 

 LINE       432
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT4,T5,T16
10CoveredT1,T2,T3
11CoveredT4,T27,T26 

 LINE       432
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T16 

 LINE       442
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT4,T6,T19
10CoveredT1,T2,T3
11CoveredT61,T161,T207 

 LINE       451
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T34,T61 

 LINE       451
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T34,T208
10CoveredT61,T161,T207 

 LINE       456
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT4,T6,T17
10CoveredT1,T2,T3
11CoveredT17,T34,T208 

 LINE       491
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------
-1--2--3-StatusTests
011CoveredT14,T15,T59
101Not Covered
110CoveredT3,T4,T26
111CoveredT1,T2,T3 

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T6,T19
110CoveredT27,T39,T92
111CoveredT1,T2,T3 

 LINE       497
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T27,T26
110CoveredT1,T2,T3
111CoveredT27,T39,T92 

 LINE       501
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT49,T138,T197
111CoveredT4,T6,T19 

 LINE       503
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T19
11CoveredT1,T2,T3 

 LINE       504
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT27,T39,T92 

 LINE       505
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T6,T19 

 LINE       513
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       513
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       513
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T39,T92 

 LINE       521
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T63,T64
11CoveredT4,T6,T19 

 LINE       521
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T39,T92 

 LINE       523
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3 

 LINE       597
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT40,T138,T197
110CoveredT4,T6,T19
111CoveredT1,T2,T3 

 LINE       598
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT5,T17,T34
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       614
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T6,T39
110CoveredT27,T39,T92
111CoveredT1,T2,T3 

 LINE       624
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T19 

 LINE       624
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       628
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T19 

 LINE       628
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT4,T6,T19
1CoveredT1,T2,T3 

 LINE       636
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T6,T19 

 LINE       636
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T19
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       654
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T19 

 LINE       654
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       654
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T19
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       659
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT14,T15,T59
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3 

 LINE       659
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT1,T2,T3
10Not Covered 

 LINE       659
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       677
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT202
10Not Covered 

 LINE       683
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       736
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T34,T61 

 LINE       747
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       775
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       775
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       787
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T2,T3 

 LINE       790
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT17,T34,T61 

 LINE       790
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T34,T61 

 LINE       790
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT161,T207,T49 

 LINE       790
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT202 

 LINE       794
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT17,T34,T61
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 186 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 302 2 2 100.00
TERNARY 451 2 2 100.00
TERNARY 513 3 3 100.00
TERNARY 624 3 3 100.00
TERNARY 628 3 3 100.00
TERNARY 654 3 3 100.00
TERNARY 683 2 2 100.00
TERNARY 736 2 2 100.00
TERNARY 747 2 2 100.00
TERNARY 775 2 2 100.00
TERNARY 167 2 2 100.00
IF 257 3 3 100.00
IF 360 4 4 100.00
IF 600 4 4 100.00
IF 674 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	232	(no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	302	((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T17,T34,T61
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T39,T92
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T4,T6,T19 



	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	736	(data_err_o) ?

Branches:
-1-StatusTests
1 Covered T17,T34,T61
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 395323925 1104295 0 0
ExclusiveOps_A 395323925 394485667 0 0
ExclusiveProgHazard_A 395323925 394485667 0 0
ExclusiveState_A 395323925 394485667 0 0
ForwardCheck_A 395323925 2078464 0 0
IdleCheck_A 395323925 52062429 0 0
MaxBufs_A 1042 1042 0 0
OneHotAlloc_A 395323925 394485667 0 0
OneHotMatch_A 395323925 394485667 0 0
OneHotRspMatch_A 395323925 394485667 0 0
OneHotUpdate_A 395323925 394485667 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 1104295 0 0
T1 2029 39 0 0
T2 1545 0 0 0
T3 195207 6802 0 0
T4 72845 97 0 0
T5 380715 2852 0 0
T6 59481 3611 0 0
T16 194750 0 0 0
T17 1766 28 0 0
T18 3644 0 0 0
T19 3275 42 0 0
T20 0 35 0 0
T26 0 40 0 0
T27 0 6 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 2078464 0 0
T4 72845 121 0 0
T5 380715 0 0 0
T6 59481 9668 0 0
T16 194750 0 0 0
T17 1766 0 0 0
T18 3644 0 0 0
T19 3275 23 0 0
T20 0 44 0 0
T21 0 288 0 0
T26 3975 46 0 0
T27 942 13 0 0
T38 1988 0 0 0
T39 0 9346 0 0
T54 0 15 0 0
T61 0 9 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 52062429 0 0
T1 2029 463 0 0
T2 1545 128 0 0
T3 195207 64208 0 0
T4 72845 467 0 0
T5 380715 42292 0 0
T6 59481 36980 0 0
T16 194750 1696 0 0
T17 1766 416 0 0
T18 3644 572 0 0
T19 3275 428 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23211100.00
ALWAYS25744100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
ALWAYS3601212100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
ALWAYS60066100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61411100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
ALWAYS67088100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN78711100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN80011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
137 1 1
140 4 4
141 4 4
146 4 4
152 1 1
154 3 3
186 1 1
193 4 4
194 4 4
196 4 4
212 4 4
218 4 4
222 4 4
229 1 1
232 1 1
257 1 1
258 1 1
259 1 1
260 1 1
MISSING_ELSE
291 1 1
292 1 1
302 1 1
305 1 1
308 1 1
326 1 1
331 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
MISSING_ELSE
377 1 1
382 1 1
393 1 1
399 1 1
407 1 1
428 1 1
432 1 1
442 1 1
445 1 1
451 1 1
456 1 1
459 1 1
491 1 1
494 1 1
497 1 1
501 1 1
503 1 1
504 1 1
505 1 1
513 1 1
521 1 1
523 1 1
597 1 1
598 1 1
600 1 1
601 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
614 1 1
617 1 1
624 1 1
628 1 1
636 1 1
654 1 1
659 1 1
664 4 4
670 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
MISSING_ELSE
683 1 1
704 1 1
724 1 1
736 1 1
738 1 1
744 1 1
745 1 1
747 1 1
751 1 1
762 1 1
775 1 1
787 1 1
790 1 1
794 1 1
797 1 1
800 1 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalCoveredPercent
Conditions45841690.83
Logical45841690.83
Non-Logical00
Event00

 LINE       140
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       140
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       140
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       140
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       141
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT49,T51,T201
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT49,T51,T201 

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT49,T51,T201
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT49,T51,T201 

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT49,T50,T51
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110CoveredT203
111CoveredT49,T50,T51 

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       146
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT1,T49,T51
10CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       146
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T49,T51 

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       154
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       154
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       154
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       167
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       167
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T3,T4
01Not Covered
10CoveredT1,T2,T3 

 LINE       167
 EXPRESSION (req_o & ack_i & no_match)
             --1--   --2--   ----3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T26,T196
110Not Covered
111CoveredT1,T3,T4 

 LINE       186
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       194
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT208,T140,T209
1110111CoveredT1,T3,T4
1111011CoveredT201,T198,T210
1111101Not Covered
1111110CoveredT197,T87,T211
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT19,T212,T213
1110111CoveredT1,T3,T4
1111011CoveredT49,T198,T210
1111101Not Covered
1111110CoveredT63,T197,T206
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT208,T50,T212
1110111CoveredT1,T3,T4
1111011CoveredT51,T201,T198
1111101Not Covered
1111110CoveredT39,T49,T214
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T3,T4
1011111Not Covered
1101111CoveredT92,T215,T212
1110111CoveredT1,T3,T4
1111011CoveredT49,T51,T201
1111101Not Covered
1111110CoveredT138,T214,T216
1111111CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       196
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T197,T87
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T63,T197
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT39,T137,T49
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       212
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT137,T138,T214
111CoveredT1,T2,T3 

 LINE       212
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT20,T137,T197
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT20,T39,T137
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT20,T39,T137
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T3,T4
101CoveredT1,T2,T3
110CoveredT20,T39,T137
111CoveredT1,T2,T3 

 LINE       218
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       222
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT10,T11,T116
10CoveredT1,T3,T4
11CoveredT10,T25,T92 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T116
010CoveredT10,T11,T116
100CoveredT10,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT10,T11,T116 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T20,T10
11CoveredT10,T11,T116 

 LINE       222
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT19,T10,T11
10CoveredT1,T3,T4
11CoveredT19,T10,T25 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T116
010CoveredT19,T10,T11
100CoveredT10,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT19,T10,T11 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T20,T10
11CoveredT10,T11,T116 

 LINE       222
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT10,T11,T116
10CoveredT1,T3,T4
11CoveredT10,T25,T92 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T116
010CoveredT10,T11,T116
100CoveredT10,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT10,T11,T116 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T20,T10
11CoveredT10,T11,T116 

 LINE       222
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT10,T11,T116
10CoveredT1,T3,T4
11CoveredT10,T25,T92 

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T116
010CoveredT10,T11,T116
100CoveredT10,T11,T25 

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT10,T11,T116 

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T20,T10
11CoveredT10,T11,T116 

 LINE       232
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       239
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT49,T51,T201
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       239
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT63,T217,T49
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       239
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT6,T27,T39
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       239
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T39,T63
10CoveredT1,T2,T3
11CoveredT1,T3,T4 

 LINE       291
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T26,T196
11CoveredT1,T3,T4 

 LINE       292
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T4,T16
10CoveredT1,T3,T4
11CoveredT1,T3,T4 

 LINE       302
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       305
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4 

 LINE       308
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT1,T3,T4 

 LINE       377
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT1,T3,T4
10CoveredT1,T2,T3 

 LINE       382
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT14,T15,T59
10CoveredT14,T15,T59
11CoveredT1,T2,T3 

 LINE       393
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       399
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T3,T6
1111CoveredT1,T2,T3 

 LINE       399
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3 

 LINE       399
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T4
110CoveredT3,T6,T43
111CoveredT1,T2,T3 

 LINE       399
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6 

 LINE       407
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111CoveredT10
110111CoveredT6,T27,T40
111011Not Covered
111101CoveredT1,T3,T4
111110CoveredT3,T6,T39
111111CoveredT1,T3,T4 

 LINE       407
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6 

 LINE       428
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT4,T19,T27
11CoveredT1,T3,T6 

 LINE       432
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT4,T16,T27
10CoveredT1,T3,T4
11CoveredT27,T39,T92 

 LINE       432
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T16,T27 

 LINE       442
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T19,T34
10CoveredT1,T3,T6
11CoveredT1,T49,T50 

 LINE       451
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T19,T35 

 LINE       451
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T35,T36
10CoveredT1,T49,T50 

 LINE       456
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT19,T34,T11
10CoveredT1,T3,T6
11CoveredT19,T35,T36 

 LINE       491
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------
-1--2--3-StatusTests
011CoveredT14,T15,T59
101Not Covered
110CoveredT3,T6,T43
111CoveredT1,T2,T3 

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T3,T6
101CoveredT4,T6,T19
110CoveredT39,T92,T112
111CoveredT1,T3,T6 

 LINE       497
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT27,T92,T215
110CoveredT1,T3,T6
111CoveredT39,T92,T112 

 LINE       501
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T6
110CoveredT6,T49,T138
111CoveredT4,T6,T19 

 LINE       503
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T19
11CoveredT1,T3,T6 

 LINE       504
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT39,T92,T112 

 LINE       505
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11CoveredT4,T6,T19 

 LINE       513
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6 

 LINE       513
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11CoveredT1,T3,T6 

 LINE       513
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T92,T112 

 LINE       521
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T63,T64
11CoveredT4,T6,T19 

 LINE       521
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T92,T112 

 LINE       523
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T3,T6 

 LINE       597
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT138,T197,T205
110CoveredT4,T6,T19
111CoveredT1,T3,T6 

 LINE       598
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T19,T10
10CoveredT1,T3,T6
11CoveredT1,T3,T6 

 LINE       614
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T6,T36
110CoveredT39,T92,T112
111CoveredT1,T3,T6 

 LINE       624
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T19 

 LINE       624
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6 

 LINE       628
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T19 

 LINE       628
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT4,T6,T19
1CoveredT1,T2,T3 

 LINE       636
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T6
10CoveredT4,T6,T19 

 LINE       636
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T19
10CoveredT1,T2,T3
11CoveredT1,T3,T6 

 LINE       654
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T19 

 LINE       654
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6 

 LINE       654
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T19
10CoveredT1,T2,T3
11CoveredT1,T3,T6 

 LINE       659
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT14,T15,T59
101CoveredT10,T11,T116
110Not Covered
111CoveredT1,T3,T4 

 LINE       659
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT1,T2,T3
10Not Covered 

 LINE       659
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T3,T4
1110CoveredT1,T3,T4
1111CoveredT1,T3,T4 

 LINE       677
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT203
10Not Covered 

 LINE       683
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       736
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T19,T49 

 LINE       747
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       775
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6 

 LINE       775
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T3,T6
1CoveredT1,T3,T6 

 LINE       787
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       790
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T19,T49 

 LINE       790
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T3,T4
11CoveredT1,T19,T49 

 LINE       790
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T3,T6
100CoveredT49,T51,T201 

 LINE       790
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT203 

 LINE       794
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T3,T4
11CoveredT1,T19,T49
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 186 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 302 2 2 100.00
TERNARY 451 2 2 100.00
TERNARY 513 3 3 100.00
TERNARY 624 3 3 100.00
TERNARY 628 3 3 100.00
TERNARY 654 3 3 100.00
TERNARY 683 2 2 100.00
TERNARY 736 2 2 100.00
TERNARY 747 2 2 100.00
TERNARY 775 2 2 100.00
TERNARY 167 2 2 100.00
IF 257 3 3 100.00
IF 360 4 4 100.00
IF 600 4 4 100.00
IF 674 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	232	(no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	302	((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T19,T35
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T3,T6
0 1 Covered T39,T92,T112
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T3,T6
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T2,T3
0 0 Covered T4,T6,T19 



	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T19
0 1 Covered T1,T3,T6
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	736	(data_err_o) ?

Branches:
-1-StatusTests
1 Covered T1,T19,T49
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T3,T4 



	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T1,T3,T4
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T6
0 0 1 Covered T1,T3,T6
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 395323925 486152 0 0
ExclusiveOps_A 395323925 394485667 0 0
ExclusiveProgHazard_A 395323925 394485667 0 0
ExclusiveState_A 395323925 394485667 0 0
ForwardCheck_A 395323925 1519282 0 0
IdleCheck_A 395323925 48489611 0 0
MaxBufs_A 1042 1042 0 0
OneHotAlloc_A 395323925 394485667 0 0
OneHotMatch_A 395323925 394485667 0 0
OneHotRspMatch_A 395323925 394485667 0 0
OneHotUpdate_A 395323925 394485667 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 486152 0 0
T1 2029 10 0 0
T2 1545 0 0 0
T3 195207 6424 0 0
T4 72845 39 0 0
T5 380715 0 0 0
T6 59481 0 0 0
T10 0 54 0 0
T16 194750 0 0 0
T17 1766 8 0 0
T18 3644 0 0 0
T19 3275 9 0 0
T20 0 64 0 0
T26 0 11 0 0
T39 0 961 0 0
T43 0 290 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 1519282 0 0
T4 72845 48 0 0
T5 380715 0 0 0
T6 59481 6902 0 0
T10 0 78 0 0
T16 194750 0 0 0
T17 1766 0 0 0
T18 3644 0 0 0
T19 3275 9 0 0
T20 0 78 0 0
T26 3975 12 0 0
T27 942 4 0 0
T38 1988 0 0 0
T39 0 10343 0 0
T43 0 342 0 0
T61 0 2 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 48489611 0 0
T1 2029 74 0 0
T2 1545 0 0 0
T3 195207 64415 0 0
T4 72845 188 0 0
T5 380715 0 0 0
T6 59481 18308 0 0
T16 194750 0 0 0
T17 1766 52 0 0
T18 3644 0 0 0
T19 3275 59 0 0
T20 0 220 0 0
T26 0 141 0 0
T27 0 8 0 0
T34 0 24 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395323925 394485667 0 0
T1 2029 1912 0 0
T2 1545 1459 0 0
T3 195207 195105 0 0
T4 72845 72793 0 0
T5 380715 363806 0 0
T6 59481 59354 0 0
T16 194750 194743 0 0
T17 1766 1624 0 0
T18 3644 3008 0 0
T19 3275 3118 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%