Unified Coverage Report :: Module :: tlul_lc_gate

Module : tlul_lc_gate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.63	88.24	94.44		57.14	83.33	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prog_tl_gate	72.41	88.24	83.33		57.14	83.33	50.00
tb.dut.u_tl_gate	74.63	88.24	94.44		57.14	83.33	50.00

---

Module Instance : tb.dut.u_prog_tl_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.41	88.24	83.33		57.14	83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.63	95.28	85.71		57.14	87.50	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	97.50	100.00	90.00			100.00	100.00

---

Module Instance : tb.dut.u_tl_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.63	88.24	94.44		57.14	83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.00	95.28	85.71		57.14	84.38	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	88.33	100.00	70.00			83.33	100.00

Line Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	45	88.24
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	22	78.57
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : tlul_lc_gate

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T10,T11,T12

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Module : tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T3
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T1,T2,T3
StFlush	184	Not Covered
StOutstanding	174	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T10,T11,T12
StError->StErrorOutstanding	203	Covered	T1,T2,T3
StErrorOutstanding->StActive	211	Covered	T1,T2,T3
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T10,T11,T12
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	10	71.43
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T10,T11,T12
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T1,T3,T4
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T10,T11,T12
StOutstanding	-	-	0	-	-	-	-	Covered	T7,T8,T9
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T1,T2,T3
StError	-	-	-	-	-	0	-	Covered	T10,T11,T12
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	790647850	0	0	0
u_state_regs_A	790647850	788971334	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790647850	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790647850	788971334	0	0
T1	4058	3824	0	0
T2	3090	2918	0	0
T3	390414	390210	0	0
T4	145690	145586	0	0
T5	761430	727612	0	0
T6	118962	118708	0	0
T16	389500	389486	0	0
T17	3532	3248	0	0
T18	7288	6016	0	0
T19	6550	6236	0	0

Line Coverage for Instance : tb.dut.u_prog_tl_gate

	Line No.	Total	Covered	Percent
TOTAL		51	45	88.24
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	22	78.57
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_prog_tl_gate

	Total	Covered	Percent
Conditions	18	15	83.33
Logical	18	15	83.33
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T8,T9,T22
1	Covered	T10,T11,T12

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prog_tl_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T3
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T1,T2,T3
StFlush	184	Not Covered
StOutstanding	174	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T10,T11,T12
StError->StErrorOutstanding	203	Covered	T1,T2,T3
StErrorOutstanding->StActive	211	Covered	T1,T2,T3
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T10,T11,T12
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Instance : tb.dut.u_prog_tl_gate

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	10	71.43
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T10,T11,T12
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T1,T4,T5
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T10,T11,T12
StOutstanding	-	-	0	-	-	-	-	Covered	T8,T9,T22
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T1,T2,T3
StError	-	-	-	-	-	0	-	Covered	T10,T11,T12
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prog_tl_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	395323925	0	0	0
u_state_regs_A	395323925	394485667	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0

Line Coverage for Instance : tb.dut.u_tl_gate

	Line No.	Total	Covered	Percent
TOTAL		51	45	88.24
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	22	78.57
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tl_gate

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T7,T23,T24
1	Covered	T10,T11,T12

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_tl_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T3
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T1,T2,T3
StFlush	184	Not Covered
StOutstanding	174	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T10,T11,T12
StError->StErrorOutstanding	203	Covered	T1,T2,T3
StErrorOutstanding->StActive	211	Covered	T1,T2,T3
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T10,T11,T12
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tl_gate

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	10	71.43
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T10,T11,T12
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T1,T3,T4
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T10,T11,T12
StOutstanding	-	-	0	-	-	-	-	Covered	T7,T23,T24
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T1,T2,T3
StError	-	-	-	-	-	0	-	Covered	T10,T11,T12
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	395323925	0	0	0
u_state_regs_A	395323925	394485667	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395323925	394485667	0	0
T1	2029	1912	0	0
T2	1545	1459	0	0
T3	195207	195105	0	0
T4	72845	72793	0	0
T5	380715	363806	0	0
T6	59481	59354	0	0
T16	194750	194743	0	0
T17	1766	1624	0	0
T18	3644	3008	0	0
T19	3275	3118	0	0