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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 95.24 93.90 98.31 92.52 97.14 96.89 98.18


Total test records in report: 1257
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T1072 /workspace/coverage/default/1.flash_ctrl_fetch_code.1998784856 Jul 25 05:05:49 PM PDT 24 Jul 25 05:06:14 PM PDT 24 297524900 ps
T1073 /workspace/coverage/default/0.flash_ctrl_host_dir_rd.1558259372 Jul 25 05:05:42 PM PDT 24 Jul 25 05:07:47 PM PDT 24 266905600 ps
T1074 /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3913218190 Jul 25 05:09:49 PM PDT 24 Jul 25 05:14:18 PM PDT 24 12479335400 ps
T1075 /workspace/coverage/default/1.flash_ctrl_phy_arb.16593282 Jul 25 05:05:48 PM PDT 24 Jul 25 05:08:43 PM PDT 24 11361312000 ps
T1076 /workspace/coverage/default/1.flash_ctrl_alert_test.2194079423 Jul 25 05:06:05 PM PDT 24 Jul 25 05:06:19 PM PDT 24 122531400 ps
T1077 /workspace/coverage/default/26.flash_ctrl_smoke.1606537500 Jul 25 05:09:04 PM PDT 24 Jul 25 05:11:13 PM PDT 24 877107100 ps
T1078 /workspace/coverage/default/1.flash_ctrl_smoke.3816120003 Jul 25 05:05:52 PM PDT 24 Jul 25 05:07:33 PM PDT 24 23670400 ps
T1079 /workspace/coverage/default/64.flash_ctrl_otp_reset.2667519797 Jul 25 05:10:37 PM PDT 24 Jul 25 05:12:51 PM PDT 24 143171300 ps
T1080 /workspace/coverage/default/8.flash_ctrl_rw_serr.2579647647 Jul 25 05:07:08 PM PDT 24 Jul 25 05:17:24 PM PDT 24 3609268000 ps
T1081 /workspace/coverage/default/12.flash_ctrl_ro.235873639 Jul 25 05:07:38 PM PDT 24 Jul 25 05:09:44 PM PDT 24 2320444700 ps
T1082 /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2223916335 Jul 25 05:09:48 PM PDT 24 Jul 25 05:12:01 PM PDT 24 12707719500 ps
T1083 /workspace/coverage/default/35.flash_ctrl_alert_test.3887924196 Jul 25 05:09:48 PM PDT 24 Jul 25 05:10:02 PM PDT 24 438247800 ps
T1084 /workspace/coverage/default/17.flash_ctrl_phy_arb.231014229 Jul 25 05:08:17 PM PDT 24 Jul 25 05:12:52 PM PDT 24 91234500 ps
T1085 /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.617017411 Jul 25 05:07:52 PM PDT 24 Jul 25 05:11:05 PM PDT 24 8777833000 ps
T1086 /workspace/coverage/default/16.flash_ctrl_rw.1249223429 Jul 25 05:08:15 PM PDT 24 Jul 25 05:18:16 PM PDT 24 6770911600 ps
T1087 /workspace/coverage/default/4.flash_ctrl_connect.871356802 Jul 25 05:06:41 PM PDT 24 Jul 25 05:06:54 PM PDT 24 45095200 ps
T1088 /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2648343761 Jul 25 05:06:06 PM PDT 24 Jul 25 05:07:37 PM PDT 24 10019663400 ps
T1089 /workspace/coverage/default/10.flash_ctrl_connect.2377013323 Jul 25 05:07:19 PM PDT 24 Jul 25 05:07:33 PM PDT 24 103377100 ps
T1090 /workspace/coverage/default/0.flash_ctrl_rw_serr.3705104387 Jul 25 05:05:43 PM PDT 24 Jul 25 05:16:08 PM PDT 24 54117342300 ps
T1091 /workspace/coverage/default/0.flash_ctrl_rd_ooo.2495213738 Jul 25 05:05:49 PM PDT 24 Jul 25 05:06:33 PM PDT 24 48011800 ps
T1092 /workspace/coverage/default/30.flash_ctrl_disable.3158688270 Jul 25 05:09:26 PM PDT 24 Jul 25 05:09:46 PM PDT 24 25790200 ps
T1093 /workspace/coverage/default/13.flash_ctrl_rand_ops.91636369 Jul 25 05:07:48 PM PDT 24 Jul 25 05:13:37 PM PDT 24 48209600 ps
T1094 /workspace/coverage/default/0.flash_ctrl_config_regwen.2117170090 Jul 25 05:05:48 PM PDT 24 Jul 25 05:06:03 PM PDT 24 39082800 ps
T1095 /workspace/coverage/default/21.flash_ctrl_otp_reset.3583747561 Jul 25 05:08:44 PM PDT 24 Jul 25 05:11:01 PM PDT 24 442746100 ps
T1096 /workspace/coverage/default/2.flash_ctrl_stress_all.2204409793 Jul 25 05:06:16 PM PDT 24 Jul 25 05:23:18 PM PDT 24 9251198800 ps
T1097 /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3931278478 Jul 25 05:07:27 PM PDT 24 Jul 25 05:07:41 PM PDT 24 25511200 ps
T1098 /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3161282432 Jul 25 05:09:00 PM PDT 24 Jul 25 05:10:29 PM PDT 24 2897588500 ps
T1099 /workspace/coverage/default/10.flash_ctrl_ro.422056846 Jul 25 05:07:19 PM PDT 24 Jul 25 05:09:16 PM PDT 24 1947544200 ps
T401 /workspace/coverage/default/48.flash_ctrl_sec_info_access.135718049 Jul 25 05:10:19 PM PDT 24 Jul 25 05:11:29 PM PDT 24 3030560500 ps
T1100 /workspace/coverage/default/21.flash_ctrl_disable.3058898904 Jul 25 05:08:44 PM PDT 24 Jul 25 05:09:06 PM PDT 24 13085900 ps
T1101 /workspace/coverage/default/29.flash_ctrl_smoke.703331736 Jul 25 05:09:18 PM PDT 24 Jul 25 05:10:08 PM PDT 24 35382500 ps
T1102 /workspace/coverage/default/49.flash_ctrl_connect.2236465580 Jul 25 05:10:20 PM PDT 24 Jul 25 05:10:36 PM PDT 24 19648100 ps
T1103 /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3678453893 Jul 25 05:09:47 PM PDT 24 Jul 25 05:10:16 PM PDT 24 67877600 ps
T1104 /workspace/coverage/default/15.flash_ctrl_smoke.4104819512 Jul 25 05:08:04 PM PDT 24 Jul 25 05:10:12 PM PDT 24 63070000 ps
T1105 /workspace/coverage/default/12.flash_ctrl_smoke.2852776215 Jul 25 05:07:26 PM PDT 24 Jul 25 05:10:18 PM PDT 24 37834800 ps
T1106 /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1713748042 Jul 25 05:07:10 PM PDT 24 Jul 25 05:07:23 PM PDT 24 45918800 ps
T77 /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.948628799 Jul 25 05:06:31 PM PDT 24 Jul 25 05:06:46 PM PDT 24 23303500 ps
T1107 /workspace/coverage/default/50.flash_ctrl_connect.581317405 Jul 25 05:10:17 PM PDT 24 Jul 25 05:10:33 PM PDT 24 23895400 ps
T1108 /workspace/coverage/default/19.flash_ctrl_smoke.1522492221 Jul 25 05:08:36 PM PDT 24 Jul 25 05:10:37 PM PDT 24 68160500 ps
T1109 /workspace/coverage/default/34.flash_ctrl_smoke.1554271439 Jul 25 05:09:38 PM PDT 24 Jul 25 05:11:48 PM PDT 24 131570800 ps
T1110 /workspace/coverage/default/31.flash_ctrl_rw_evict.729975060 Jul 25 05:09:27 PM PDT 24 Jul 25 05:09:59 PM PDT 24 33508300 ps
T1111 /workspace/coverage/default/3.flash_ctrl_error_mp.307827930 Jul 25 05:06:22 PM PDT 24 Jul 25 05:43:59 PM PDT 24 2468045400 ps
T65 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2744342761 Jul 25 05:00:11 PM PDT 24 Jul 25 05:01:10 PM PDT 24 2864824200 ps
T66 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.401999820 Jul 25 05:00:31 PM PDT 24 Jul 25 05:00:49 PM PDT 24 231220600 ps
T67 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4191336038 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:43 PM PDT 24 272726500 ps
T1112 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3168937112 Jul 25 05:00:19 PM PDT 24 Jul 25 05:00:34 PM PDT 24 14485100 ps
T1113 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.885850911 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:05 PM PDT 24 35579600 ps
T245 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3618950180 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:21 PM PDT 24 27530500 ps
T115 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.988006428 Jul 25 05:00:19 PM PDT 24 Jul 25 05:00:39 PM PDT 24 112577500 ps
T240 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1430478088 Jul 25 05:00:15 PM PDT 24 Jul 25 05:01:23 PM PDT 24 10543612800 ps
T246 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2716926735 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:39 PM PDT 24 17323300 ps
T1114 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2906529504 Jul 25 05:00:00 PM PDT 24 Jul 25 05:00:15 PM PDT 24 40386100 ps
T247 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1722926371 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:39 PM PDT 24 89659800 ps
T231 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.459033831 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:05 PM PDT 24 34882200 ps
T242 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2695191075 Jul 25 05:00:22 PM PDT 24 Jul 25 05:00:38 PM PDT 24 39454000 ps
T312 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3623337431 Jul 25 05:00:15 PM PDT 24 Jul 25 05:00:30 PM PDT 24 53890500 ps
T1115 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.356740015 Jul 25 05:00:14 PM PDT 24 Jul 25 05:00:28 PM PDT 24 24433400 ps
T113 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.165422927 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:29 PM PDT 24 893525000 ps
T313 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3943752319 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:25 PM PDT 24 27298200 ps
T114 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.380655155 Jul 25 05:00:09 PM PDT 24 Jul 25 05:07:50 PM PDT 24 698794300 ps
T311 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2291096166 Jul 25 04:59:56 PM PDT 24 Jul 25 05:00:14 PM PDT 24 107087600 ps
T1116 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.760367808 Jul 25 05:00:19 PM PDT 24 Jul 25 05:00:34 PM PDT 24 141594800 ps
T316 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2390097067 Jul 25 05:00:27 PM PDT 24 Jul 25 05:00:41 PM PDT 24 78467300 ps
T241 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1522533099 Jul 25 05:00:34 PM PDT 24 Jul 25 05:00:52 PM PDT 24 136034500 ps
T314 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3880597312 Jul 25 05:00:28 PM PDT 24 Jul 25 05:00:42 PM PDT 24 202234900 ps
T218 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1271362421 Jul 25 05:00:13 PM PDT 24 Jul 25 05:00:32 PM PDT 24 51039500 ps
T219 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1608830715 Jul 25 05:00:09 PM PDT 24 Jul 25 05:00:26 PM PDT 24 39832700 ps
T1117 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3441646317 Jul 25 05:00:34 PM PDT 24 Jul 25 05:00:50 PM PDT 24 40616700 ps
T315 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3006585816 Jul 25 05:00:31 PM PDT 24 Jul 25 05:00:45 PM PDT 24 17958000 ps
T224 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2680365503 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:34 PM PDT 24 88674000 ps
T225 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4121371641 Jul 25 05:00:05 PM PDT 24 Jul 25 05:06:29 PM PDT 24 812838800 ps
T226 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.8056991 Jul 25 05:00:10 PM PDT 24 Jul 25 05:00:31 PM PDT 24 62344200 ps
T228 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2643921381 Jul 25 05:00:24 PM PDT 24 Jul 25 05:13:07 PM PDT 24 2665105300 ps
T1118 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3636167887 Jul 25 04:59:56 PM PDT 24 Jul 25 05:00:12 PM PDT 24 15154200 ps
T1119 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.437003548 Jul 25 05:00:41 PM PDT 24 Jul 25 05:00:55 PM PDT 24 25444100 ps
T227 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2074812098 Jul 25 05:00:07 PM PDT 24 Jul 25 05:14:48 PM PDT 24 535752300 ps
T317 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.490450291 Jul 25 05:00:22 PM PDT 24 Jul 25 05:00:36 PM PDT 24 16585000 ps
T229 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2978072772 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:12 PM PDT 24 159804600 ps
T1120 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2250137256 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:27 PM PDT 24 17012500 ps
T230 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1238135696 Jul 25 05:00:15 PM PDT 24 Jul 25 05:00:33 PM PDT 24 113813500 ps
T282 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3976731791 Jul 25 05:00:15 PM PDT 24 Jul 25 05:00:32 PM PDT 24 294845600 ps
T425 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.533835875 Jul 25 05:00:24 PM PDT 24 Jul 25 05:00:38 PM PDT 24 31871500 ps
T283 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3773267686 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:28 PM PDT 24 134949600 ps
T1121 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2709028817 Jul 25 04:59:55 PM PDT 24 Jul 25 05:00:09 PM PDT 24 30017700 ps
T286 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.481140923 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:24 PM PDT 24 72071300 ps
T1122 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2654952157 Jul 25 05:00:18 PM PDT 24 Jul 25 05:00:32 PM PDT 24 14719500 ps
T251 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1084395915 Jul 25 05:00:09 PM PDT 24 Jul 25 05:15:10 PM PDT 24 2172128700 ps
T1123 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.784641154 Jul 25 04:59:53 PM PDT 24 Jul 25 05:00:09 PM PDT 24 11815700 ps
T1124 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1200052138 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:29 PM PDT 24 58332100 ps
T1125 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1347823482 Jul 25 04:59:54 PM PDT 24 Jul 25 05:00:11 PM PDT 24 97910600 ps
T1126 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1571870054 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:40 PM PDT 24 26545200 ps
T426 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4041610911 Jul 25 05:00:20 PM PDT 24 Jul 25 05:00:38 PM PDT 24 210954900 ps
T250 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1020171589 Jul 25 05:00:15 PM PDT 24 Jul 25 05:15:10 PM PDT 24 1134455000 ps
T284 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3107446474 Jul 25 05:00:21 PM PDT 24 Jul 25 05:00:39 PM PDT 24 55643300 ps
T1127 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4291085899 Jul 25 05:00:08 PM PDT 24 Jul 25 05:00:22 PM PDT 24 28312000 ps
T424 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3871452309 Jul 25 04:59:59 PM PDT 24 Jul 25 05:00:17 PM PDT 24 48849200 ps
T1128 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3399953565 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:39 PM PDT 24 24663200 ps
T1129 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1128966429 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:31 PM PDT 24 70845100 ps
T248 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3449002416 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:34 PM PDT 24 204136900 ps
T243 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2186783277 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:36 PM PDT 24 182795100 ps
T1130 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3712836710 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:39 PM PDT 24 50470300 ps
T1131 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2653270277 Jul 25 04:59:56 PM PDT 24 Jul 25 05:00:14 PM PDT 24 57534100 ps
T1132 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4159432924 Jul 25 05:00:19 PM PDT 24 Jul 25 05:00:35 PM PDT 24 41638000 ps
T285 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.223013306 Jul 25 04:59:54 PM PDT 24 Jul 25 05:00:59 PM PDT 24 1591196900 ps
T1133 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3125587835 Jul 25 05:00:17 PM PDT 24 Jul 25 05:00:34 PM PDT 24 84286900 ps
T244 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.829205673 Jul 25 04:59:57 PM PDT 24 Jul 25 05:00:16 PM PDT 24 97609200 ps
T1134 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.659136452 Jul 25 05:00:17 PM PDT 24 Jul 25 05:00:30 PM PDT 24 37318400 ps
T1135 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4264276724 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:30 PM PDT 24 34770900 ps
T1136 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3652045176 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:39 PM PDT 24 1509939400 ps
T1137 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2222447887 Jul 25 05:00:28 PM PDT 24 Jul 25 05:00:42 PM PDT 24 17086900 ps
T1138 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.857050519 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:41 PM PDT 24 32321100 ps
T1139 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2846529114 Jul 25 05:00:39 PM PDT 24 Jul 25 05:00:53 PM PDT 24 15248800 ps
T1140 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2335783817 Jul 25 04:59:57 PM PDT 24 Jul 25 05:00:10 PM PDT 24 19055400 ps
T1141 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.142891805 Jul 25 05:00:02 PM PDT 24 Jul 25 05:00:54 PM PDT 24 2389118700 ps
T232 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4230413847 Jul 25 04:59:59 PM PDT 24 Jul 25 05:00:13 PM PDT 24 58857600 ps
T233 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.142335376 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:30 PM PDT 24 57235900 ps
T1142 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1636974538 Jul 25 05:00:33 PM PDT 24 Jul 25 05:00:49 PM PDT 24 20214900 ps
T1143 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2930361676 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:39 PM PDT 24 81507800 ps
T1144 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.703263703 Jul 25 05:00:23 PM PDT 24 Jul 25 05:00:40 PM PDT 24 434898400 ps
T1145 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2322670610 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:41 PM PDT 24 34017900 ps
T1146 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.749342690 Jul 25 05:00:05 PM PDT 24 Jul 25 05:00:23 PM PDT 24 148246100 ps
T1147 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2253171928 Jul 25 05:00:32 PM PDT 24 Jul 25 05:00:48 PM PDT 24 45052300 ps
T1148 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4140382331 Jul 25 05:00:09 PM PDT 24 Jul 25 05:00:23 PM PDT 24 15261200 ps
T288 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3783116887 Jul 25 05:00:01 PM PDT 24 Jul 25 05:00:18 PM PDT 24 65714000 ps
T1149 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3330282966 Jul 25 05:00:23 PM PDT 24 Jul 25 05:00:37 PM PDT 24 17035600 ps
T1150 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3086822660 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:27 PM PDT 24 25288900 ps
T1151 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1268490594 Jul 25 05:00:14 PM PDT 24 Jul 25 05:00:28 PM PDT 24 11212600 ps
T290 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1611524247 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:42 PM PDT 24 105633200 ps
T1152 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3065582343 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:30 PM PDT 24 60555800 ps
T1153 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2720547352 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:29 PM PDT 24 27102400 ps
T1154 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2988048087 Jul 25 05:00:02 PM PDT 24 Jul 25 05:00:22 PM PDT 24 43890900 ps
T1155 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.709504766 Jul 25 05:00:37 PM PDT 24 Jul 25 05:00:50 PM PDT 24 14780000 ps
T255 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3188679304 Jul 25 05:00:17 PM PDT 24 Jul 25 05:00:36 PM PDT 24 48260400 ps
T1156 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.928573091 Jul 25 05:00:33 PM PDT 24 Jul 25 05:00:47 PM PDT 24 105238800 ps
T1157 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.306320212 Jul 25 05:00:14 PM PDT 24 Jul 25 05:00:53 PM PDT 24 45219600 ps
T252 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2307842501 Jul 25 05:00:09 PM PDT 24 Jul 25 05:00:30 PM PDT 24 248632500 ps
T287 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1433568744 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:36 PM PDT 24 189396800 ps
T253 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.630697166 Jul 25 05:00:13 PM PDT 24 Jul 25 05:00:30 PM PDT 24 140432300 ps
T1158 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1432005502 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:25 PM PDT 24 147344100 ps
T1159 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3714294550 Jul 25 05:00:29 PM PDT 24 Jul 25 05:00:43 PM PDT 24 51039000 ps
T1160 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2717183160 Jul 25 04:59:49 PM PDT 24 Jul 25 05:00:11 PM PDT 24 908209000 ps
T1161 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4229877671 Jul 25 05:00:33 PM PDT 24 Jul 25 05:00:47 PM PDT 24 16252300 ps
T1162 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2050667493 Jul 25 05:00:32 PM PDT 24 Jul 25 05:00:46 PM PDT 24 38215400 ps
T349 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.161755672 Jul 25 04:59:53 PM PDT 24 Jul 25 05:12:31 PM PDT 24 357914500 ps
T1163 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.906543766 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:30 PM PDT 24 737947400 ps
T1164 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.385395724 Jul 25 05:00:09 PM PDT 24 Jul 25 05:00:23 PM PDT 24 11859600 ps
T1165 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3221093145 Jul 25 05:00:34 PM PDT 24 Jul 25 05:00:52 PM PDT 24 20924500 ps
T1166 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2195902516 Jul 25 05:00:27 PM PDT 24 Jul 25 05:00:41 PM PDT 24 48205200 ps
T289 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2596728454 Jul 25 05:00:13 PM PDT 24 Jul 25 05:00:31 PM PDT 24 267056100 ps
T1167 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3433937416 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:28 PM PDT 24 23741100 ps
T1168 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4051041586 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:29 PM PDT 24 36613400 ps
T1169 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1665214423 Jul 25 05:00:33 PM PDT 24 Jul 25 05:00:47 PM PDT 24 196888500 ps
T1170 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.102747597 Jul 25 05:00:18 PM PDT 24 Jul 25 05:00:38 PM PDT 24 39321900 ps
T1171 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2680913161 Jul 25 04:59:51 PM PDT 24 Jul 25 05:00:05 PM PDT 24 44541700 ps
T1172 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3660316077 Jul 25 05:00:10 PM PDT 24 Jul 25 05:00:24 PM PDT 24 14932100 ps
T1173 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2966120679 Jul 25 05:00:32 PM PDT 24 Jul 25 05:00:47 PM PDT 24 61588600 ps
T1174 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2403597758 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:40 PM PDT 24 56826100 ps
T1175 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1890593735 Jul 25 05:00:21 PM PDT 24 Jul 25 05:00:35 PM PDT 24 29969300 ps
T1176 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1850438593 Jul 25 04:59:51 PM PDT 24 Jul 25 05:00:08 PM PDT 24 57031400 ps
T1177 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1033050891 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:43 PM PDT 24 93978000 ps
T1178 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.768460285 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:27 PM PDT 24 56397700 ps
T1179 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3621209281 Jul 25 05:00:08 PM PDT 24 Jul 25 05:00:24 PM PDT 24 74562900 ps
T1180 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2652623321 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:36 PM PDT 24 386315700 ps
T1181 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.655956619 Jul 25 05:00:17 PM PDT 24 Jul 25 05:00:31 PM PDT 24 16204000 ps
T254 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2693988775 Jul 25 05:00:27 PM PDT 24 Jul 25 05:00:44 PM PDT 24 367010300 ps
T1182 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1096212925 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:23 PM PDT 24 18092500 ps
T257 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2241998228 Jul 25 05:00:09 PM PDT 24 Jul 25 05:15:03 PM PDT 24 788007700 ps
T1183 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3236869891 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:32 PM PDT 24 15100000 ps
T1184 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4138662995 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:21 PM PDT 24 17770000 ps
T1185 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4205503013 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:26 PM PDT 24 318540400 ps
T291 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4025436444 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:33 PM PDT 24 191315400 ps
T1186 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1116101622 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:27 PM PDT 24 73276900 ps
T1187 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.702702245 Jul 25 05:00:15 PM PDT 24 Jul 25 05:07:50 PM PDT 24 419780700 ps
T1188 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2581752582 Jul 25 05:00:11 PM PDT 24 Jul 25 05:00:25 PM PDT 24 45423200 ps
T1189 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.4207255452 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:28 PM PDT 24 93514200 ps
T1190 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2720188887 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:26 PM PDT 24 53539500 ps
T292 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1817825602 Jul 25 05:00:15 PM PDT 24 Jul 25 05:00:31 PM PDT 24 118504400 ps
T1191 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1094649815 Jul 25 05:00:10 PM PDT 24 Jul 25 05:00:27 PM PDT 24 42015800 ps
T1192 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4088744150 Jul 25 05:00:19 PM PDT 24 Jul 25 05:00:35 PM PDT 24 151894500 ps
T1193 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.191094321 Jul 25 05:00:29 PM PDT 24 Jul 25 05:01:06 PM PDT 24 806847100 ps
T1194 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.641572484 Jul 25 05:00:03 PM PDT 24 Jul 25 05:00:22 PM PDT 24 84928200 ps
T1195 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1664082173 Jul 25 05:00:26 PM PDT 24 Jul 25 05:00:44 PM PDT 24 189272800 ps
T1196 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3956078840 Jul 25 04:59:55 PM PDT 24 Jul 25 05:00:34 PM PDT 24 2995672300 ps
T234 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2278662477 Jul 25 05:00:06 PM PDT 24 Jul 25 05:00:20 PM PDT 24 31778200 ps
T1197 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.974869908 Jul 25 05:00:18 PM PDT 24 Jul 25 05:00:32 PM PDT 24 32000500 ps
T1198 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1661342832 Jul 25 05:00:09 PM PDT 24 Jul 25 05:00:23 PM PDT 24 17289100 ps
T293 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1880953373 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:31 PM PDT 24 900471900 ps
T1199 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3741366894 Jul 25 05:00:06 PM PDT 24 Jul 25 05:00:20 PM PDT 24 45020100 ps
T1200 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.426576299 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:32 PM PDT 24 419740200 ps
T1201 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2280250363 Jul 25 05:00:06 PM PDT 24 Jul 25 05:00:20 PM PDT 24 23940000 ps
T1202 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4124246255 Jul 25 05:00:30 PM PDT 24 Jul 25 05:00:44 PM PDT 24 184971700 ps
T1203 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.396915908 Jul 25 05:00:20 PM PDT 24 Jul 25 05:00:36 PM PDT 24 12117000 ps
T1204 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1602010806 Jul 25 04:59:47 PM PDT 24 Jul 25 05:00:04 PM PDT 24 37409500 ps
T1205 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4210352972 Jul 25 05:00:18 PM PDT 24 Jul 25 05:00:32 PM PDT 24 96402300 ps
T1206 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.278520580 Jul 25 05:00:04 PM PDT 24 Jul 25 05:00:38 PM PDT 24 57093300 ps
T1207 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2191715980 Jul 25 04:59:55 PM PDT 24 Jul 25 05:00:08 PM PDT 24 29889800 ps
T1208 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1771050138 Jul 25 05:00:03 PM PDT 24 Jul 25 05:00:43 PM PDT 24 375655200 ps
T1209 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3864522196 Jul 25 05:00:28 PM PDT 24 Jul 25 05:00:46 PM PDT 24 108786600 ps
T1210 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.4141759131 Jul 25 05:00:09 PM PDT 24 Jul 25 05:00:23 PM PDT 24 163015100 ps
T1211 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3929922476 Jul 25 05:00:10 PM PDT 24 Jul 25 05:00:29 PM PDT 24 144787300 ps
T1212 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.926194051 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:23 PM PDT 24 19874000 ps
T1213 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3327440849 Jul 25 05:00:29 PM PDT 24 Jul 25 05:00:43 PM PDT 24 26560700 ps
T1214 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2437336605 Jul 25 05:00:23 PM PDT 24 Jul 25 05:00:37 PM PDT 24 17083600 ps
T1215 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2295781920 Jul 25 05:00:08 PM PDT 24 Jul 25 05:00:25 PM PDT 24 164927200 ps
T1216 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.430015876 Jul 25 05:00:16 PM PDT 24 Jul 25 05:00:34 PM PDT 24 24623700 ps
T1217 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.468500040 Jul 25 05:00:40 PM PDT 24 Jul 25 05:00:54 PM PDT 24 44009400 ps
T347 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.875373279 Jul 25 05:00:09 PM PDT 24 Jul 25 05:07:47 PM PDT 24 1811199300 ps
T1218 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4217753864 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:30 PM PDT 24 67255000 ps
T1219 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4036673755 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:47 PM PDT 24 409526200 ps
T1220 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3610777515 Jul 25 05:00:13 PM PDT 24 Jul 25 05:00:32 PM PDT 24 119532300 ps
T1221 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2669574593 Jul 25 05:00:08 PM PDT 24 Jul 25 05:00:24 PM PDT 24 21344300 ps
T1222 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3822286889 Jul 25 05:00:12 PM PDT 24 Jul 25 05:00:28 PM PDT 24 23858300 ps
T1223 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3449216716 Jul 25 05:00:00 PM PDT 24 Jul 25 05:00:15 PM PDT 24 48020400 ps
T1224 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1641037622 Jul 25 04:59:49 PM PDT 24 Jul 25 05:01:12 PM PDT 24 3208125200 ps
T351 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1724647696 Jul 25 05:00:21 PM PDT 24 Jul 25 05:08:01 PM PDT 24 1494171400 ps
T1225 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3698560661 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:26 PM PDT 24 1849482500 ps
T350 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3174063003 Jul 25 05:00:11 PM PDT 24 Jul 25 05:06:37 PM PDT 24 599861500 ps
T345 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3691436547 Jul 25 05:00:35 PM PDT 24 Jul 25 05:15:26 PM PDT 24 373771600 ps
T1226 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1058724550 Jul 25 05:00:28 PM PDT 24 Jul 25 05:00:41 PM PDT 24 105661700 ps
T1227 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3363280378 Jul 25 05:00:15 PM PDT 24 Jul 25 05:00:32 PM PDT 24 138343600 ps
T1228 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2938566498 Jul 25 05:00:29 PM PDT 24 Jul 25 05:08:05 PM PDT 24 444815900 ps
T1229 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1533554253 Jul 25 05:00:29 PM PDT 24 Jul 25 05:00:42 PM PDT 24 16606600 ps
T235 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3583469883 Jul 25 04:59:50 PM PDT 24 Jul 25 05:00:04 PM PDT 24 42095100 ps
T1230 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3777045651 Jul 25 05:00:24 PM PDT 24 Jul 25 05:00:38 PM PDT 24 56184200 ps
T1231 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3163024204 Jul 25 05:00:36 PM PDT 24 Jul 25 05:00:50 PM PDT 24 17369800 ps
T1232 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.885427975 Jul 25 05:00:24 PM PDT 24 Jul 25 05:00:40 PM PDT 24 38295800 ps
T249 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2283326911 Jul 25 05:00:20 PM PDT 24 Jul 25 05:07:59 PM PDT 24 2506317900 ps
T1233 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3787149564 Jul 25 04:59:57 PM PDT 24 Jul 25 05:00:11 PM PDT 24 51889200 ps
T1234 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2017942376 Jul 25 05:00:22 PM PDT 24 Jul 25 05:00:35 PM PDT 24 14727900 ps
T1235 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2290017392 Jul 25 04:59:51 PM PDT 24 Jul 25 05:00:30 PM PDT 24 122093800 ps
T1236 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.863866318 Jul 25 05:00:14 PM PDT 24 Jul 25 05:00:28 PM PDT 24 18813600 ps
T1237 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.4110279033 Jul 25 05:00:07 PM PDT 24 Jul 25 05:00:21 PM PDT 24 13749500 ps
T352 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.890958850 Jul 25 05:00:03 PM PDT 24 Jul 25 05:07:53 PM PDT 24 291944100 ps
T344 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2223499827 Jul 25 05:00:05 PM PDT 24 Jul 25 05:00:26 PM PDT 24 108724200 ps
T1238 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.590739625 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:08 PM PDT 24 22398600 ps
T1239 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3066026140 Jul 25 05:00:06 PM PDT 24 Jul 25 05:00:21 PM PDT 24 177336800 ps
T1240 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2777057777 Jul 25 05:00:03 PM PDT 24 Jul 25 05:01:13 PM PDT 24 3281218900 ps
T1241 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2719324005 Jul 25 05:00:13 PM PDT 24 Jul 25 05:00:26 PM PDT 24 32080200 ps
T1242 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.610202596 Jul 25 04:59:55 PM PDT 24 Jul 25 05:00:11 PM PDT 24 38777800 ps
T1243 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1910933355 Jul 25 05:00:06 PM PDT 24 Jul 25 05:01:05 PM PDT 24 1297170900 ps
T1244 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2114843660 Jul 25 05:00:10 PM PDT 24 Jul 25 05:00:26 PM PDT 24 32417300 ps
T353 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.321565162 Jul 25 05:00:20 PM PDT 24 Jul 25 05:07:56 PM PDT 24 427632600 ps
T1245 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2553015547 Jul 25 05:00:08 PM PDT 24 Jul 25 05:00:26 PM PDT 24 119713000 ps
T1246 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1320334070 Jul 25 05:00:32 PM PDT 24 Jul 25 05:00:49 PM PDT 24 527973200 ps
T1247 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1868480555 Jul 25 05:00:21 PM PDT 24 Jul 25 05:06:47 PM PDT 24 441141300 ps
T1248 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3171762420 Jul 25 05:00:23 PM PDT 24 Jul 25 05:01:24 PM PDT 24 1474612700 ps
T346 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.256806794 Jul 25 05:00:20 PM PDT 24 Jul 25 05:12:58 PM PDT 24 1387163900 ps
T1249 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3001707602 Jul 25 05:00:28 PM PDT 24 Jul 25 05:00:44 PM PDT 24 47542500 ps
T1250 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2657602261 Jul 25 05:00:25 PM PDT 24 Jul 25 05:00:42 PM PDT 24 514203800 ps
T1251 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3538170002 Jul 25 04:59:52 PM PDT 24 Jul 25 05:00:08 PM PDT 24 14100100 ps
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