Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	95.24	93.90	98.31	92.52	97.14	96.89	98.18

Total test records in report: 1257

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1252	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1779684004			Jul 25 05:00:18 PM PDT 24	Jul 25 05:00:34 PM PDT 24	15010300 ps
T1253	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1238456568			Jul 25 05:00:08 PM PDT 24	Jul 25 05:00:22 PM PDT 24	36735700 ps
T348	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1459680894			Jul 25 04:59:59 PM PDT 24	Jul 25 05:07:36 PM PDT 24	583577400 ps
T1254	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4292451152			Jul 25 05:00:24 PM PDT 24	Jul 25 05:00:40 PM PDT 24	36619900 ps
T1255	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3108597847			Jul 25 05:00:24 PM PDT 24	Jul 25 05:00:43 PM PDT 24	56664600 ps
T1256	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3548000601			Jul 25 05:00:07 PM PDT 24	Jul 25 05:00:26 PM PDT 24	58202900 ps
T1257	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.106580959			Jul 25 05:00:29 PM PDT 24	Jul 25 05:00:46 PM PDT 24	38327700 ps

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.364214827
Short name	T4
Test name
Test status
Simulation time	1078138000 ps
CPU time	470.05 seconds
Started	Jul 25 05:08:36 PM PDT 24
Finished	Jul 25 05:16:26 PM PDT 24
Peak memory	262932 kb
Host	smart-22c9cefe-360c-446c-a729-7a963ababb75
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=364214827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.364214827
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.2844479413
Short name	T11
Test name
Test status
Simulation time	135559105300 ps
CPU time	1003.15 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:22:58 PM PDT 24
Peak memory	261232 kb
Host	smart-241655fc-4c4f-4f34-80e9-013823f166c1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844479413 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2844479413
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4121371641
Short name	T225
Test name
Test status
Simulation time	812838800 ps
CPU time	382.21 seconds
Started	Jul 25 05:00:05 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	264084 kb
Host	smart-857cd8cc-3e87-4a51-a21e-d22109ba39cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121371641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _tl_intg_err.4121371641
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.2083189938
Short name	T19
Test name
Test status
Simulation time	34083900 ps
CPU time	29.03 seconds
Started	Jul 25 05:09:46 PM PDT 24
Finished	Jul 25 05:10:16 PM PDT 24
Peak memory	275340 kb
Host	smart-866115a1-869b-4ad9-baa0-dee3870ec1a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083189938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.2083189938
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.2867415265
Short name	T70
Test name
Test status
Simulation time	19365273300 ps
CPU time	297.95 seconds
Started	Jul 25 05:06:45 PM PDT 24
Finished	Jul 25 05:11:43 PM PDT 24
Peak memory	274668 kb
Host	smart-d2d0839d-54fe-44b0-8005-d30d864cc697
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867415265 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.2867415265
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2744342761
Short name	T65
Test name
Test status
Simulation time	2864824200 ps
CPU time	59.02 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:01:10 PM PDT 24
Peak memory	261664 kb
Host	smart-4a43127e-46f9-465f-b77e-f21fca2e72f8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744342761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.2744342761
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.2184113276
Short name	T14
Test name
Test status
Simulation time	7219871100 ps
CPU time	4779.07 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 06:26:23 PM PDT 24
Peak memory	283860 kb
Host	smart-5c63a073-f1df-4caf-8627-3d6225a81c5c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184113276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2184113276
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd.2273479121
Short name	T6
Test name
Test status
Simulation time	2974168100 ps
CPU time	155.61 seconds
Started	Jul 25 05:08:52 PM PDT 24
Finished	Jul 25 05:11:28 PM PDT 24
Peak memory	284556 kb
Host	smart-20d533bb-5aa1-4dd7-b0d8-9a8376722db7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273479121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla sh_ctrl_intr_rd.2273479121
Directory	/workspace/24.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.3328683621
Short name	T55
Test name
Test status
Simulation time	5397043400 ps
CPU time	444.73 seconds
Started	Jul 25 05:05:51 PM PDT 24
Finished	Jul 25 05:13:16 PM PDT 24
Peak memory	263180 kb
Host	smart-ff416dc5-ea16-4da0-afa7-2f61527833c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3328683621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3328683621
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2698002857
Short name	T149
Test name
Test status
Simulation time	80136193200 ps
CPU time	851.76 seconds
Started	Jul 25 05:07:11 PM PDT 24
Finished	Jul 25 05:21:23 PM PDT 24
Peak memory	264852 kb
Host	smart-a5ec4617-6bde-48db-a5e5-1d8ca409ee4e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698002857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.2698002857
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1199530232
Short name	T31
Test name
Test status
Simulation time	12364532500 ps
CPU time	266.07 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:13:26 PM PDT 24
Peak memory	292724 kb
Host	smart-dd0c8084-875d-4cff-915e-bbfc0fe95010
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199530232 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1199530232
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.988006428
Short name	T115
Test name
Test status
Simulation time	112577500 ps
CPU time	19.95 seconds
Started	Jul 25 05:00:19 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	264064 kb
Host	smart-fd7e8a89-07db-4e51-ab53-b12819873aa0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988006428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.988006428
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.2743228407
Short name	T73
Test name
Test status
Simulation time	199741000 ps
CPU time	130.92 seconds
Started	Jul 25 05:10:29 PM PDT 24
Finished	Jul 25 05:12:40 PM PDT 24
Peak memory	260168 kb
Host	smart-dfffb39c-30d2-4091-890a-bc9832b0ac9b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743228407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o tp_reset.2743228407
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.2937297339
Short name	T68
Test name
Test status
Simulation time	1338125800 ps
CPU time	74.71 seconds
Started	Jul 25 05:06:09 PM PDT 24
Finished	Jul 25 05:07:24 PM PDT 24
Peak memory	260472 kb
Host	smart-c270630b-31d7-485b-a2b3-c1eccd4bae6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937297339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2937297339
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.1202045446
Short name	T21
Test name
Test status
Simulation time	1236313800 ps
CPU time	67.22 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	263584 kb
Host	smart-f8f6b9fe-5346-442b-9e77-d7ad46095f02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202045446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1202045446
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.1088022419
Short name	T394
Test name
Test status
Simulation time	336860600 ps
CPU time	132.68 seconds
Started	Jul 25 05:10:28 PM PDT 24
Finished	Jul 25 05:12:41 PM PDT 24
Peak memory	260048 kb
Host	smart-2a9db8e4-0574-4acc-839f-44297e6241f5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088022419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.1088022419
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.377068264
Short name	T34
Test name
Test status
Simulation time	67276000 ps
CPU time	30.91 seconds
Started	Jul 25 05:07:39 PM PDT 24
Finished	Jul 25 05:08:10 PM PDT 24
Peak memory	275316 kb
Host	smart-1d23264c-6a3f-404a-8ded-120c34258423
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377068264 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.377068264
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.695625968
Short name	T138
Test name
Test status
Simulation time	3564415200 ps
CPU time	575.69 seconds
Started	Jul 25 05:06:09 PM PDT 24
Finished	Jul 25 05:15:44 PM PDT 24
Peak memory	314304 kb
Host	smart-dae52b7f-3c6a-4c20-94d1-db9dea4a231a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695625968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.695625968
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2716926735
Short name	T246
Test name
Test status
Simulation time	17323300 ps
CPU time	14.32 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	261272 kb
Host	smart-3a9e8ab7-7229-431b-b906-45a4e3d3112f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716926735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test. 2716926735
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.226696973
Short name	T595
Test name
Test status
Simulation time	660108400 ps
CPU time	130.86 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:10:44 PM PDT 24
Peak memory	260896 kb
Host	smart-146e4c42-1084-442e-861e-e54cbc47ce20
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226696973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ot p_reset.226696973
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.1983533758
Short name	T7
Test name
Test status
Simulation time	13676000 ps
CPU time	13.85 seconds
Started	Jul 25 05:06:18 PM PDT 24
Finished	Jul 25 05:06:32 PM PDT 24
Peak memory	264932 kb
Host	smart-7e10753a-520d-47de-a04f-43193ec1a37d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983533758 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1983533758
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1379097294
Short name	T10
Test name
Test status
Simulation time	233378637400 ps
CPU time	2519.45 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:48:32 PM PDT 24
Peak memory	263800 kb
Host	smart-46c5b93d-f1bf-49eb-8f4e-b949bf06c430
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379097294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.1379097294
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3817767301
Short name	T170
Test name
Test status
Simulation time	10035138800 ps
CPU time	59.37 seconds
Started	Jul 25 05:08:39 PM PDT 24
Finished	Jul 25 05:09:38 PM PDT 24
Peak memory	292732 kb
Host	smart-7b2bd4fd-77f9-4b69-b80c-6fb218d02e1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817767301 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3817767301
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.2497459490
Short name	T38
Test name
Test status
Simulation time	25075100 ps
CPU time	13.85 seconds
Started	Jul 25 05:09:02 PM PDT 24
Finished	Jul 25 05:09:16 PM PDT 24
Peak memory	257888 kb
Host	smart-b32d275e-7ac5-4e71-b6c5-1564f2cad653
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497459490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 2497459490
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2214980418
Short name	T299
Test name
Test status
Simulation time	7667867400 ps
CPU time	250.39 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:14:11 PM PDT 24
Peak memory	260716 kb
Host	smart-1fb8fc52-3141-4c20-9771-5a8d35db4e3e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214980418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.2214980418
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.2757270452
Short name	T45
Test name
Test status
Simulation time	2348885600 ps
CPU time	31.16 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:07:39 PM PDT 24
Peak memory	262320 kb
Host	smart-36809a50-6a33-4569-ab78-43facfe50163
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757270452 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2757270452
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.948628799
Short name	T77
Test name
Test status
Simulation time	23303500 ps
CPU time	14.27 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:06:46 PM PDT 24
Peak memory	262492 kb
Host	smart-efa700c0-1460-494a-b77f-827033eafd16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948628799 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.948628799
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.249989581
Short name	T49
Test name
Test status
Simulation time	639344000 ps
CPU time	140.37 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:09:48 PM PDT 24
Peak memory	281568 kb
Host	smart-6c3b7406-b27c-4d8e-a519-e1977cb97b9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 249989581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.249989581
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.3935981305
Short name	T79
Test name
Test status
Simulation time	10773992900 ps
CPU time	72 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:06:53 PM PDT 24
Peak memory	260292 kb
Host	smart-3365f3b2-3f03-4eee-bc4f-b35269286b49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935981305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3935981305
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.204541139
Short name	T176
Test name
Test status
Simulation time	39539300 ps
CPU time	133.1 seconds
Started	Jul 25 05:09:49 PM PDT 24
Finished	Jul 25 05:12:02 PM PDT 24
Peak memory	259964 kb
Host	smart-2d165be5-effd-4445-9f6f-a86ccf2b238c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204541139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot p_reset.204541139
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.3079725800
Short name	T76
Test name
Test status
Simulation time	976383600 ps
CPU time	68.82 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:07:50 PM PDT 24
Peak memory	260480 kb
Host	smart-a1b1c6a1-528d-4e52-a109-1eb2a0ae2e3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079725800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3079725800
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.1362998424
Short name	T44
Test name
Test status
Simulation time	112283498900 ps
CPU time	2756.44 seconds
Started	Jul 25 05:06:23 PM PDT 24
Finished	Jul 25 05:52:19 PM PDT 24
Peak memory	261676 kb
Host	smart-a292a191-d199-43f5-998a-d9ccc6a6187f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362998424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.1362998424
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.3439894477
Short name	T367
Test name
Test status
Simulation time	6045188400 ps
CPU time	743.41 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:19:16 PM PDT 24
Peak memory	320512 kb
Host	smart-c0e25045-c123-4937-b668-4658e2228f3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439894477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s err.3439894477
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.2956168902
Short name	T92
Test name
Test status
Simulation time	238871600 ps
CPU time	31.56 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:07:03 PM PDT 24
Peak memory	276360 kb
Host	smart-916050d4-f9a6-4dcd-ab22-ea7c960e2b6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956168902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_re_evict.2956168902
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2241998228
Short name	T257
Test name
Test status
Simulation time	788007700 ps
CPU time	894.09 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:15:03 PM PDT 24
Peak memory	264096 kb
Host	smart-fcda6e6a-8f48-427a-9847-a319eb3feb04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241998228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.2241998228
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2701666091
Short name	T276
Test name
Test status
Simulation time	26502300 ps
CPU time	13.51 seconds
Started	Jul 25 05:08:27 PM PDT 24
Finished	Jul 25 05:08:40 PM PDT 24
Peak memory	259544 kb
Host	smart-af6294bd-3475-4b24-b214-f138e483516e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701666091 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2701666091
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.8056991
Short name	T226
Test name
Test status
Simulation time	62344200 ps
CPU time	20.38 seconds
Started	Jul 25 05:00:10 PM PDT 24
Finished	Jul 25 05:00:31 PM PDT 24
Peak memory	264044 kb
Host	smart-69822da3-80ec-4020-8149-0312d3134db5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8056991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.8056991
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.767923632
Short name	T95
Test name
Test status
Simulation time	1844744500 ps
CPU time	2351.83 seconds
Started	Jul 25 05:05:42 PM PDT 24
Finished	Jul 25 05:44:54 PM PDT 24
Peak memory	264744 kb
Host	smart-e746d2fb-832a-43ef-a8d2-4e9607b31d32
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767923632 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_error_prog_type.767923632
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.459033831
Short name	T231
Test name
Test status
Simulation time	34882200 ps
CPU time	13.47 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:05 PM PDT 24
Peak memory	263048 kb
Host	smart-6993f2de-7cfe-43e4-b3ac-e1e2deb2a67e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459033831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_mem_partial_access.459033831
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3413699622
Short name	T207
Test name
Test status
Simulation time	62302800 ps
CPU time	13.66 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:08:47 PM PDT 24
Peak memory	259752 kb
Host	smart-63a54861-6a96-474f-a68c-1b8a35d32b68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413699622 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3413699622
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.4275514728
Short name	T156
Test name
Test status
Simulation time	11651235200 ps
CPU time	67.87 seconds
Started	Jul 25 05:08:05 PM PDT 24
Finished	Jul 25 05:09:13 PM PDT 24
Peak memory	263512 kb
Host	smart-e002da8b-9a70-41cc-b73a-e014992eda30
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275514728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.4 275514728
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.2255837340
Short name	T9
Test name
Test status
Simulation time	45451500 ps
CPU time	15.19 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:06:04 PM PDT 24
Peak memory	264480 kb
Host	smart-2b7bf9be-fe52-4539-8813-187356d01fe9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255837340 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.2255837340
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.909992282
Short name	T94
Test name
Test status
Simulation time	701953500 ps
CPU time	42.25 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:06:57 PM PDT 24
Peak memory	264632 kb
Host	smart-bd788e9a-67c2-44a6-81e6-1c3e77e0ba3b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909992282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_fs_sup.909992282
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3618950180
Short name	T245
Test name
Test status
Simulation time	27530500 ps
CPU time	13.63 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:21 PM PDT 24
Peak memory	261348 kb
Host	smart-3144d02e-3318-4142-89a3-7427eaf1f7f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618950180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3 618950180
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3071651968
Short name	T87
Test name
Test status
Simulation time	795154100 ps
CPU time	21.55 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:06:56 PM PDT 24
Peak memory	265264 kb
Host	smart-343ef78e-1e97-42d2-95de-b390986fae41
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071651968 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3071651968
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.3831709809
Short name	T188
Test name
Test status
Simulation time	14146100 ps
CPU time	20.54 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:09:30 PM PDT 24
Peak memory	273888 kb
Host	smart-06fae1c7-0d1e-4ec1-8380-0a825d2a12f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831709809 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.3831709809
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3864392779
Short name	T167
Test name
Test status
Simulation time	40121290600 ps
CPU time	806.03 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:22:00 PM PDT 24
Peak memory	264560 kb
Host	smart-486dda54-951f-4b1b-9e7e-8eefa51d9c54
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864392779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.3864392779
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.4207210685
Short name	T27
Test name
Test status
Simulation time	188840800 ps
CPU time	14.28 seconds
Started	Jul 25 05:06:13 PM PDT 24
Finished	Jul 25 05:06:28 PM PDT 24
Peak memory	261428 kb
Host	smart-2946e459-3f1c-4195-8631-476aee73445e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4207210685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.4207210685
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.256806794
Short name	T346
Test name
Test status
Simulation time	1387163900 ps
CPU time	757.83 seconds
Started	Jul 25 05:00:20 PM PDT 24
Finished	Jul 25 05:12:58 PM PDT 24
Peak memory	264032 kb
Host	smart-a391b7b5-d3cf-48dc-a481-c720cac86443
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256806794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ tl_intg_err.256806794
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.851573886
Short name	T512
Test name
Test status
Simulation time	1597592500 ps
CPU time	243.35 seconds
Started	Jul 25 05:12:28 PM PDT 24
Finished	Jul 25 05:16:31 PM PDT 24
Peak memory	281540 kb
Host	smart-55533054-72b2-4bc1-8263-9f504d4e3c88
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851573886 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.851573886
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.2773390739
Short name	T108
Test name
Test status
Simulation time	124307000 ps
CPU time	13.79 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:10:01 PM PDT 24
Peak memory	282832 kb
Host	smart-f1b897d4-341e-4519-9ff2-24dade7ad24b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773390739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2773390739
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.481140923
Short name	T286
Test name
Test status
Simulation time	72071300 ps
CPU time	31.54 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:24 PM PDT 24
Peak memory	263724 kb
Host	smart-416bc667-5fea-4899-9e37-0fe8505aaf21
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481140923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.flash_ctrl_csr_hw_reset.481140923
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.3182445968
Short name	T329
Test name
Test status
Simulation time	74649200 ps
CPU time	33.88 seconds
Started	Jul 25 05:06:13 PM PDT 24
Finished	Jul 25 05:06:47 PM PDT 24
Peak memory	275356 kb
Host	smart-c45f1d45-b473-4f34-ad96-750e8c577eec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182445968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_re_evict.3182445968
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1084395915
Short name	T251
Test name
Test status
Simulation time	2172128700 ps
CPU time	900.58 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:15:10 PM PDT 24
Peak memory	264184 kb
Host	smart-4d70be3d-a11c-4871-9e61-64a79f10b755
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084395915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.1084395915
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.1952410576
Short name	T334
Test name
Test status
Simulation time	65840300 ps
CPU time	30.04 seconds
Started	Jul 25 05:07:25 PM PDT 24
Finished	Jul 25 05:07:55 PM PDT 24
Peak memory	275320 kb
Host	smart-05232390-8f35-40d1-8954-da320ad3193f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952410576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_rw_evict.1952410576
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.3489054687
Short name	T355
Test name
Test status
Simulation time	1054008500 ps
CPU time	62.71 seconds
Started	Jul 25 05:07:41 PM PDT 24
Finished	Jul 25 05:08:44 PM PDT 24
Peak memory	263548 kb
Host	smart-a49e07b2-bd5f-4753-8fdf-b2c2b9485cc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489054687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3489054687
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.2175141404
Short name	T882
Test name
Test status
Simulation time	120467500 ps
CPU time	13.67 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:04 PM PDT 24
Peak memory	264808 kb
Host	smart-8343a383-b41e-419a-b60e-d860c69c4097
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175141404 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.2175141404
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.130483064
Short name	T273
Test name
Test status
Simulation time	10070147600 ps
CPU time	38.82 seconds
Started	Jul 25 05:07:29 PM PDT 24
Finished	Jul 25 05:08:08 PM PDT 24
Peak memory	265292 kb
Host	smart-0c7379bc-20a7-4a26-8ee7-e951c8699708
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130483064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.130483064
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1427402004
Short name	T274
Test name
Test status
Simulation time	10025235800 ps
CPU time	124.03 seconds
Started	Jul 25 05:08:25 PM PDT 24
Finished	Jul 25 05:10:29 PM PDT 24
Peak memory	279460 kb
Host	smart-30e2fb61-9a5c-4ff9-a5c9-6b0ec756448d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427402004 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1427402004
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.1565622465
Short name	T89
Test name
Test status
Simulation time	870339700 ps
CPU time	19.47 seconds
Started	Jul 25 05:06:00 PM PDT 24
Finished	Jul 25 05:06:20 PM PDT 24
Peak memory	262884 kb
Host	smart-96472eb9-78c2-4386-a246-65b6459804e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565622465 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1565622465
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.266672301
Short name	T325
Test name
Test status
Simulation time	2937842000 ps
CPU time	213.13 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:10:44 PM PDT 24
Peak memory	284464 kb
Host	smart-60c6f512-0a19-40d2-bd30-71acd913f764
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266672301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_intr_rd.266672301
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.1235664241
Short name	T17
Test name
Test status
Simulation time	73491200 ps
CPU time	30.95 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:07:30 PM PDT 24
Peak memory	268200 kb
Host	smart-4616f7fe-e82e-49a5-8d7e-253b7d40f52e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235664241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.1235664241
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1116101622
Short name	T1186
Test name
Test status
Simulation time	73276900 ps
CPU time	20.47 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:27 PM PDT 24
Peak memory	264076 kb
Host	smart-3b4517bf-7818-4bfb-ade2-7fcc2e0c020f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116101622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1 116101622
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1551035255
Short name	T682
Test name
Test status
Simulation time	30449500 ps
CPU time	13.52 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:04 PM PDT 24
Peak memory	264472 kb
Host	smart-5d645dfa-3457-46e1-8a0e-2a2400f150c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551035255 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1551035255
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2074812098
Short name	T227
Test name
Test status
Simulation time	535752300 ps
CPU time	880.45 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:14:48 PM PDT 24
Peak memory	261540 kb
Host	smart-b7e57837-b1c8-43c9-b35d-ce5ed2cd9dde
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074812098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.2074812098
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.3974721714
Short name	T318
Test name
Test status
Simulation time	1568488200 ps
CPU time	244.79 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:11:21 PM PDT 24
Peak memory	284728 kb
Host	smart-a763bd5e-55c1-48f7-a72b-a3106aabd689
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974721714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.3974721714
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.629260536
Short name	T415
Test name
Test status
Simulation time	4856895500 ps
CPU time	64.14 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:08:32 PM PDT 24
Peak memory	262820 kb
Host	smart-45d6a3e2-2f8d-42e6-b83d-2e70004145fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629260536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.629260536
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.2346099143
Short name	T419
Test name
Test status
Simulation time	993935900 ps
CPU time	84.91 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:07:49 PM PDT 24
Peak memory	260688 kb
Host	smart-a73381e3-f8b2-4ba1-bad8-75377711605c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346099143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2346099143
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.1306560324
Short name	T403
Test name
Test status
Simulation time	440313100 ps
CPU time	56.05 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:07:37 PM PDT 24
Peak memory	262900 kb
Host	smart-7ffc88c0-0399-48a4-a834-fddeceb4d98b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306560324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1306560324
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.1403390387
Short name	T400
Test name
Test status
Simulation time	8403550100 ps
CPU time	84.97 seconds
Started	Jul 25 05:10:18 PM PDT 24
Finished	Jul 25 05:11:43 PM PDT 24
Peak memory	263020 kb
Host	smart-baf7db1e-a885-45a5-8583-7402e1f9a5e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403390387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1403390387
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.3200877906
Short name	T405
Test name
Test status
Simulation time	710301200 ps
CPU time	49.59 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:07:42 PM PDT 24
Peak memory	264748 kb
Host	smart-46a56d02-a9f8-4540-8f09-81af6ce11cb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200877906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3200877906
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.2756837928
Short name	T46
Test name
Test status
Simulation time	1120386500 ps
CPU time	23.56 seconds
Started	Jul 25 05:05:40 PM PDT 24
Finished	Jul 25 05:06:03 PM PDT 24
Peak memory	262260 kb
Host	smart-3ccc69bd-2c33-4718-9f41-bb9466ef34aa
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756837928 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2756837928
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2109460421
Short name	T810
Test name
Test status
Simulation time	84104200 ps
CPU time	31.34 seconds
Started	Jul 25 05:09:05 PM PDT 24
Finished	Jul 25 05:09:36 PM PDT 24
Peak memory	275352 kb
Host	smart-321e3bd2-64d1-4935-82a1-3b7c705cc4c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109460421 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2109460421
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3862017254
Short name	T644
Test name
Test status
Simulation time	13888991900 ps
CPU time	161.78 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:12:29 PM PDT 24
Peak memory	290652 kb
Host	smart-941fd5e3-efec-4667-a2de-cf9255a3e2e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862017254 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3862017254
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.1301896723
Short name	T202
Test name
Test status
Simulation time	3485532800 ps
CPU time	557.5 seconds
Started	Jul 25 05:06:17 PM PDT 24
Finished	Jul 25 05:15:35 PM PDT 24
Peak memory	314196 kb
Host	smart-a5f2504c-0048-443d-a251-dce2d720bb5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301896723 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_rw_derr.1301896723
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1685508958
Short name	T60
Test name
Test status
Simulation time	46092100 ps
CPU time	14.21 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:06:58 PM PDT 24
Peak memory	276648 kb
Host	smart-c78ac313-cf00-48bf-a946-0731e51b6f31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1685508958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.1685508958
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.3115823732
Short name	T137
Test name
Test status
Simulation time	20271200 ps
CPU time	13.81 seconds
Started	Jul 25 05:06:49 PM PDT 24
Finished	Jul 25 05:07:03 PM PDT 24
Peak memory	261008 kb
Host	smart-4134a0d0-ce08-4826-8798-60ff505892fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115823732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_config_regwen.3115823732
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.1490499499
Short name	T86
Test name
Test status
Simulation time	755552100 ps
CPU time	17.99 seconds
Started	Jul 25 05:06:12 PM PDT 24
Finished	Jul 25 05:06:31 PM PDT 24
Peak memory	265320 kb
Host	smart-1b9e8b55-c9cb-4800-b251-47fa2c4c2051
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490499499 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.1490499499
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.1737971781
Short name	T203
Test name
Test status
Simulation time	7259441700 ps
CPU time	750.81 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:19:30 PM PDT 24
Peak memory	322852 kb
Host	smart-27c0ef75-f46a-4594-bb53-bc2442fabbf3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737971781 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_rw_derr.1737971781
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2727188820
Short name	T272
Test name
Test status
Simulation time	10109745200 ps
CPU time	37.58 seconds
Started	Jul 25 05:05:51 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	265128 kb
Host	smart-561abac4-1187-44f5-8a4a-b5cb7f6b4da2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727188820 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2727188820
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.2168531571
Short name	T104
Test name
Test status
Simulation time	12859100 ps
CPU time	20.75 seconds
Started	Jul 25 05:09:52 PM PDT 24
Finished	Jul 25 05:10:13 PM PDT 24
Peak memory	273072 kb
Host	smart-d2ed46f8-dcae-4877-8b74-392229132825
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168531571 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.2168531571
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.4098234070
Short name	T362
Test name
Test status
Simulation time	10782700 ps
CPU time	21.86 seconds
Started	Jul 25 05:05:58 PM PDT 24
Finished	Jul 25 05:06:20 PM PDT 24
Peak memory	273300 kb
Host	smart-8b90e337-3bf8-49b1-a9c1-c490d0c13afd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098234070 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.4098234070
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.467876704
Short name	T523
Test name
Test status
Simulation time	1787386600 ps
CPU time	26.28 seconds
Started	Jul 25 05:06:03 PM PDT 24
Finished	Jul 25 05:06:30 PM PDT 24
Peak memory	264920 kb
Host	smart-5b8a96c1-6214-45dd-9ce1-f9399974e998
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467876704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_prog_reset.467876704
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.2419078558
Short name	T105
Test name
Test status
Simulation time	25074200 ps
CPU time	21.04 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:07:48 PM PDT 24
Peak memory	273232 kb
Host	smart-d56e6a04-f06d-487d-8474-4ad56e3cb649
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419078558 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.2419078558
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.4069908961
Short name	T360
Test name
Test status
Simulation time	10004900 ps
CPU time	22.31 seconds
Started	Jul 25 05:07:49 PM PDT 24
Finished	Jul 25 05:08:11 PM PDT 24
Peak memory	273280 kb
Host	smart-0799218c-23e7-473b-857a-a66cef927beb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069908961 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.4069908961
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.1829690331
Short name	T395
Test name
Test status
Simulation time	20393700 ps
CPU time	22.23 seconds
Started	Jul 25 05:07:58 PM PDT 24
Finished	Jul 25 05:08:20 PM PDT 24
Peak memory	273468 kb
Host	smart-4dc2e07e-8f0f-46bc-a4e4-31a4ab2c272f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829690331 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.1829690331
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.447852179
Short name	T390
Test name
Test status
Simulation time	13860900 ps
CPU time	21.56 seconds
Started	Jul 25 05:09:01 PM PDT 24
Finished	Jul 25 05:09:23 PM PDT 24
Peak memory	273420 kb
Host	smart-cbe58df0-116d-4642-9ec3-4c2dd8a82292
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447852179 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.447852179
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.2814567530
Short name	T356
Test name
Test status
Simulation time	15781300 ps
CPU time	21.7 seconds
Started	Jul 25 05:09:19 PM PDT 24
Finished	Jul 25 05:09:40 PM PDT 24
Peak memory	273184 kb
Host	smart-8f919413-ca17-4c6c-be98-9d05b14e5a57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814567530 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.2814567530
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.3158688270
Short name	T1092
Test name
Test status
Simulation time	25790200 ps
CPU time	20.36 seconds
Started	Jul 25 05:09:26 PM PDT 24
Finished	Jul 25 05:09:46 PM PDT 24
Peak memory	273356 kb
Host	smart-1cd90670-bd44-4f5e-8a1d-5a8e0effa990
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158688270 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.3158688270
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.1614054911
Short name	T144
Test name
Test status
Simulation time	58698006400 ps
CPU time	4514.65 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 06:20:56 PM PDT 24
Peak memory	265052 kb
Host	smart-60338a10-a951-4947-a262-48ce399df162
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614054911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.1614054911
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.1909602368
Short name	T463
Test name
Test status
Simulation time	8466365400 ps
CPU time	72.66 seconds
Started	Jul 25 05:05:51 PM PDT 24
Finished	Jul 25 05:07:03 PM PDT 24
Peak memory	261236 kb
Host	smart-c7beb3b1-b1e4-4261-8f8c-204941778b56
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909602368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_intr_wr.1909602368
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.4266453947
Short name	T262
Test name
Test status
Simulation time	1452282300 ps
CPU time	123.68 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:07:45 PM PDT 24
Peak memory	262536 kb
Host	smart-0a17cb83-3267-4540-bfa7-f6141958a66d
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4266453947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.4266453947
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.702531759
Short name	T69
Test name
Test status
Simulation time	9061981700 ps
CPU time	2330.9 seconds
Started	Jul 25 05:06:08 PM PDT 24
Finished	Jul 25 05:44:59 PM PDT 24
Peak memory	262616 kb
Host	smart-7e4f6805-0e4a-462c-8eda-386d81eab9e1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=702531759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.702531759
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2527847975
Short name	T429
Test name
Test status
Simulation time	3252043600 ps
CPU time	55.61 seconds
Started	Jul 25 05:07:39 PM PDT 24
Finished	Jul 25 05:08:34 PM PDT 24
Peak memory	260844 kb
Host	smart-861ab369-2f77-4622-89c5-a8ed01594db2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527847975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ hw_sec_otp.2527847975
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.829205673
Short name	T244
Test name
Test status
Simulation time	97609200 ps
CPU time	18.52 seconds
Started	Jul 25 04:59:57 PM PDT 24
Finished	Jul 25 05:00:16 PM PDT 24
Peak memory	264072 kb
Host	smart-663f02b3-ead6-48b6-91af-bd2f5d81d499
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829205673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.829205673
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2283326911
Short name	T249
Test name
Test status
Simulation time	2506317900 ps
CPU time	458.75 seconds
Started	Jul 25 05:00:20 PM PDT 24
Finished	Jul 25 05:07:59 PM PDT 24
Peak memory	264124 kb
Host	smart-dd2dbabf-49be-4685-877c-ef94b1dfe23e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283326911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.2283326911
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.169771794
Short name	T24
Test name
Test status
Simulation time	17446100 ps
CPU time	13.78 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:04 PM PDT 24
Peak memory	264536 kb
Host	smart-d9a86652-ddae-45a6-a336-5cafdc748fed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169771794 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.169771794
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.3014103672
Short name	T515
Test name
Test status
Simulation time	3208109700 ps
CPU time	1031.42 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:22:53 PM PDT 24
Peak memory	270288 kb
Host	smart-39310c00-ea38-4468-9747-304aaf664c18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014103672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3014103672
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.2500239913
Short name	T548
Test name
Test status
Simulation time	122913100 ps
CPU time	28.79 seconds
Started	Jul 25 05:06:07 PM PDT 24
Finished	Jul 25 05:06:36 PM PDT 24
Peak memory	268080 kb
Host	smart-fa0610eb-4987-49c0-9bad-43d91ece82e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500239913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_rd_intg.2500239913
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.4034251900
Short name	T59
Test name
Test status
Simulation time	1634792800 ps
CPU time	4728.33 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 06:25:21 PM PDT 24
Peak memory	289252 kb
Host	smart-b1b4277f-1473-4856-8d75-ac502787e06e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034251900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4034251900
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.826704333
Short name	T90
Test name
Test status
Simulation time	811643300 ps
CPU time	18.53 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:07:03 PM PDT 24
Peak memory	262768 kb
Host	smart-0aca7ecd-2005-447c-a49c-c0ca8bdc7937
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826704333 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.826704333
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2777057777
Short name	T1240
Test name
Test status
Simulation time	3281218900 ps
CPU time	66.49 seconds
Started	Jul 25 05:00:03 PM PDT 24
Finished	Jul 25 05:01:13 PM PDT 24
Peak memory	261520 kb
Host	smart-a9e1e437-65eb-476c-a35a-4f694d638a36
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777057777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.2777057777
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1641037622
Short name	T1224
Test name
Test status
Simulation time	3208125200 ps
CPU time	82.49 seconds
Started	Jul 25 04:59:49 PM PDT 24
Finished	Jul 25 05:01:12 PM PDT 24
Peak memory	261692 kb
Host	smart-e37d0d2e-57e6-49dd-a957-b646e268d400
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641037622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_bit_bash.1641037622
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.926194051
Short name	T1212
Test name
Test status
Simulation time	19874000 ps
CPU time	31.05 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	263444 kb
Host	smart-d0906e2c-932e-4e5c-9290-b8866c4f6289
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926194051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.flash_ctrl_csr_hw_reset.926194051
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3449216716
Short name	T1223
Test name
Test status
Simulation time	48020400 ps
CPU time	14.91 seconds
Started	Jul 25 05:00:00 PM PDT 24
Finished	Jul 25 05:00:15 PM PDT 24
Peak memory	270880 kb
Host	smart-0b649850-429c-4841-96bc-9c539c8d86f8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449216716 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3449216716
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1850438593
Short name	T1176
Test name
Test status
Simulation time	57031400 ps
CPU time	16.49 seconds
Started	Jul 25 04:59:51 PM PDT 24
Finished	Jul 25 05:00:08 PM PDT 24
Peak memory	264076 kb
Host	smart-1d06b034-ccd7-47d4-befa-8d13849042fc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850438593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1850438593
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2680913161
Short name	T1171
Test name
Test status
Simulation time	44541700 ps
CPU time	13.51 seconds
Started	Jul 25 04:59:51 PM PDT 24
Finished	Jul 25 05:00:05 PM PDT 24
Peak memory	261456 kb
Host	smart-fc7908ec-ab19-4c80-b40d-5a243b0f7de4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680913161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2 680913161
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3583469883
Short name	T235
Test name
Test status
Simulation time	42095100 ps
CPU time	13.68 seconds
Started	Jul 25 04:59:50 PM PDT 24
Finished	Jul 25 05:00:04 PM PDT 24
Peak memory	262900 kb
Host	smart-793c211e-ac4e-4144-a7e0-f245ca6aace9
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583469883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.3583469883
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2191715980
Short name	T1207
Test name
Test status
Simulation time	29889800 ps
CPU time	13.36 seconds
Started	Jul 25 04:59:55 PM PDT 24
Finished	Jul 25 05:00:08 PM PDT 24
Peak memory	261432 kb
Host	smart-89ab7732-add7-4ef2-93d2-f2fdd09b90a1
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191715980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.2191715980
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2717183160
Short name	T1160
Test name
Test status
Simulation time	908209000 ps
CPU time	20.95 seconds
Started	Jul 25 04:59:49 PM PDT 24
Finished	Jul 25 05:00:11 PM PDT 24
Peak memory	261704 kb
Host	smart-4db4db99-b40d-4669-bb0a-f7e98e24ae3b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717183160 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.2717183160
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2335783817
Short name	T1140
Test name
Test status
Simulation time	19055400 ps
CPU time	13.13 seconds
Started	Jul 25 04:59:57 PM PDT 24
Finished	Jul 25 05:00:10 PM PDT 24
Peak memory	253184 kb
Host	smart-b98929be-adb1-4f9a-a7f5-d62734f4eb37
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335783817 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2335783817
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.784641154
Short name	T1123
Test name
Test status
Simulation time	11815700 ps
CPU time	15.64 seconds
Started	Jul 25 04:59:53 PM PDT 24
Finished	Jul 25 05:00:09 PM PDT 24
Peak memory	253372 kb
Host	smart-ff471ee8-2984-4553-bab6-3ef143bb6723
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784641154 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.784641154
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1602010806
Short name	T1204
Test name
Test status
Simulation time	37409500 ps
CPU time	16.52 seconds
Started	Jul 25 04:59:47 PM PDT 24
Finished	Jul 25 05:00:04 PM PDT 24
Peak memory	264056 kb
Host	smart-2b07f1b0-dc1d-4c69-8527-f2aa91b35b88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602010806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1 602010806
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1459680894
Short name	T348
Test name
Test status
Simulation time	583577400 ps
CPU time	457.03 seconds
Started	Jul 25 04:59:59 PM PDT 24
Finished	Jul 25 05:07:36 PM PDT 24
Peak memory	264156 kb
Host	smart-cec2d521-9689-4a7b-92c3-c7d7f977f784
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459680894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _tl_intg_err.1459680894
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3956078840
Short name	T1196
Test name
Test status
Simulation time	2995672300 ps
CPU time	38.73 seconds
Started	Jul 25 04:59:55 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	261464 kb
Host	smart-6abaa725-0b06-44be-ac3b-7e8b6080376a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956078840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_aliasing.3956078840
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.142891805
Short name	T1141
Test name
Test status
Simulation time	2389118700 ps
CPU time	47.64 seconds
Started	Jul 25 05:00:02 PM PDT 24
Finished	Jul 25 05:00:54 PM PDT 24
Peak memory	261536 kb
Host	smart-9527e7d7-c25d-49aa-a58b-d5387bc81408
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142891805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.flash_ctrl_csr_bit_bash.142891805
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3871452309
Short name	T424
Test name
Test status
Simulation time	48849200 ps
CPU time	17.68 seconds
Started	Jul 25 04:59:59 PM PDT 24
Finished	Jul 25 05:00:17 PM PDT 24
Peak memory	272464 kb
Host	smart-6ca5a1de-71a4-4f0b-be3c-558617c2738a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871452309 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3871452309
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4041610911
Short name	T426
Test name
Test status
Simulation time	210954900 ps
CPU time	17.26 seconds
Started	Jul 25 05:00:20 PM PDT 24
Finished	Jul 25 05:00:38 PM PDT 24
Peak memory	264088 kb
Host	smart-bb0052db-b2cf-4106-a9e7-2ff1441412f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041610911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.4041610911
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2709028817
Short name	T1121
Test name
Test status
Simulation time	30017700 ps
CPU time	13.76 seconds
Started	Jul 25 04:59:55 PM PDT 24
Finished	Jul 25 05:00:09 PM PDT 24
Peak memory	261520 kb
Host	smart-498d12bf-17ad-4142-8066-5e210dd2b540
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709028817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2 709028817
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2278662477
Short name	T234
Test name
Test status
Simulation time	31778200 ps
CPU time	13.73 seconds
Started	Jul 25 05:00:06 PM PDT 24
Finished	Jul 25 05:00:20 PM PDT 24
Peak memory	262340 kb
Host	smart-4ecf85b4-222b-4a86-ad3a-f19b137eac87
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278662477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.2278662477
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3741366894
Short name	T1199
Test name
Test status
Simulation time	45020100 ps
CPU time	13.28 seconds
Started	Jul 25 05:00:06 PM PDT 24
Finished	Jul 25 05:00:20 PM PDT 24
Peak memory	261512 kb
Host	smart-07d9571c-c5d7-47b9-8545-125153bfc1cd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741366894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.3741366894
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1771050138
Short name	T1208
Test name
Test status
Simulation time	375655200 ps
CPU time	35.03 seconds
Started	Jul 25 05:00:03 PM PDT 24
Finished	Jul 25 05:00:43 PM PDT 24
Peak memory	262880 kb
Host	smart-157dcaee-1c67-423e-9ee9-774c552884f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771050138 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1771050138
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.590739625
Short name	T1238
Test name
Test status
Simulation time	22398600 ps
CPU time	15.57 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:08 PM PDT 24
Peak memory	253352 kb
Host	smart-509865a5-895d-40c9-9836-9160835c6a0e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590739625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.590739625
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.610202596
Short name	T1242
Test name
Test status
Simulation time	38777800 ps
CPU time	16.23 seconds
Started	Jul 25 04:59:55 PM PDT 24
Finished	Jul 25 05:00:11 PM PDT 24
Peak memory	253288 kb
Host	smart-737a92ec-52e1-4c3f-94b5-4626b42d3d33
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610202596 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.610202596
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.890958850
Short name	T352
Test name
Test status
Simulation time	291944100 ps
CPU time	466.82 seconds
Started	Jul 25 05:00:03 PM PDT 24
Finished	Jul 25 05:07:53 PM PDT 24
Peak memory	264116 kb
Host	smart-19f33f7c-8f98-48d0-857b-a20bd9722a00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890958850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ tl_intg_err.890958850
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.749342690
Short name	T1146
Test name
Test status
Simulation time	148246100 ps
CPU time	16.14 seconds
Started	Jul 25 05:00:05 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	271044 kb
Host	smart-438b001a-4685-4baf-8e6f-c0363bc85564
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749342690 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.749342690
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3773267686
Short name	T283
Test name
Test status
Simulation time	134949600 ps
CPU time	17.53 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	263984 kb
Host	smart-8dd8454d-43f7-429f-9ca4-7b507f4ac4ec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773267686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.3773267686
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3623337431
Short name	T312
Test name
Test status
Simulation time	53890500 ps
CPU time	13.99 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	261396 kb
Host	smart-648c941e-a07b-4b38-b297-930be4494266
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623337431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 3623337431
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2553015547
Short name	T1245
Test name
Test status
Simulation time	119713000 ps
CPU time	17.83 seconds
Started	Jul 25 05:00:08 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	262840 kb
Host	smart-bd660f4a-e8af-4fe8-9786-831aa00d16f7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553015547 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2553015547
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3636167887
Short name	T1118
Test name
Test status
Simulation time	15154200 ps
CPU time	15.72 seconds
Started	Jul 25 04:59:56 PM PDT 24
Finished	Jul 25 05:00:12 PM PDT 24
Peak memory	253176 kb
Host	smart-389be1d3-fd0f-4cf2-bca2-f295ee9bb5e0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636167887 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3636167887
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.768460285
Short name	T1178
Test name
Test status
Simulation time	56397700 ps
CPU time	15.69 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:27 PM PDT 24
Peak memory	253332 kb
Host	smart-74b2f38e-014a-4537-98b1-0e0716ae746a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768460285 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.768460285
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.4207255452
Short name	T1189
Test name
Test status
Simulation time	93514200 ps
CPU time	15.94 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	264012 kb
Host	smart-97c8f909-dea9-41ff-a232-9109df7acfb8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207255452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors. 4207255452
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3107446474
Short name	T284
Test name
Test status
Simulation time	55643300 ps
CPU time	17.25 seconds
Started	Jul 25 05:00:21 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	263292 kb
Host	smart-912ba96f-3a12-43c5-8360-f2a23270c219
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107446474 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3107446474
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3363280378
Short name	T1227
Test name
Test status
Simulation time	138343600 ps
CPU time	16.81 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	264040 kb
Host	smart-6628a797-cf9e-4b70-b104-5b55000c03aa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363280378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.3363280378
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2720188887
Short name	T1190
Test name
Test status
Simulation time	53539500 ps
CPU time	13.43 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	261400 kb
Host	smart-f3772bc2-1b84-4bc9-8191-3dddd5a47904
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720188887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test. 2720188887
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2966120679
Short name	T1173
Test name
Test status
Simulation time	61588600 ps
CPU time	14.91 seconds
Started	Jul 25 05:00:32 PM PDT 24
Finished	Jul 25 05:00:47 PM PDT 24
Peak memory	261720 kb
Host	smart-73e9dd12-49e2-40a4-8c07-5a1c6f8dd1ea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966120679 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2966120679
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4051041586
Short name	T1168
Test name
Test status
Simulation time	36613400 ps
CPU time	16.01 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:29 PM PDT 24
Peak memory	253376 kb
Host	smart-5caa73d0-a585-46e4-a1b9-e2adae41f3f3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051041586 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.4051041586
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.760367808
Short name	T1116
Test name
Test status
Simulation time	141594800 ps
CPU time	15.6 seconds
Started	Jul 25 05:00:19 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	253392 kb
Host	smart-5e24a8d8-a604-4618-acdf-00b539d1d904
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760367808 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.760367808
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.102747597
Short name	T1170
Test name
Test status
Simulation time	39321900 ps
CPU time	19.4 seconds
Started	Jul 25 05:00:18 PM PDT 24
Finished	Jul 25 05:00:38 PM PDT 24
Peak memory	278680 kb
Host	smart-a5f9cb9b-03f2-4f72-a723-bf9c71cb90eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102747597 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.102747597
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.533835875
Short name	T425
Test name
Test status
Simulation time	31871500 ps
CPU time	13.84 seconds
Started	Jul 25 05:00:24 PM PDT 24
Finished	Jul 25 05:00:38 PM PDT 24
Peak memory	261720 kb
Host	smart-78501388-00e0-48cf-bbfd-bf06cead9aed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533835875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.flash_ctrl_csr_rw.533835875
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2437336605
Short name	T1214
Test name
Test status
Simulation time	17083600 ps
CPU time	13.86 seconds
Started	Jul 25 05:00:23 PM PDT 24
Finished	Jul 25 05:00:37 PM PDT 24
Peak memory	261504 kb
Host	smart-a95e90b4-11bc-4a10-8dce-ce1b5fc9a1f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437336605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 2437336605
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1817825602
Short name	T292
Test name
Test status
Simulation time	118504400 ps
CPU time	15.83 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:00:31 PM PDT 24
Peak memory	261524 kb
Host	smart-dc5ecf6c-4079-47a7-8a9c-d3535159dfc6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817825602 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1817825602
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.885427975
Short name	T1232
Test name
Test status
Simulation time	38295800 ps
CPU time	16.01 seconds
Started	Jul 25 05:00:24 PM PDT 24
Finished	Jul 25 05:00:40 PM PDT 24
Peak memory	253428 kb
Host	smart-6cbfb62c-d7e1-4323-8459-b9940b6e7082
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885427975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.885427975
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3822286889
Short name	T1222
Test name
Test status
Simulation time	23858300 ps
CPU time	15.83 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	253296 kb
Host	smart-74aa1744-93ca-40d1-939c-fc1151a93d47
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822286889 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3822286889
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.630697166
Short name	T253
Test name
Test status
Simulation time	140432300 ps
CPU time	17.03 seconds
Started	Jul 25 05:00:13 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	264008 kb
Host	smart-77f28af8-c5de-42be-8af6-438ab37e0765
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630697166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.630697166
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3174063003
Short name	T350
Test name
Test status
Simulation time	599861500 ps
CPU time	385.34 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:06:37 PM PDT 24
Peak memory	262500 kb
Host	smart-2cd50bfa-4672-4d3c-a868-ca4f687b0396
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174063003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.3174063003
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1664082173
Short name	T1195
Test name
Test status
Simulation time	189272800 ps
CPU time	17.36 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:44 PM PDT 24
Peak memory	264148 kb
Host	smart-02584a85-606b-454f-91a9-a09fecb3307c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664082173 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1664082173
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3976731791
Short name	T282
Test name
Test status
Simulation time	294845600 ps
CPU time	17 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	264068 kb
Host	smart-0d95480e-0f55-46c5-b7c4-65fb69e1dfe9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976731791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.3976731791
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3399953565
Short name	T1128
Test name
Test status
Simulation time	24663200 ps
CPU time	13.28 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	261368 kb
Host	smart-0e8adb46-c8fb-472d-b759-958d4afdf11d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399953565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 3399953565
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.191094321
Short name	T1193
Test name
Test status
Simulation time	806847100 ps
CPU time	36.79 seconds
Started	Jul 25 05:00:29 PM PDT 24
Finished	Jul 25 05:01:06 PM PDT 24
Peak memory	261564 kb
Host	smart-a148cbbc-e75f-4798-93b9-bbba737e12e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191094321 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.191094321
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.356740015
Short name	T1115
Test name
Test status
Simulation time	24433400 ps
CPU time	13.37 seconds
Started	Jul 25 05:00:14 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	253204 kb
Host	smart-6e006803-f17d-447f-ba26-2db0b294ff13
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356740015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.356740015
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1200052138
Short name	T1124
Test name
Test status
Simulation time	58332100 ps
CPU time	15.81 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:29 PM PDT 24
Peak memory	253412 kb
Host	smart-1bba2978-d33c-4983-8eaf-45d52c80ad36
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200052138 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1200052138
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.106580959
Short name	T1257
Test name
Test status
Simulation time	38327700 ps
CPU time	17.05 seconds
Started	Jul 25 05:00:29 PM PDT 24
Finished	Jul 25 05:00:46 PM PDT 24
Peak memory	263280 kb
Host	smart-8e09045b-f7c7-43a2-8961-bb1d4d909505
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106580959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.106580959
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1020171589
Short name	T250
Test name
Test status
Simulation time	1134455000 ps
CPU time	895.15 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:15:10 PM PDT 24
Peak memory	264184 kb
Host	smart-624eed9b-670c-4874-b894-d63c78fbbd23
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020171589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr l_tl_intg_err.1020171589
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1033050891
Short name	T1177
Test name
Test status
Simulation time	93978000 ps
CPU time	16.93 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:43 PM PDT 24
Peak memory	270584 kb
Host	smart-3f9cf84c-370a-4418-bded-7e199a1ed57c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033050891 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1033050891
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4292451152
Short name	T1254
Test name
Test status
Simulation time	36619900 ps
CPU time	16.61 seconds
Started	Jul 25 05:00:24 PM PDT 24
Finished	Jul 25 05:00:40 PM PDT 24
Peak memory	264040 kb
Host	smart-8f635473-d297-46b0-a5f2-8f8d8248cfc2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292451152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.4292451152
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1432005502
Short name	T1158
Test name
Test status
Simulation time	147344100 ps
CPU time	13.38 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:25 PM PDT 24
Peak memory	261396 kb
Host	smart-1fa65143-1792-4a5b-b2f9-23c9b3e42957
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432005502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test. 1432005502
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.906543766
Short name	T1163
Test name
Test status
Simulation time	737947400 ps
CPU time	18.44 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	262984 kb
Host	smart-306d8694-701c-4cf2-b588-7597b36ceb4f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906543766 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.906543766
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2114843660
Short name	T1244
Test name
Test status
Simulation time	32417300 ps
CPU time	15.91 seconds
Started	Jul 25 05:00:10 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	253376 kb
Host	smart-12bb305d-1e6c-4514-9224-a3dac270717d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114843660 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2114843660
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.857050519
Short name	T1138
Test name
Test status
Simulation time	32321100 ps
CPU time	15.93 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:41 PM PDT 24
Peak memory	253264 kb
Host	smart-2a732006-9c45-4c96-bf19-f9bc86018c1f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857050519 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.857050519
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2186783277
Short name	T243
Test name
Test status
Simulation time	182795100 ps
CPU time	19.95 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:36 PM PDT 24
Peak memory	264056 kb
Host	smart-d04a016a-20b9-40b5-9bcf-917e7b446497
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186783277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors. 2186783277
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2643921381
Short name	T228
Test name
Test status
Simulation time	2665105300 ps
CPU time	763.04 seconds
Started	Jul 25 05:00:24 PM PDT 24
Finished	Jul 25 05:13:07 PM PDT 24
Peak memory	264116 kb
Host	smart-ca04e7d2-e7b1-4b03-8d71-70733ab21322
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643921381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr l_tl_intg_err.2643921381
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2403597758
Short name	T1174
Test name
Test status
Simulation time	56826100 ps
CPU time	15.01 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:40 PM PDT 24
Peak memory	264124 kb
Host	smart-7b82ca54-4c8c-4919-b8fc-ea826e1db553
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403597758 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2403597758
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2695191075
Short name	T242
Test name
Test status
Simulation time	39454000 ps
CPU time	16.34 seconds
Started	Jul 25 05:00:22 PM PDT 24
Finished	Jul 25 05:00:38 PM PDT 24
Peak memory	261448 kb
Host	smart-dc69f2df-2cbe-4d2f-8631-11c818421692
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695191075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_csr_rw.2695191075
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3330282966
Short name	T1149
Test name
Test status
Simulation time	17035600 ps
CPU time	13.69 seconds
Started	Jul 25 05:00:23 PM PDT 24
Finished	Jul 25 05:00:37 PM PDT 24
Peak memory	261524 kb
Host	smart-47d7f2ed-d1b6-4cd2-821e-17ac4d2e3699
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330282966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test. 3330282966
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.703263703
Short name	T1144
Test name
Test status
Simulation time	434898400 ps
CPU time	17.33 seconds
Started	Jul 25 05:00:23 PM PDT 24
Finished	Jul 25 05:00:40 PM PDT 24
Peak memory	262960 kb
Host	smart-4688d6ce-7f05-4d56-987e-c6e1cc842f3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703263703 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.703263703
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.396915908
Short name	T1203
Test name
Test status
Simulation time	12117000 ps
CPU time	15.93 seconds
Started	Jul 25 05:00:20 PM PDT 24
Finished	Jul 25 05:00:36 PM PDT 24
Peak memory	253232 kb
Host	smart-33995bbc-bc07-4b1d-b20d-8b97c50f5ff4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396915908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.396915908
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3660316077
Short name	T1172
Test name
Test status
Simulation time	14932100 ps
CPU time	13.55 seconds
Started	Jul 25 05:00:10 PM PDT 24
Finished	Jul 25 05:00:24 PM PDT 24
Peak memory	253032 kb
Host	smart-aab687e4-1135-4927-b04e-621ed9c4e612
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660316077 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3660316077
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3108597847
Short name	T1255
Test name
Test status
Simulation time	56664600 ps
CPU time	19.72 seconds
Started	Jul 25 05:00:24 PM PDT 24
Finished	Jul 25 05:00:43 PM PDT 24
Peak memory	264060 kb
Host	smart-2b80b944-d5ff-4004-b5a8-ab6d296287ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108597847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors. 3108597847
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.702702245
Short name	T1187
Test name
Test status
Simulation time	419780700 ps
CPU time	455.09 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:07:50 PM PDT 24
Peak memory	264108 kb
Host	smart-fdda0fb9-3580-47f7-8267-30cda65e4ee2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702702245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl _tl_intg_err.702702245
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2680365503
Short name	T224
Test name
Test status
Simulation time	88674000 ps
CPU time	18.17 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	272292 kb
Host	smart-250ac853-d579-4a6a-bd68-1f0417debacb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680365503 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2680365503
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2657602261
Short name	T1250
Test name
Test status
Simulation time	514203800 ps
CPU time	17.02 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:42 PM PDT 24
Peak memory	264052 kb
Host	smart-6cf6481c-22ba-44a9-b864-8ec97b87287c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657602261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.2657602261
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2654952157
Short name	T1122
Test name
Test status
Simulation time	14719500 ps
CPU time	14.18 seconds
Started	Jul 25 05:00:18 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	261528 kb
Host	smart-2c4804f8-94bd-462a-8e21-112db8f593a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654952157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 2654952157
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1433568744
Short name	T287
Test name
Test status
Simulation time	189396800 ps
CPU time	20.1 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:36 PM PDT 24
Peak memory	262916 kb
Host	smart-31d35aca-9cfb-4dc7-b051-4a248cf9c009
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433568744 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.1433568744
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1661342832
Short name	T1198
Test name
Test status
Simulation time	17289100 ps
CPU time	13.37 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	253340 kb
Host	smart-412a7ee3-9abe-47dc-849c-56fcf390fd5c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661342832 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1661342832
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4159432924
Short name	T1132
Test name
Test status
Simulation time	41638000 ps
CPU time	15.39 seconds
Started	Jul 25 05:00:19 PM PDT 24
Finished	Jul 25 05:00:35 PM PDT 24
Peak memory	253228 kb
Host	smart-51a8af3a-4b4b-45d7-ae6f-36efa54277c7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159432924 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.4159432924
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1271362421
Short name	T218
Test name
Test status
Simulation time	51039500 ps
CPU time	18.68 seconds
Started	Jul 25 05:00:13 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	263468 kb
Host	smart-2a06f001-7663-44fc-9437-b9811927ca7f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271362421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors. 1271362421
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.165422927
Short name	T113
Test name
Test status
Simulation time	893525000 ps
CPU time	17.65 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:29 PM PDT 24
Peak memory	272336 kb
Host	smart-d3573d34-b3e8-45a0-8428-7e4b297a37d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165422927 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.165422927
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2322670610
Short name	T1145
Test name
Test status
Simulation time	34017900 ps
CPU time	14.37 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:41 PM PDT 24
Peak memory	264068 kb
Host	smart-b8ab14d7-36fc-4d34-be63-c985db42d87a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322670610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.2322670610
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2050667493
Short name	T1162
Test name
Test status
Simulation time	38215400 ps
CPU time	13.8 seconds
Started	Jul 25 05:00:32 PM PDT 24
Finished	Jul 25 05:00:46 PM PDT 24
Peak memory	261528 kb
Host	smart-cc84d231-f317-4e4a-8f11-e2d2e8270025
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050667493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test. 2050667493
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4264276724
Short name	T1135
Test name
Test status
Simulation time	34770900 ps
CPU time	17.72 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	264084 kb
Host	smart-55774100-9bc0-44dc-b2a8-a4a7d4d9e2ed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264276724 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.4264276724
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3433937416
Short name	T1167
Test name
Test status
Simulation time	23741100 ps
CPU time	15.88 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	253408 kb
Host	smart-85948dd5-5e9c-4e8c-8d59-f20b6285382a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433937416 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3433937416
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3236869891
Short name	T1183
Test name
Test status
Simulation time	15100000 ps
CPU time	15.73 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	253388 kb
Host	smart-1d3894d7-77e6-4016-a43b-c8f1b1bb9937
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236869891 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.3236869891
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3449002416
Short name	T248
Test name
Test status
Simulation time	204136900 ps
CPU time	18.58 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	264056 kb
Host	smart-d076a426-66da-4ed9-8b7c-4305a650d3e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449002416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 3449002416
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1724647696
Short name	T351
Test name
Test status
Simulation time	1494171400 ps
CPU time	460 seconds
Started	Jul 25 05:00:21 PM PDT 24
Finished	Jul 25 05:08:01 PM PDT 24
Peak memory	264112 kb
Host	smart-ac830684-f304-4ca6-8448-afcb22e266a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724647696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr l_tl_intg_err.1724647696
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.401999820
Short name	T66
Test name
Test status
Simulation time	231220600 ps
CPU time	17.64 seconds
Started	Jul 25 05:00:31 PM PDT 24
Finished	Jul 25 05:00:49 PM PDT 24
Peak memory	270820 kb
Host	smart-75a80223-c51c-41cc-bbe2-410e669df6a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401999820 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.401999820
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4191336038
Short name	T67
Test name
Test status
Simulation time	272726500 ps
CPU time	17.55 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:43 PM PDT 24
Peak memory	263984 kb
Host	smart-4afa4f0c-2a2c-4a2d-841f-1eede7d89c21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191336038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.4191336038
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2720547352
Short name	T1153
Test name
Test status
Simulation time	27102400 ps
CPU time	13.41 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:29 PM PDT 24
Peak memory	261488 kb
Host	smart-497b7fc0-2ea0-42f6-a01a-91f20f8e84a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720547352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 2720547352
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1522533099
Short name	T241
Test name
Test status
Simulation time	136034500 ps
CPU time	17.39 seconds
Started	Jul 25 05:00:34 PM PDT 24
Finished	Jul 25 05:00:52 PM PDT 24
Peak memory	263004 kb
Host	smart-303ff9e9-fdba-4575-93ee-1976c1f55f1d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522533099 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.1522533099
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1636974538
Short name	T1142
Test name
Test status
Simulation time	20214900 ps
CPU time	15.79 seconds
Started	Jul 25 05:00:33 PM PDT 24
Finished	Jul 25 05:00:49 PM PDT 24
Peak memory	253264 kb
Host	smart-1c403a3a-bbbf-4f50-a9d4-ebdd462818b9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636974538 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1636974538
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3441646317
Short name	T1117
Test name
Test status
Simulation time	40616700 ps
CPU time	15.55 seconds
Started	Jul 25 05:00:34 PM PDT 24
Finished	Jul 25 05:00:50 PM PDT 24
Peak memory	253332 kb
Host	smart-56695368-49a8-4403-9b90-80ce64f181d0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441646317 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3441646317
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3188679304
Short name	T255
Test name
Test status
Simulation time	48260400 ps
CPU time	18.89 seconds
Started	Jul 25 05:00:17 PM PDT 24
Finished	Jul 25 05:00:36 PM PDT 24
Peak memory	263512 kb
Host	smart-1ba05e7e-1a97-442d-a26c-e6f1634f51f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188679304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors. 3188679304
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3691436547
Short name	T345
Test name
Test status
Simulation time	373771600 ps
CPU time	890.13 seconds
Started	Jul 25 05:00:35 PM PDT 24
Finished	Jul 25 05:15:26 PM PDT 24
Peak memory	264120 kb
Host	smart-ea3dfded-0892-4489-9195-af02fa3a50e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691436547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.3691436547
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1320334070
Short name	T1246
Test name
Test status
Simulation time	527973200 ps
CPU time	16.42 seconds
Started	Jul 25 05:00:32 PM PDT 24
Finished	Jul 25 05:00:49 PM PDT 24
Peak memory	270700 kb
Host	smart-dc186021-43fb-4b74-ae3a-3552c8102020
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320334070 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1320334070
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3221093145
Short name	T1165
Test name
Test status
Simulation time	20924500 ps
CPU time	16.28 seconds
Started	Jul 25 05:00:34 PM PDT 24
Finished	Jul 25 05:00:52 PM PDT 24
Peak memory	264064 kb
Host	smart-747e00a5-4f9e-4735-bbdd-7ac9d501c3e0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221093145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.3221093145
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3880597312
Short name	T314
Test name
Test status
Simulation time	202234900 ps
CPU time	13.44 seconds
Started	Jul 25 05:00:28 PM PDT 24
Finished	Jul 25 05:00:42 PM PDT 24
Peak memory	261512 kb
Host	smart-d8da443c-e072-4c8d-9179-e999c8a0769e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880597312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test. 3880597312
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3864522196
Short name	T1209
Test name
Test status
Simulation time	108786600 ps
CPU time	17.86 seconds
Started	Jul 25 05:00:28 PM PDT 24
Finished	Jul 25 05:00:46 PM PDT 24
Peak memory	262904 kb
Host	smart-49fb974f-ff0b-4618-bb20-ae0bd710b8fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864522196 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.3864522196
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2253171928
Short name	T1147
Test name
Test status
Simulation time	45052300 ps
CPU time	15.77 seconds
Started	Jul 25 05:00:32 PM PDT 24
Finished	Jul 25 05:00:48 PM PDT 24
Peak memory	253276 kb
Host	smart-e4246df6-8682-4ca9-a367-c957885771db
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253171928 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2253171928
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3001707602
Short name	T1249
Test name
Test status
Simulation time	47542500 ps
CPU time	15.79 seconds
Started	Jul 25 05:00:28 PM PDT 24
Finished	Jul 25 05:00:44 PM PDT 24
Peak memory	253332 kb
Host	smart-d4e04bcf-b630-43d6-ae08-18964d0014da
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001707602 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.3001707602
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2693988775
Short name	T254
Test name
Test status
Simulation time	367010300 ps
CPU time	16.4 seconds
Started	Jul 25 05:00:27 PM PDT 24
Finished	Jul 25 05:00:44 PM PDT 24
Peak memory	264076 kb
Host	smart-95af4296-8347-4cb1-89d5-5f545b69f5dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693988775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 2693988775
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2938566498
Short name	T1228
Test name
Test status
Simulation time	444815900 ps
CPU time	456.24 seconds
Started	Jul 25 05:00:29 PM PDT 24
Finished	Jul 25 05:08:05 PM PDT 24
Peak memory	264152 kb
Host	smart-31716303-0229-4f4a-98d9-b34560641126
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938566498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.2938566498
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1910933355
Short name	T1243
Test name
Test status
Simulation time	1297170900 ps
CPU time	58.48 seconds
Started	Jul 25 05:00:06 PM PDT 24
Finished	Jul 25 05:01:05 PM PDT 24
Peak memory	261688 kb
Host	smart-7dcbaaf3-2243-4744-99a3-bd834bd223c0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910933355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_aliasing.1910933355
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3652045176
Short name	T1136
Test name
Test status
Simulation time	1509939400 ps
CPU time	46.93 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	261724 kb
Host	smart-d05d6d7b-97cc-4936-8e0d-31155e3e99a5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652045176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_bit_bash.3652045176
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2290017392
Short name	T1235
Test name
Test status
Simulation time	122093800 ps
CPU time	38.65 seconds
Started	Jul 25 04:59:51 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	261668 kb
Host	smart-131aef41-e84c-4811-b0d3-f0a2a4eeaff9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290017392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.2290017392
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3698560661
Short name	T1225
Test name
Test status
Simulation time	1849482500 ps
CPU time	18.67 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	270808 kb
Host	smart-ceaf7e5c-6552-4d55-ac87-deb54eee3efd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698560661 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3698560661
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3125587835
Short name	T1133
Test name
Test status
Simulation time	84286900 ps
CPU time	16.21 seconds
Started	Jul 25 05:00:17 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	263828 kb
Host	smart-7608e996-385f-45c5-9cf3-3f27c3dedd42
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125587835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.3125587835
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2280250363
Short name	T1201
Test name
Test status
Simulation time	23940000 ps
CPU time	13.51 seconds
Started	Jul 25 05:00:06 PM PDT 24
Finished	Jul 25 05:00:20 PM PDT 24
Peak memory	261408 kb
Host	smart-fbd785d9-1787-410c-974f-7aef265a1282
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280250363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2 280250363
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4230413847
Short name	T232
Test name
Test status
Simulation time	58857600 ps
CPU time	13.54 seconds
Started	Jul 25 04:59:59 PM PDT 24
Finished	Jul 25 05:00:13 PM PDT 24
Peak memory	261580 kb
Host	smart-49473b08-d18a-42cb-b832-85cb8bffc343
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230413847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_mem_partial_access.4230413847
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.863866318
Short name	T1236
Test name
Test status
Simulation time	18813600 ps
CPU time	14.42 seconds
Started	Jul 25 05:00:14 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	261396 kb
Host	smart-125a876b-7dec-4276-8eae-8049b241fb50
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863866318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem _walk.863866318
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1880953373
Short name	T293
Test name
Test status
Simulation time	900471900 ps
CPU time	18.98 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:31 PM PDT 24
Peak memory	262948 kb
Host	smart-5835a889-e0f8-4c9e-8295-00c4799f9174
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880953373 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1880953373
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.885850911
Short name	T1113
Test name
Test status
Simulation time	35579600 ps
CPU time	13.11 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:05 PM PDT 24
Peak memory	253340 kb
Host	smart-39d97a2f-753b-4758-90e2-574cb10510cc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885850911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.885850911
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2719324005
Short name	T1241
Test name
Test status
Simulation time	32080200 ps
CPU time	13.17 seconds
Started	Jul 25 05:00:13 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	253392 kb
Host	smart-af232317-af25-4852-8a7d-d1b3718b9584
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719324005 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2719324005
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.161755672
Short name	T349
Test name
Test status
Simulation time	357914500 ps
CPU time	757.88 seconds
Started	Jul 25 04:59:53 PM PDT 24
Finished	Jul 25 05:12:31 PM PDT 24
Peak memory	264212 kb
Host	smart-68c74cd9-9f5a-43a5-8316-1fc6e37be159
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161755672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ tl_intg_err.161755672
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2930361676
Short name	T1143
Test name
Test status
Simulation time	81507800 ps
CPU time	13.7 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	261524 kb
Host	smart-ace6fbcb-11cd-463a-bcbe-c197e8f08794
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930361676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test. 2930361676
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.437003548
Short name	T1119
Test name
Test status
Simulation time	25444100 ps
CPU time	13.95 seconds
Started	Jul 25 05:00:41 PM PDT 24
Finished	Jul 25 05:00:55 PM PDT 24
Peak memory	261352 kb
Host	smart-a36e7f18-a208-49ce-868d-7f4a7758441c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437003548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.437003548
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.709504766
Short name	T1155
Test name
Test status
Simulation time	14780000 ps
CPU time	13.36 seconds
Started	Jul 25 05:00:37 PM PDT 24
Finished	Jul 25 05:00:50 PM PDT 24
Peak memory	261528 kb
Host	smart-6ba351c3-3e4c-4777-bf11-4598e5ad743a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709504766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.709504766
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.468500040
Short name	T1217
Test name
Test status
Simulation time	44009400 ps
CPU time	13.43 seconds
Started	Jul 25 05:00:40 PM PDT 24
Finished	Jul 25 05:00:54 PM PDT 24
Peak memory	261476 kb
Host	smart-fed6e759-52fd-49ca-94c6-55a2be99258d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468500040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.468500040
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.928573091
Short name	T1156
Test name
Test status
Simulation time	105238800 ps
CPU time	13.51 seconds
Started	Jul 25 05:00:33 PM PDT 24
Finished	Jul 25 05:00:47 PM PDT 24
Peak memory	261472 kb
Host	smart-03304e54-d0c5-4331-a8e6-2d8b5480e85e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928573091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.928573091
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1722926371
Short name	T247
Test name
Test status
Simulation time	89659800 ps
CPU time	13.38 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	261400 kb
Host	smart-2422dd20-d6e9-4d86-ba8d-30b4522f3bfc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722926371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test. 1722926371
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2017942376
Short name	T1234
Test name
Test status
Simulation time	14727900 ps
CPU time	13.33 seconds
Started	Jul 25 05:00:22 PM PDT 24
Finished	Jul 25 05:00:35 PM PDT 24
Peak memory	261500 kb
Host	smart-4cf4df99-5a0c-44e2-8a6e-48daf8f7cb19
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017942376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test. 2017942376
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.655956619
Short name	T1181
Test name
Test status
Simulation time	16204000 ps
CPU time	13.65 seconds
Started	Jul 25 05:00:17 PM PDT 24
Finished	Jul 25 05:00:31 PM PDT 24
Peak memory	261540 kb
Host	smart-e5d7f80c-5c34-42f8-a3cd-47d7a3c6700c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655956619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.655956619
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2195902516
Short name	T1166
Test name
Test status
Simulation time	48205200 ps
CPU time	13.32 seconds
Started	Jul 25 05:00:27 PM PDT 24
Finished	Jul 25 05:00:41 PM PDT 24
Peak memory	261424 kb
Host	smart-e6134c20-0eec-4570-bfb1-8be42392ca45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195902516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 2195902516
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.974869908
Short name	T1197
Test name
Test status
Simulation time	32000500 ps
CPU time	13.46 seconds
Started	Jul 25 05:00:18 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	261356 kb
Host	smart-3a2256c2-5302-44dc-aebe-5708c33a0e2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974869908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.974869908
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.223013306
Short name	T285
Test name
Test status
Simulation time	1591196900 ps
CPU time	65.29 seconds
Started	Jul 25 04:59:54 PM PDT 24
Finished	Jul 25 05:00:59 PM PDT 24
Peak memory	261716 kb
Host	smart-c580740c-1efe-4aea-a4c6-80d5d182f4bb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223013306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.flash_ctrl_csr_aliasing.223013306
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.278520580
Short name	T1206
Test name
Test status
Simulation time	57093300 ps
CPU time	31.04 seconds
Started	Jul 25 05:00:04 PM PDT 24
Finished	Jul 25 05:00:38 PM PDT 24
Peak memory	261564 kb
Host	smart-acfe5bd7-327a-4915-a253-48c3dc2c6646
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278520580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.flash_ctrl_csr_hw_reset.278520580
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1347823482
Short name	T1125
Test name
Test status
Simulation time	97910600 ps
CPU time	17.47 seconds
Started	Jul 25 04:59:54 PM PDT 24
Finished	Jul 25 05:00:11 PM PDT 24
Peak memory	272384 kb
Host	smart-fa5e8304-b79b-42f4-a1e8-1c8880ca34e0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347823482 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1347823482
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1238456568
Short name	T1253
Test name
Test status
Simulation time	36735700 ps
CPU time	14.43 seconds
Started	Jul 25 05:00:08 PM PDT 24
Finished	Jul 25 05:00:22 PM PDT 24
Peak memory	261612 kb
Host	smart-121a0174-2b2d-45df-bcb3-dbcfd955ba11
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238456568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_csr_rw.1238456568
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.4141759131
Short name	T1210
Test name
Test status
Simulation time	163015100 ps
CPU time	13.51 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	261472 kb
Host	smart-9cb6b2d9-981a-4a8b-b844-9b0d3baf4182
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141759131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.4 141759131
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4210352972
Short name	T1205
Test name
Test status
Simulation time	96402300 ps
CPU time	13.33 seconds
Started	Jul 25 05:00:18 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	261452 kb
Host	smart-fbe8e4b9-3ba9-4e6d-b186-3d17ca1b3fbd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210352972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.4210352972
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.641572484
Short name	T1194
Test name
Test status
Simulation time	84928200 ps
CPU time	15.64 seconds
Started	Jul 25 05:00:03 PM PDT 24
Finished	Jul 25 05:00:22 PM PDT 24
Peak memory	263784 kb
Host	smart-f19712be-f867-4e1d-8002-3ae695273b24
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641572484 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.641572484
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2906529504
Short name	T1114
Test name
Test status
Simulation time	40386100 ps
CPU time	15.51 seconds
Started	Jul 25 05:00:00 PM PDT 24
Finished	Jul 25 05:00:15 PM PDT 24
Peak memory	253272 kb
Host	smart-efcc3aaa-cf77-4e6e-8d6a-84643ba67460
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906529504 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2906529504
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3538170002
Short name	T1251
Test name
Test status
Simulation time	14100100 ps
CPU time	16.22 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:08 PM PDT 24
Peak memory	253356 kb
Host	smart-4fde3723-a16e-47f3-b895-81bff401b963
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538170002 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3538170002
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1608830715
Short name	T219
Test name
Test status
Simulation time	39832700 ps
CPU time	15.91 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	264068 kb
Host	smart-124bd701-34bb-4f76-b731-7715f9ab4195
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608830715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1 608830715
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1868480555
Short name	T1247
Test name
Test status
Simulation time	441141300 ps
CPU time	385.83 seconds
Started	Jul 25 05:00:21 PM PDT 24
Finished	Jul 25 05:06:47 PM PDT 24
Peak memory	261468 kb
Host	smart-cb77f860-5c5e-4468-916c-d25a522d61e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868480555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.1868480555
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1890593735
Short name	T1175
Test name
Test status
Simulation time	29969300 ps
CPU time	13.81 seconds
Started	Jul 25 05:00:21 PM PDT 24
Finished	Jul 25 05:00:35 PM PDT 24
Peak memory	261400 kb
Host	smart-1580f7a4-711b-427a-af12-b4a7ae9c5890
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890593735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test. 1890593735
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.490450291
Short name	T317
Test name
Test status
Simulation time	16585000 ps
CPU time	13.71 seconds
Started	Jul 25 05:00:22 PM PDT 24
Finished	Jul 25 05:00:36 PM PDT 24
Peak memory	261472 kb
Host	smart-949109d9-6d00-4ffc-8352-e2fa3b991f39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490450291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.490450291
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1665214423
Short name	T1169
Test name
Test status
Simulation time	196888500 ps
CPU time	13.45 seconds
Started	Jul 25 05:00:33 PM PDT 24
Finished	Jul 25 05:00:47 PM PDT 24
Peak memory	261464 kb
Host	smart-fe35ff2e-e351-40a5-9f68-8cc5f4579058
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665214423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 1665214423
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1058724550
Short name	T1226
Test name
Test status
Simulation time	105661700 ps
CPU time	13.41 seconds
Started	Jul 25 05:00:28 PM PDT 24
Finished	Jul 25 05:00:41 PM PDT 24
Peak memory	261464 kb
Host	smart-dc752270-1b94-4deb-8f9c-01ab0c994c02
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058724550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test. 1058724550
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3712836710
Short name	T1130
Test name
Test status
Simulation time	50470300 ps
CPU time	13.36 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:39 PM PDT 24
Peak memory	261460 kb
Host	smart-f062cb5d-e152-4133-9a41-38887441cb0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712836710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 3712836710
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1533554253
Short name	T1229
Test name
Test status
Simulation time	16606600 ps
CPU time	13.51 seconds
Started	Jul 25 05:00:29 PM PDT 24
Finished	Jul 25 05:00:42 PM PDT 24
Peak memory	261388 kb
Host	smart-2a195570-9686-4467-9d2a-a7323d920ea9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533554253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 1533554253
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3777045651
Short name	T1230
Test name
Test status
Simulation time	56184200 ps
CPU time	13.49 seconds
Started	Jul 25 05:00:24 PM PDT 24
Finished	Jul 25 05:00:38 PM PDT 24
Peak memory	261360 kb
Host	smart-fb0b89d4-895a-40f1-b406-804d4bda63a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777045651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 3777045651
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2222447887
Short name	T1137
Test name
Test status
Simulation time	17086900 ps
CPU time	14.28 seconds
Started	Jul 25 05:00:28 PM PDT 24
Finished	Jul 25 05:00:42 PM PDT 24
Peak memory	261364 kb
Host	smart-ee4be6de-a0bc-4a22-8b26-ece70378e42a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222447887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test. 2222447887
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4229877671
Short name	T1161
Test name
Test status
Simulation time	16252300 ps
CPU time	14.1 seconds
Started	Jul 25 05:00:33 PM PDT 24
Finished	Jul 25 05:00:47 PM PDT 24
Peak memory	261460 kb
Host	smart-66954004-bfa1-46b5-ae78-78cda1ce5d68
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229877671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test. 4229877671
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3171762420
Short name	T1248
Test name
Test status
Simulation time	1474612700 ps
CPU time	60.68 seconds
Started	Jul 25 05:00:23 PM PDT 24
Finished	Jul 25 05:01:24 PM PDT 24
Peak memory	261676 kb
Host	smart-414403c8-0ace-40fb-892d-fe7553cea703
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171762420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_aliasing.3171762420
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1430478088
Short name	T240
Test name
Test status
Simulation time	10543612800 ps
CPU time	67.98 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:01:23 PM PDT 24
Peak memory	261680 kb
Host	smart-014c313c-cf8d-4aac-95fa-9162b032aac3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430478088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_bit_bash.1430478088
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.306320212
Short name	T1157
Test name
Test status
Simulation time	45219600 ps
CPU time	38.48 seconds
Started	Jul 25 05:00:14 PM PDT 24
Finished	Jul 25 05:00:53 PM PDT 24
Peak memory	261452 kb
Host	smart-b3742eeb-d4fc-4c6d-8be4-3bf61f31e058
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306320212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_hw_reset.306320212
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4025436444
Short name	T291
Test name
Test status
Simulation time	191315400 ps
CPU time	16.55 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:33 PM PDT 24
Peak memory	272280 kb
Host	smart-3fc13a57-560d-43e0-a324-991a97cdb8c0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025436444 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.4025436444
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2653270277
Short name	T1131
Test name
Test status
Simulation time	57534100 ps
CPU time	17.88 seconds
Started	Jul 25 04:59:56 PM PDT 24
Finished	Jul 25 05:00:14 PM PDT 24
Peak memory	264040 kb
Host	smart-4ab0aaa4-57c6-48de-b0b8-afca915a28e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653270277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_csr_rw.2653270277
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.142335376
Short name	T233
Test name
Test status
Simulation time	57235900 ps
CPU time	13.55 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	263328 kb
Host	smart-d0e8a425-e442-4310-bac4-accd057758e8
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142335376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_mem_partial_access.142335376
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4291085899
Short name	T1127
Test name
Test status
Simulation time	28312000 ps
CPU time	13.65 seconds
Started	Jul 25 05:00:08 PM PDT 24
Finished	Jul 25 05:00:22 PM PDT 24
Peak memory	261332 kb
Host	smart-afcb940c-c9df-4c3a-80f6-09e25e9c70dd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291085899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me m_walk.4291085899
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3929922476
Short name	T1211
Test name
Test status
Simulation time	144787300 ps
CPU time	17.93 seconds
Started	Jul 25 05:00:10 PM PDT 24
Finished	Jul 25 05:00:29 PM PDT 24
Peak memory	261656 kb
Host	smart-1e57e342-672e-44eb-b59d-32966aa4e66c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929922476 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3929922476
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.385395724
Short name	T1164
Test name
Test status
Simulation time	11859600 ps
CPU time	13.62 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	253200 kb
Host	smart-ac06ec4e-26f7-4752-acef-8802632b2f22
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385395724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.385395724
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1096212925
Short name	T1182
Test name
Test status
Simulation time	18092500 ps
CPU time	15.74 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	253264 kb
Host	smart-4a4e2f5f-aa51-4ede-a311-306019c533c1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096212925 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1096212925
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2978072772
Short name	T229
Test name
Test status
Simulation time	159804600 ps
CPU time	19.7 seconds
Started	Jul 25 04:59:52 PM PDT 24
Finished	Jul 25 05:00:12 PM PDT 24
Peak memory	264148 kb
Host	smart-1f3e9b3d-3c30-4629-9008-37189a8fbf93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978072772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2 978072772
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3163024204
Short name	T1231
Test name
Test status
Simulation time	17369800 ps
CPU time	13.41 seconds
Started	Jul 25 05:00:36 PM PDT 24
Finished	Jul 25 05:00:50 PM PDT 24
Peak memory	261464 kb
Host	smart-1bba6680-fb89-4de8-83ce-26d278f95934
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163024204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 3163024204
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2390097067
Short name	T316
Test name
Test status
Simulation time	78467300 ps
CPU time	13.64 seconds
Started	Jul 25 05:00:27 PM PDT 24
Finished	Jul 25 05:00:41 PM PDT 24
Peak memory	261528 kb
Host	smart-deb6dbb4-61e4-4be3-b025-ea2f395edb14
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390097067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 2390097067
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3714294550
Short name	T1159
Test name
Test status
Simulation time	51039000 ps
CPU time	13.45 seconds
Started	Jul 25 05:00:29 PM PDT 24
Finished	Jul 25 05:00:43 PM PDT 24
Peak memory	261400 kb
Host	smart-0872ab95-7087-4c26-a291-aa246d2ca7b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714294550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 3714294550
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2581752582
Short name	T1188
Test name
Test status
Simulation time	45423200 ps
CPU time	13.6 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:25 PM PDT 24
Peak memory	261372 kb
Host	smart-2ba1f33b-eddb-4b53-b3ee-b8020534faff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581752582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test. 2581752582
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3065582343
Short name	T1152
Test name
Test status
Simulation time	60555800 ps
CPU time	13.69 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	261460 kb
Host	smart-506d1d10-46ae-4f10-b528-eeaf66f51fb9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065582343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test. 3065582343
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3327440849
Short name	T1213
Test name
Test status
Simulation time	26560700 ps
CPU time	13.36 seconds
Started	Jul 25 05:00:29 PM PDT 24
Finished	Jul 25 05:00:43 PM PDT 24
Peak memory	261464 kb
Host	smart-f2f19283-aaad-4c42-b41d-5cdea233f1dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327440849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 3327440849
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1571870054
Short name	T1126
Test name
Test status
Simulation time	26545200 ps
CPU time	13.23 seconds
Started	Jul 25 05:00:26 PM PDT 24
Finished	Jul 25 05:00:40 PM PDT 24
Peak memory	261368 kb
Host	smart-ae4ff6d0-2900-4e51-a148-708e9b0c8560
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571870054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 1571870054
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4124246255
Short name	T1202
Test name
Test status
Simulation time	184971700 ps
CPU time	13.57 seconds
Started	Jul 25 05:00:30 PM PDT 24
Finished	Jul 25 05:00:44 PM PDT 24
Peak memory	261504 kb
Host	smart-946f8ef8-2883-44a9-933b-b1ef0d06503e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124246255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 4124246255
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2846529114
Short name	T1139
Test name
Test status
Simulation time	15248800 ps
CPU time	13.69 seconds
Started	Jul 25 05:00:39 PM PDT 24
Finished	Jul 25 05:00:53 PM PDT 24
Peak memory	261284 kb
Host	smart-476f5729-17a4-4a86-98aa-7bba2ddae0b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846529114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 2846529114
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3006585816
Short name	T315
Test name
Test status
Simulation time	17958000 ps
CPU time	13.76 seconds
Started	Jul 25 05:00:31 PM PDT 24
Finished	Jul 25 05:00:45 PM PDT 24
Peak memory	261448 kb
Host	smart-6e95877c-1b35-40c8-bf01-13332c0fac7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006585816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test. 3006585816
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4205503013
Short name	T1185
Test name
Test status
Simulation time	318540400 ps
CPU time	18.9 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	271696 kb
Host	smart-27aceda5-0f7e-458b-8adb-4706ccda81af
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205503013 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4205503013
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.430015876
Short name	T1216
Test name
Test status
Simulation time	24623700 ps
CPU time	17.63 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	263984 kb
Host	smart-55d08b0a-1c79-4bbf-a083-2299c155d858
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430015876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_csr_rw.430015876
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2250137256
Short name	T1120
Test name
Test status
Simulation time	17012500 ps
CPU time	14.11 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:27 PM PDT 24
Peak memory	261388 kb
Host	smart-89478fb6-49a0-484a-8c9d-54f6231936da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250137256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2 250137256
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4036673755
Short name	T1219
Test name
Test status
Simulation time	409526200 ps
CPU time	35.16 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:47 PM PDT 24
Peak memory	261748 kb
Host	smart-120ec304-f14a-43c3-a6bb-8d9baa1b2a84
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036673755 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.4036673755
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4088744150
Short name	T1192
Test name
Test status
Simulation time	151894500 ps
CPU time	15.83 seconds
Started	Jul 25 05:00:19 PM PDT 24
Finished	Jul 25 05:00:35 PM PDT 24
Peak memory	253312 kb
Host	smart-32913383-e359-4027-8b07-e96627c98088
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088744150 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.4088744150
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3621209281
Short name	T1179
Test name
Test status
Simulation time	74562900 ps
CPU time	15.78 seconds
Started	Jul 25 05:00:08 PM PDT 24
Finished	Jul 25 05:00:24 PM PDT 24
Peak memory	253376 kb
Host	smart-49d11f3c-4436-4bbc-bb2d-059810215850
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621209281 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3621209281
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2223499827
Short name	T344
Test name
Test status
Simulation time	108724200 ps
CPU time	19.26 seconds
Started	Jul 25 05:00:05 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	264088 kb
Host	smart-858515f7-b678-4530-ac44-d5cd7362cdce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223499827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2 223499827
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3066026140
Short name	T1239
Test name
Test status
Simulation time	177336800 ps
CPU time	15.1 seconds
Started	Jul 25 05:00:06 PM PDT 24
Finished	Jul 25 05:00:21 PM PDT 24
Peak memory	272400 kb
Host	smart-aeb5a6fa-5a37-49fd-b108-0e631e42982f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066026140 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3066026140
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4217753864
Short name	T1218
Test name
Test status
Simulation time	67255000 ps
CPU time	17.22 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	261452 kb
Host	smart-e0b4219e-2e7b-4614-becf-3120a1fda0d6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217753864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.4217753864
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4140382331
Short name	T1148
Test name
Test status
Simulation time	15261200 ps
CPU time	14.05 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:00:23 PM PDT 24
Peak memory	261372 kb
Host	smart-2f2e6a86-991e-4254-bd82-4c4e55fc8939
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140382331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.4 140382331
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2652623321
Short name	T1180
Test name
Test status
Simulation time	386315700 ps
CPU time	19.7 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:36 PM PDT 24
Peak memory	261592 kb
Host	smart-8809e764-07a2-4f37-b3eb-35ff54ac540c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652623321 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2652623321
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2988048087
Short name	T1154
Test name
Test status
Simulation time	43890900 ps
CPU time	15.74 seconds
Started	Jul 25 05:00:02 PM PDT 24
Finished	Jul 25 05:00:22 PM PDT 24
Peak memory	253192 kb
Host	smart-203ed682-de03-49c2-999b-c6c3ba13cc4c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988048087 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2988048087
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3086822660
Short name	T1150
Test name
Test status
Simulation time	25288900 ps
CPU time	15.86 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:27 PM PDT 24
Peak memory	253396 kb
Host	smart-ca1cf90e-d199-490f-9691-f805309dbe29
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086822660 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.3086822660
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2307842501
Short name	T252
Test name
Test status
Simulation time	248632500 ps
CPU time	20.15 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	264036 kb
Host	smart-6f192c9f-d9be-4683-9daa-25ff9e231004
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307842501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2 307842501
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.321565162
Short name	T353
Test name
Test status
Simulation time	427632600 ps
CPU time	455.56 seconds
Started	Jul 25 05:00:20 PM PDT 24
Finished	Jul 25 05:07:56 PM PDT 24
Peak memory	264108 kb
Host	smart-4dfc11b0-1098-4013-b499-47dc4256000c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321565162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ tl_intg_err.321565162
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1238135696
Short name	T230
Test name
Test status
Simulation time	113813500 ps
CPU time	17.33 seconds
Started	Jul 25 05:00:15 PM PDT 24
Finished	Jul 25 05:00:33 PM PDT 24
Peak memory	264056 kb
Host	smart-c935e147-bd93-4a7f-af0e-d571d84ce999
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238135696 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1238135696
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2291096166
Short name	T311
Test name
Test status
Simulation time	107087600 ps
CPU time	18.22 seconds
Started	Jul 25 04:59:56 PM PDT 24
Finished	Jul 25 05:00:14 PM PDT 24
Peak memory	264024 kb
Host	smart-49ad7a26-7ccc-4de5-a2b1-46b6689e4821
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291096166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_csr_rw.2291096166
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4138662995
Short name	T1184
Test name
Test status
Simulation time	17770000 ps
CPU time	13.6 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:21 PM PDT 24
Peak memory	261400 kb
Host	smart-e6305b9d-a886-4a69-ba8d-4bda92aef3b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138662995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.4 138662995
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1128966429
Short name	T1129
Test name
Test status
Simulation time	70845100 ps
CPU time	14.94 seconds
Started	Jul 25 05:00:16 PM PDT 24
Finished	Jul 25 05:00:31 PM PDT 24
Peak memory	261744 kb
Host	smart-41079807-5a3a-49be-9f2f-3467c072948f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128966429 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1128966429
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2669574593
Short name	T1221
Test name
Test status
Simulation time	21344300 ps
CPU time	15.92 seconds
Started	Jul 25 05:00:08 PM PDT 24
Finished	Jul 25 05:00:24 PM PDT 24
Peak memory	253340 kb
Host	smart-cda0a688-9f9d-44a2-8932-02f790fc2547
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669574593 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2669574593
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1779684004
Short name	T1252
Test name
Test status
Simulation time	15010300 ps
CPU time	15.48 seconds
Started	Jul 25 05:00:18 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	253388 kb
Host	smart-5c7c667b-794d-4317-8126-c38ce49c96e8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779684004 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1779684004
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1094649815
Short name	T1191
Test name
Test status
Simulation time	42015800 ps
CPU time	16.84 seconds
Started	Jul 25 05:00:10 PM PDT 24
Finished	Jul 25 05:00:27 PM PDT 24
Peak memory	264048 kb
Host	smart-daca9a28-2b38-4f41-b042-cfdb84d705b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094649815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1 094649815
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.380655155
Short name	T114
Test name
Test status
Simulation time	698794300 ps
CPU time	460.4 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:07:50 PM PDT 24
Peak memory	264084 kb
Host	smart-3587cf52-df1b-4ed6-b749-a2084b18b3d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380655155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ tl_intg_err.380655155
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1611524247
Short name	T290
Test name
Test status
Simulation time	105633200 ps
CPU time	17.43 seconds
Started	Jul 25 05:00:25 PM PDT 24
Finished	Jul 25 05:00:42 PM PDT 24
Peak memory	271792 kb
Host	smart-b130a738-2f69-41f0-8c69-e9f7c03c0c91
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611524247 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1611524247
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3783116887
Short name	T288
Test name
Test status
Simulation time	65714000 ps
CPU time	17.2 seconds
Started	Jul 25 05:00:01 PM PDT 24
Finished	Jul 25 05:00:18 PM PDT 24
Peak memory	263980 kb
Host	smart-0d89e04b-b0c5-48ce-aa37-110ad86d8aec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783116887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.3783116887
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3943752319
Short name	T313
Test name
Test status
Simulation time	27298200 ps
CPU time	13.5 seconds
Started	Jul 25 05:00:11 PM PDT 24
Finished	Jul 25 05:00:25 PM PDT 24
Peak memory	261528 kb
Host	smart-d08786cd-9937-4dc5-ad62-1edd2e3b2540
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943752319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3 943752319
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3548000601
Short name	T1256
Test name
Test status
Simulation time	58202900 ps
CPU time	19.01 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:26 PM PDT 24
Peak memory	261684 kb
Host	smart-b2c753aa-1c2f-4ef5-b61d-14a3da191d94
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548000601 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3548000601
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.4110279033
Short name	T1237
Test name
Test status
Simulation time	13749500 ps
CPU time	13.27 seconds
Started	Jul 25 05:00:07 PM PDT 24
Finished	Jul 25 05:00:21 PM PDT 24
Peak memory	253384 kb
Host	smart-450327d9-cead-48c6-a246-181e4b93db57
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110279033 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.4110279033
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.659136452
Short name	T1134
Test name
Test status
Simulation time	37318400 ps
CPU time	13.17 seconds
Started	Jul 25 05:00:17 PM PDT 24
Finished	Jul 25 05:00:30 PM PDT 24
Peak memory	253404 kb
Host	smart-070a452a-2554-4a05-be24-437edc333983
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659136452 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.659136452
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2295781920
Short name	T1215
Test name
Test status
Simulation time	164927200 ps
CPU time	16.53 seconds
Started	Jul 25 05:00:08 PM PDT 24
Finished	Jul 25 05:00:25 PM PDT 24
Peak memory	264088 kb
Host	smart-752fed10-8b27-47af-8bf0-68938a2676ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295781920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.2 295781920
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.875373279
Short name	T347
Test name
Test status
Simulation time	1811199300 ps
CPU time	457.41 seconds
Started	Jul 25 05:00:09 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	264100 kb
Host	smart-d4b4c1b6-71b0-4b23-a1bf-ba8d8d33c21b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875373279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ tl_intg_err.875373279
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.426576299
Short name	T1200
Test name
Test status
Simulation time	419740200 ps
CPU time	19.27 seconds
Started	Jul 25 05:00:12 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	272360 kb
Host	smart-e7419631-be71-42e4-9be9-2d610b3bb978
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426576299 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.426576299
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2596728454
Short name	T289
Test name
Test status
Simulation time	267056100 ps
CPU time	17.68 seconds
Started	Jul 25 05:00:13 PM PDT 24
Finished	Jul 25 05:00:31 PM PDT 24
Peak memory	261988 kb
Host	smart-42ea7f0f-3ebc-4498-aaba-95e91c058c9d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596728454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_csr_rw.2596728454
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3787149564
Short name	T1233
Test name
Test status
Simulation time	51889200 ps
CPU time	13.48 seconds
Started	Jul 25 04:59:57 PM PDT 24
Finished	Jul 25 05:00:11 PM PDT 24
Peak memory	261456 kb
Host	smart-c1283933-251a-45f0-8348-087a903d2f36
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787149564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3 787149564
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3610777515
Short name	T1220
Test name
Test status
Simulation time	119532300 ps
CPU time	18.89 seconds
Started	Jul 25 05:00:13 PM PDT 24
Finished	Jul 25 05:00:32 PM PDT 24
Peak memory	261508 kb
Host	smart-39767ad4-5b5e-481f-8885-b2811e24b7b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610777515 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3610777515
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3168937112
Short name	T1112
Test name
Test status
Simulation time	14485100 ps
CPU time	15.68 seconds
Started	Jul 25 05:00:19 PM PDT 24
Finished	Jul 25 05:00:34 PM PDT 24
Peak memory	253240 kb
Host	smart-49598fde-fb8a-4b7d-afe4-26009cf89eb7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168937112 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.3168937112
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1268490594
Short name	T1151
Test name
Test status
Simulation time	11212600 ps
CPU time	13.46 seconds
Started	Jul 25 05:00:14 PM PDT 24
Finished	Jul 25 05:00:28 PM PDT 24
Peak memory	253308 kb
Host	smart-cc0fd8ee-2526-480b-aa26-731d3ce712cd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268490594 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1268490594
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.3978130221
Short name	T300
Test name
Test status
Simulation time	109529000 ps
CPU time	13.73 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:06:03 PM PDT 24
Peak memory	257776 kb
Host	smart-66b8668d-c0db-4a2c-848f-61a26d2da30e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978130221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3 978130221
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.2117170090
Short name	T1094
Test name
Test status
Simulation time	39082800 ps
CPU time	14.36 seconds
Started	Jul 25 05:05:48 PM PDT 24
Finished	Jul 25 05:06:03 PM PDT 24
Peak memory	264444 kb
Host	smart-15dda812-5e26-4212-9b21-02bb733e0500
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117170090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.2117170090
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.3893249853
Short name	T124
Test name
Test status
Simulation time	45022000 ps
CPU time	13.18 seconds
Started	Jul 25 05:05:51 PM PDT 24
Finished	Jul 25 05:06:04 PM PDT 24
Peak memory	284044 kb
Host	smart-dd96562c-77cb-4880-8be1-16404841ef6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893249853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3893249853
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.964900091
Short name	T182
Test name
Test status
Simulation time	46158100 ps
CPU time	22.06 seconds
Started	Jul 25 05:06:07 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	265356 kb
Host	smart-053c5e8b-84c2-4f32-aa57-89ced39db5bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964900091 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.964900091
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.103012308
Short name	T1049
Test name
Test status
Simulation time	4172855800 ps
CPU time	397.62 seconds
Started	Jul 25 05:05:40 PM PDT 24
Finished	Jul 25 05:12:18 PM PDT 24
Peak memory	263244 kb
Host	smart-a451e921-1112-4bfa-8519-0142862440a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=103012308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.103012308
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.344689022
Short name	T776
Test name
Test status
Simulation time	7911004700 ps
CPU time	2214.17 seconds
Started	Jul 25 05:05:40 PM PDT 24
Finished	Jul 25 05:42:35 PM PDT 24
Peak memory	262688 kb
Host	smart-fe874657-d96c-4804-83c0-cfb15a9a7104
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=344689022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.344689022
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.2619502037
Short name	T877
Test name
Test status
Simulation time	622756700 ps
CPU time	37.17 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:27 PM PDT 24
Peak memory	262196 kb
Host	smart-d1d207de-1d6c-4a6e-a8ee-457d45604a1b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619502037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.2619502037
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.4230640907
Short name	T626
Test name
Test status
Simulation time	191526300 ps
CPU time	30.13 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:20 PM PDT 24
Peak memory	275192 kb
Host	smart-ca8e6171-05b1-4be4-ac53-fd95f7c81ff2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230640907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.4230640907
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.417321752
Short name	T876
Test name
Test status
Simulation time	473250804000 ps
CPU time	1942.79 seconds
Started	Jul 25 05:05:40 PM PDT 24
Finished	Jul 25 05:38:03 PM PDT 24
Peak memory	263844 kb
Host	smart-cb0b661a-2126-48d9-97b4-08fc9e50bcc7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417321752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.flash_ctrl_host_ctrl_arb.417321752
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.1558259372
Short name	T1073
Test name
Test status
Simulation time	266905600 ps
CPU time	125.07 seconds
Started	Jul 25 05:05:42 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	262452 kb
Host	smart-ea27a600-262d-4946-b6da-7305443bb108
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1558259372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1558259372
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.1021263946
Short name	T807
Test name
Test status
Simulation time	213259020100 ps
CPU time	2032.8 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:39:34 PM PDT 24
Peak memory	259800 kb
Host	smart-af2f8887-7430-42f6-accb-713c991953db
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021263946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_rma.1021263946
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3956700720
Short name	T186
Test name
Test status
Simulation time	540431067100 ps
CPU time	1309.18 seconds
Started	Jul 25 05:05:45 PM PDT 24
Finished	Jul 25 05:27:34 PM PDT 24
Peak memory	264772 kb
Host	smart-318de97b-fe7a-4329-bb8c-222fd3686b55
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956700720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_hw_rma_reset.3956700720
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2498235222
Short name	T856
Test name
Test status
Simulation time	23168475900 ps
CPU time	162.89 seconds
Started	Jul 25 05:05:44 PM PDT 24
Finished	Jul 25 05:08:27 PM PDT 24
Peak memory	261936 kb
Host	smart-60e682f2-2453-4569-b5dc-25263fadbcf9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498235222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.2498235222
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.3384588024
Short name	T259
Test name
Test status
Simulation time	1542462700 ps
CPU time	142.2 seconds
Started	Jul 25 05:05:52 PM PDT 24
Finished	Jul 25 05:08:14 PM PDT 24
Peak memory	284780 kb
Host	smart-bec7f9f4-5380-4467-af51-06e4f4e2ed18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384588024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_intr_rd.3384588024
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.606082204
Short name	T841
Test name
Test status
Simulation time	12511577900 ps
CPU time	290.54 seconds
Started	Jul 25 05:06:02 PM PDT 24
Finished	Jul 25 05:10:53 PM PDT 24
Peak memory	290616 kb
Host	smart-62116fd1-41ff-4e74-b71c-c763187af396
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606082204 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.606082204
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.813046965
Short name	T664
Test name
Test status
Simulation time	125976602900 ps
CPU time	265.75 seconds
Started	Jul 25 05:06:02 PM PDT 24
Finished	Jul 25 05:10:28 PM PDT 24
Peak memory	259956 kb
Host	smart-7bb7c364-f827-475e-affd-aa9c89300ce5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813 046965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.813046965
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.2367737807
Short name	T496
Test name
Test status
Simulation time	15989458400 ps
CPU time	72.63 seconds
Started	Jul 25 05:05:39 PM PDT 24
Finished	Jul 25 05:06:52 PM PDT 24
Peak memory	262588 kb
Host	smart-f3ba5086-8019-40f8-8a12-a47290c2f3da
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367737807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2367737807
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.1065773150
Short name	T977
Test name
Test status
Simulation time	19020585600 ps
CPU time	573.46 seconds
Started	Jul 25 05:05:40 PM PDT 24
Finished	Jul 25 05:15:14 PM PDT 24
Peak memory	274476 kb
Host	smart-08219da8-e94e-4284-874b-dccf2752310e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065773150 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.1065773150
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.2635936748
Short name	T166
Test name
Test status
Simulation time	150123900 ps
CPU time	132.04 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:07:54 PM PDT 24
Peak memory	265076 kb
Host	smart-bb3831d9-87ca-4b19-8bb6-33592706c35a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635936748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot p_reset.2635936748
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.1141075733
Short name	T509
Test name
Test status
Simulation time	767148300 ps
CPU time	125.8 seconds
Started	Jul 25 05:05:48 PM PDT 24
Finished	Jul 25 05:07:54 PM PDT 24
Peak memory	289680 kb
Host	smart-c68c88eb-6374-43dc-a059-976a3d6b0fa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141075733 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.1141075733
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2731936565
Short name	T194
Test name
Test status
Simulation time	17045700 ps
CPU time	14.12 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:06:10 PM PDT 24
Peak memory	261148 kb
Host	smart-5787add9-e5ac-48f0-83b6-921a2396cb3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2731936565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2731936565
Directory	/workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.566016204
Short name	T693
Test name
Test status
Simulation time	746129900 ps
CPU time	497.18 seconds
Started	Jul 25 05:05:40 PM PDT 24
Finished	Jul 25 05:13:58 PM PDT 24
Peak memory	262896 kb
Host	smart-39108784-7020-402c-a4e1-6ea14d0a4fcc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=566016204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.566016204
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1705255964
Short name	T88
Test name
Test status
Simulation time	777826300 ps
CPU time	15.03 seconds
Started	Jul 25 05:05:57 PM PDT 24
Finished	Jul 25 05:06:13 PM PDT 24
Peak memory	264828 kb
Host	smart-8bb0c89d-5ca3-4a7f-9e2e-df9969d1975c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705255964 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1705255964
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.526195381
Short name	T193
Test name
Test status
Simulation time	15197600 ps
CPU time	14.16 seconds
Started	Jul 25 05:05:57 PM PDT 24
Finished	Jul 25 05:06:12 PM PDT 24
Peak memory	262536 kb
Host	smart-64d5553d-45fa-49ca-9a0e-6e1deeaf60a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526195381 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.526195381
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.1078626006
Short name	T911
Test name
Test status
Simulation time	31752100 ps
CPU time	13.44 seconds
Started	Jul 25 05:05:47 PM PDT 24
Finished	Jul 25 05:06:01 PM PDT 24
Peak memory	264856 kb
Host	smart-9cda9617-788c-4b68-8885-0674579c6737
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078626006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.1078626006
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.2565386961
Short name	T155
Test name
Test status
Simulation time	99024100 ps
CPU time	440.74 seconds
Started	Jul 25 05:05:42 PM PDT 24
Finished	Jul 25 05:13:03 PM PDT 24
Peak memory	281368 kb
Host	smart-d7805dcc-563d-4ffd-935a-4032c51d33bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565386961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2565386961
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.362746970
Short name	T992
Test name
Test status
Simulation time	453288200 ps
CPU time	32.45 seconds
Started	Jul 25 05:05:51 PM PDT 24
Finished	Jul 25 05:06:23 PM PDT 24
Peak memory	268096 kb
Host	smart-b34c9fc6-a854-4d17-aeb3-eff10bf175e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362746970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_rd_intg.362746970
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.2495213738
Short name	T1091
Test name
Test status
Simulation time	48011800 ps
CPU time	44.12 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:06:33 PM PDT 24
Peak memory	275388 kb
Host	smart-4b081dad-aa0f-4ff4-9e83-8bbb8d6a6c7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495213738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_rd_ooo.2495213738
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.1341388520
Short name	T954
Test name
Test status
Simulation time	575523700 ps
CPU time	35.07 seconds
Started	Jul 25 05:05:53 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	275328 kb
Host	smart-1cd21a17-b4a9-4232-8e9b-6620fbf2ce29
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341388520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.1341388520
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.2702664194
Short name	T982
Test name
Test status
Simulation time	41015200 ps
CPU time	14.15 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:05:56 PM PDT 24
Peak memory	264780 kb
Host	smart-3bf9e5a6-921a-49d5-af1c-19b56950d6ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2702664194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep .2702664194
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.2995463846
Short name	T522
Test name
Test status
Simulation time	19286900 ps
CPU time	21.02 seconds
Started	Jul 25 05:05:44 PM PDT 24
Finished	Jul 25 05:06:05 PM PDT 24
Peak memory	264996 kb
Host	smart-69c377f0-41f3-44ae-9953-5385a02b093a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995463846 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.2995463846
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1708735014
Short name	T378
Test name
Test status
Simulation time	25028400 ps
CPU time	22.59 seconds
Started	Jul 25 05:05:38 PM PDT 24
Finished	Jul 25 05:06:01 PM PDT 24
Peak memory	264652 kb
Host	smart-43fad998-7116-409f-bb78-cf8766f4b81d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708735014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.1708735014
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.3080656426
Short name	T169
Test name
Test status
Simulation time	41318335600 ps
CPU time	942.83 seconds
Started	Jul 25 05:05:48 PM PDT 24
Finished	Jul 25 05:21:32 PM PDT 24
Peak memory	261252 kb
Host	smart-c81617aa-8c78-4b9c-95dc-cc71306a33f7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080656426 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.3080656426
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.3147716126
Short name	T957
Test name
Test status
Simulation time	978992800 ps
CPU time	102.63 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:07:24 PM PDT 24
Peak memory	280644 kb
Host	smart-a2cdc0a6-2937-48ad-8a11-3325a601c467
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147716126 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.3147716126
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.374426666
Short name	T239
Test name
Test status
Simulation time	571418000 ps
CPU time	122.49 seconds
Started	Jul 25 05:05:43 PM PDT 24
Finished	Jul 25 05:07:46 PM PDT 24
Peak memory	281464 kb
Host	smart-953e4314-6442-4f8c-9bcc-d020f92f13a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 374426666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.374426666
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.146553245
Short name	T377
Test name
Test status
Simulation time	3931037500 ps
CPU time	130.93 seconds
Started	Jul 25 05:05:43 PM PDT 24
Finished	Jul 25 05:07:54 PM PDT 24
Peak memory	289772 kb
Host	smart-ef46b2e8-3511-4eac-8af7-39020e4fecc5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146553245 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.146553245
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.2825293935
Short name	T618
Test name
Test status
Simulation time	12686499000 ps
CPU time	519.8 seconds
Started	Jul 25 05:05:42 PM PDT 24
Finished	Jul 25 05:14:22 PM PDT 24
Peak memory	309256 kb
Host	smart-23b3717d-d54a-4e64-b9d9-9f2124d63ccb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825293935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.2825293935
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict.755324644
Short name	T836
Test name
Test status
Simulation time	49604700 ps
CPU time	28.38 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:06:17 PM PDT 24
Peak memory	275372 kb
Host	smart-c39820a5-a209-4f49-8e4c-d850caf178d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755324644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_rw_evict.755324644
Directory	/workspace/0.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4132531144
Short name	T808
Test name
Test status
Simulation time	42930000 ps
CPU time	28.91 seconds
Started	Jul 25 05:06:02 PM PDT 24
Finished	Jul 25 05:06:31 PM PDT 24
Peak memory	275244 kb
Host	smart-57c9b6ae-19cc-42f9-9ce5-5f385a18d81a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132531144 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.4132531144
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_serr.3705104387
Short name	T1090
Test name
Test status
Simulation time	54117342300 ps
CPU time	624.75 seconds
Started	Jul 25 05:05:43 PM PDT 24
Finished	Jul 25 05:16:08 PM PDT 24
Peak memory	312316 kb
Host	smart-1afdb942-a5b8-4b02-a3d9-996e9586c53f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705104387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s err.3705104387
Directory	/workspace/0.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.598139349
Short name	T13
Test name
Test status
Simulation time	1333845800 ps
CPU time	4752.09 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 06:25:01 PM PDT 24
Peak memory	289124 kb
Host	smart-4c5299dc-3e03-47cf-8393-1f9cfce41733
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598139349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.598139349
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.3980029159
Short name	T407
Test name
Test status
Simulation time	6043928500 ps
CPU time	69 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:07:05 PM PDT 24
Peak memory	263424 kb
Host	smart-ddf86f33-1d4b-4951-a8e2-c739049b20b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980029159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3980029159
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.1987588914
Short name	T35
Test name
Test status
Simulation time	972073000 ps
CPU time	102.18 seconds
Started	Jul 25 05:05:44 PM PDT 24
Finished	Jul 25 05:07:26 PM PDT 24
Peak memory	265076 kb
Host	smart-51624767-2960-4794-a8c9-82bee56a1524
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987588914 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_serr_address.1987588914
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.2781281609
Short name	T621
Test name
Test status
Simulation time	1188149300 ps
CPU time	54.35 seconds
Started	Jul 25 05:05:41 PM PDT 24
Finished	Jul 25 05:06:36 PM PDT 24
Peak memory	276404 kb
Host	smart-d2bc295f-b71c-4425-8e16-05f400ae60b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781281609 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.2781281609
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.2158188051
Short name	T611
Test name
Test status
Simulation time	46519800 ps
CPU time	121.26 seconds
Started	Jul 25 05:05:43 PM PDT 24
Finished	Jul 25 05:07:44 PM PDT 24
Peak memory	276228 kb
Host	smart-2b639c78-add8-4cfb-b867-eab68ca38e05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158188051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2158188051
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.112436121
Short name	T648
Test name
Test status
Simulation time	45701900 ps
CPU time	26.01 seconds
Started	Jul 25 05:05:43 PM PDT 24
Finished	Jul 25 05:06:09 PM PDT 24
Peak memory	259584 kb
Host	smart-de510764-f572-4a8f-b335-91e9915908e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112436121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.112436121
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.1080342092
Short name	T54
Test name
Test status
Simulation time	206233200 ps
CPU time	83.02 seconds
Started	Jul 25 05:05:48 PM PDT 24
Finished	Jul 25 05:07:11 PM PDT 24
Peak memory	261256 kb
Host	smart-a395163d-11ed-4d76-ae9e-db8da9d8e8eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080342092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres s_all.1080342092
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.4030595949
Short name	T1056
Test name
Test status
Simulation time	46001100 ps
CPU time	24.15 seconds
Started	Jul 25 05:05:43 PM PDT 24
Finished	Jul 25 05:06:08 PM PDT 24
Peak memory	262080 kb
Host	smart-d2eee8d6-7815-4a8d-b64b-814eac45a2c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030595949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4030595949
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.2050701256
Short name	T383
Test name
Test status
Simulation time	8560846700 ps
CPU time	195.07 seconds
Started	Jul 25 05:05:42 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	265008 kb
Host	smart-0be2fb4c-93ba-4b7a-a3a2-96ca6e9b1594
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050701256 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_wo.2050701256
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.2012184987
Short name	T1001
Test name
Test status
Simulation time	75083800 ps
CPU time	15.33 seconds
Started	Jul 25 05:05:44 PM PDT 24
Finished	Jul 25 05:06:00 PM PDT 24
Peak memory	264788 kb
Host	smart-b91b7459-796f-45f9-b4a6-f5165ed8219f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2012184987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe ep.2012184987
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.1363709257
Short name	T23
Test name
Test status
Simulation time	24719800 ps
CPU time	13.87 seconds
Started	Jul 25 05:05:57 PM PDT 24
Finished	Jul 25 05:06:11 PM PDT 24
Peak memory	261340 kb
Host	smart-524fbce7-d0fa-4e2c-abe1-a0ae3051b748
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363709257 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1363709257
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.2194079423
Short name	T1076
Test name
Test status
Simulation time	122531400 ps
CPU time	13.88 seconds
Started	Jul 25 05:06:05 PM PDT 24
Finished	Jul 25 05:06:19 PM PDT 24
Peak memory	264932 kb
Host	smart-98c33b8a-b902-4742-a863-6430cc0363fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194079423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2 194079423
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.3851658067
Short name	T354
Test name
Test status
Simulation time	63657300 ps
CPU time	14.12 seconds
Started	Jul 25 05:06:02 PM PDT 24
Finished	Jul 25 05:06:16 PM PDT 24
Peak memory	260996 kb
Host	smart-5cff5b3e-8100-43f2-aa52-88a093edce4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851658067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.3851658067
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.459447772
Short name	T959
Test name
Test status
Simulation time	39892300 ps
CPU time	13.31 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:06:10 PM PDT 24
Peak memory	284108 kb
Host	smart-d3817083-3faf-400f-bf7b-2a4ab36ccbf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459447772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.459447772
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.2956060470
Short name	T761
Test name
Test status
Simulation time	14428766600 ps
CPU time	2175.66 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:42:22 PM PDT 24
Peak memory	265012 kb
Host	smart-3fc3c8e4-13b5-4a46-aff5-92de0232d6cd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2956060470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2956060470
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.3664272795
Short name	T96
Test name
Test status
Simulation time	1977123500 ps
CPU time	2519.73 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:47:49 PM PDT 24
Peak memory	264356 kb
Host	smart-713d7895-b689-4f13-87f4-474c7613e031
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664272795 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3664272795
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.82152664
Short name	T748
Test name
Test status
Simulation time	641180100 ps
CPU time	874.84 seconds
Started	Jul 25 05:06:02 PM PDT 24
Finished	Jul 25 05:20:37 PM PDT 24
Peak memory	272976 kb
Host	smart-98dacdfe-c7e9-40a6-955f-9d4d474fb51c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82152664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.82152664
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.1998784856
Short name	T1072
Test name
Test status
Simulation time	297524900 ps
CPU time	25.18 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:06:14 PM PDT 24
Peak memory	262356 kb
Host	smart-d433ab4a-1cf5-4b99-bdf9-7931d4fa83a5
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998784856 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1998784856
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.1462747020
Short name	T899
Test name
Test status
Simulation time	298290700 ps
CPU time	39.83 seconds
Started	Jul 25 05:05:59 PM PDT 24
Finished	Jul 25 05:06:39 PM PDT 24
Peak memory	265068 kb
Host	smart-ff939ed7-da30-41cc-8532-dcbfe57301a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462747020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_fs_sup.1462747020
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.2977768150
Short name	T952
Test name
Test status
Simulation time	97824936700 ps
CPU time	3608.43 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 06:06:05 PM PDT 24
Peak memory	262684 kb
Host	smart-9abf3b24-3627-4e04-9049-d6b85795974e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977768150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.2977768150
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.2488879339
Short name	T615
Test name
Test status
Simulation time	26988900 ps
CPU time	30.27 seconds
Started	Jul 25 05:06:11 PM PDT 24
Finished	Jul 25 05:06:41 PM PDT 24
Peak memory	275292 kb
Host	smart-b4046d23-6a0d-4cb4-b6a8-3b79c5954b35
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488879339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.2488879339
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4158747564
Short name	T117
Test name
Test status
Simulation time	288972932900 ps
CPU time	2920.58 seconds
Started	Jul 25 05:05:52 PM PDT 24
Finished	Jul 25 05:54:33 PM PDT 24
Peak memory	264008 kb
Host	smart-182eb17a-f8a8-4c20-a44c-af0e93dced37
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158747564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_host_ctrl_arb.4158747564
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.534057346
Short name	T264
Test name
Test status
Simulation time	186625700 ps
CPU time	92.21 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:07:23 PM PDT 24
Peak memory	262396 kb
Host	smart-b8fb0e31-7a5e-4634-a0bd-9bc82869d169
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=534057346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.534057346
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2648343761
Short name	T1088
Test name
Test status
Simulation time	10019663400 ps
CPU time	90.89 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:07:37 PM PDT 24
Peak memory	330624 kb
Host	smart-b7855be5-2942-4c7e-881c-6acd49429be6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648343761 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2648343761
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2412041719
Short name	T657
Test name
Test status
Simulation time	25980200 ps
CPU time	13.56 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:06:20 PM PDT 24
Peak memory	264736 kb
Host	smart-5294ecc6-89f7-42ef-a8e8-ed9520b310f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412041719 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2412041719
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.93675686
Short name	T642
Test name
Test status
Simulation time	338321061000 ps
CPU time	1866.29 seconds
Started	Jul 25 05:05:54 PM PDT 24
Finished	Jul 25 05:37:00 PM PDT 24
Peak memory	265000 kb
Host	smart-7dd74193-b833-4273-a449-55233da68a09
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93675686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_hw_rma.93675686
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3033859572
Short name	T1030
Test name
Test status
Simulation time	80144282500 ps
CPU time	907.61 seconds
Started	Jul 25 05:05:54 PM PDT 24
Finished	Jul 25 05:21:02 PM PDT 24
Peak memory	264204 kb
Host	smart-5e141b89-5060-4942-8d04-e932b92b501b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033859572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.3033859572
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3755359874
Short name	T591
Test name
Test status
Simulation time	10743560600 ps
CPU time	227.55 seconds
Started	Jul 25 05:05:53 PM PDT 24
Finished	Jul 25 05:09:41 PM PDT 24
Peak memory	262992 kb
Host	smart-521edc6d-c278-482b-9066-a5c2c291eb8f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755359874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h w_sec_otp.3755359874
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.3700422310
Short name	T1032
Test name
Test status
Simulation time	7005179500 ps
CPU time	129.32 seconds
Started	Jul 25 05:05:57 PM PDT 24
Finished	Jul 25 05:08:06 PM PDT 24
Peak memory	293684 kb
Host	smart-7cff71a3-d867-4cfb-8b35-2f3723c8d272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700422310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_intr_rd.3700422310
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2778073752
Short name	T455
Test name
Test status
Simulation time	10818922900 ps
CPU time	124.98 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:08:01 PM PDT 24
Peak memory	292644 kb
Host	smart-7934a287-824d-420d-a0b3-a1d07c1b5adc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778073752 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2778073752
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.490987777
Short name	T29
Test name
Test status
Simulation time	5328772700 ps
CPU time	73.36 seconds
Started	Jul 25 05:05:57 PM PDT 24
Finished	Jul 25 05:07:11 PM PDT 24
Peak memory	260228 kb
Host	smart-4c2ee4de-8e19-4cb7-aa8f-6e72ad93ce6a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490987777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_intr_wr.490987777
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2937169228
Short name	T531
Test name
Test status
Simulation time	76547540700 ps
CPU time	180.15 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:08:56 PM PDT 24
Peak memory	259464 kb
Host	smart-59c1d464-ffde-4a33-9ffd-6eea067c73af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293 7169228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2937169228
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.4277152980
Short name	T804
Test name
Test status
Simulation time	6822877500 ps
CPU time	64.85 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:55 PM PDT 24
Peak memory	263632 kb
Host	smart-f940f8d8-dc39-498b-b71b-285462bc444a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277152980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.4277152980
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3585808668
Short name	T700
Test name
Test status
Simulation time	17175400 ps
CPU time	13.37 seconds
Started	Jul 25 05:06:10 PM PDT 24
Finished	Jul 25 05:06:24 PM PDT 24
Peak memory	264496 kb
Host	smart-e5682b89-539d-466f-8fe7-36b6e05487be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585808668 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3585808668
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.3150611133
Short name	T58
Test name
Test status
Simulation time	4332486400 ps
CPU time	72.34 seconds
Started	Jul 25 05:06:07 PM PDT 24
Finished	Jul 25 05:07:19 PM PDT 24
Peak memory	260448 kb
Host	smart-47e3638c-259e-404c-bba2-331e063e1b78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150611133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3150611133
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.1505686047
Short name	T142
Test name
Test status
Simulation time	21057564500 ps
CPU time	311.14 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:11:07 PM PDT 24
Peak memory	273948 kb
Host	smart-c3179cb8-6bde-42b3-8281-aeb6114f36dc
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505686047 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.1505686047
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.3175794964
Short name	T638
Test name
Test status
Simulation time	103079300 ps
CPU time	132.29 seconds
Started	Jul 25 05:05:49 PM PDT 24
Finished	Jul 25 05:08:02 PM PDT 24
Peak memory	260840 kb
Host	smart-278099a6-8f09-4e56-b466-8aa9db8283ee
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175794964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot p_reset.3175794964
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.241907858
Short name	T489
Test name
Test status
Simulation time	4109388200 ps
CPU time	177.79 seconds
Started	Jul 25 05:05:59 PM PDT 24
Finished	Jul 25 05:08:57 PM PDT 24
Peak memory	281532 kb
Host	smart-5b4b5d49-98c7-49c5-a09c-8b5ef28a0101
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241907858 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.241907858
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.16593282
Short name	T1075
Test name
Test status
Simulation time	11361312000 ps
CPU time	174.78 seconds
Started	Jul 25 05:05:48 PM PDT 24
Finished	Jul 25 05:08:43 PM PDT 24
Peak memory	262936 kb
Host	smart-31f33605-63d3-4eba-b89c-b1c9e002fa8c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=16593282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.16593282
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3573556890
Short name	T1026
Test name
Test status
Simulation time	15208200 ps
CPU time	13.83 seconds
Started	Jul 25 05:05:57 PM PDT 24
Finished	Jul 25 05:06:11 PM PDT 24
Peak memory	262524 kb
Host	smart-c6aa8a38-d831-48be-9c36-60ec74344e5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573556890 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3573556890
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.2430262371
Short name	T738
Test name
Test status
Simulation time	281630500 ps
CPU time	455.87 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:13:26 PM PDT 24
Peak memory	284176 kb
Host	smart-7dcbceed-8acd-409f-8aa9-981f584364fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430262371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2430262371
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2127742854
Short name	T215
Test name
Test status
Simulation time	3804754300 ps
CPU time	124.1 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:08:00 PM PDT 24
Peak memory	262496 kb
Host	smart-bd91448c-05f4-4f8c-af2e-335ed0dca87d
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2127742854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2127742854
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.4062596046
Short name	T139
Test name
Test status
Simulation time	215385600 ps
CPU time	34.17 seconds
Started	Jul 25 05:06:00 PM PDT 24
Finished	Jul 25 05:06:34 PM PDT 24
Peak memory	275364 kb
Host	smart-b0450d62-349d-4b82-8e8d-cd9e6b38fa50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062596046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.4062596046
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1874801538
Short name	T800
Test name
Test status
Simulation time	19842900 ps
CPU time	22.97 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:06:19 PM PDT 24
Peak memory	265092 kb
Host	smart-b58128e5-9b56-41e6-8a45-d3360e78b496
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874801538 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1874801538
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2861657783
Short name	T534
Test name
Test status
Simulation time	23246500 ps
CPU time	23.12 seconds
Started	Jul 25 05:05:54 PM PDT 24
Finished	Jul 25 05:06:17 PM PDT 24
Peak memory	264664 kb
Host	smart-e87c7710-5daf-4e32-8eaa-c098c278381c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861657783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.2861657783
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.4161625953
Short name	T168
Test name
Test status
Simulation time	332108792000 ps
CPU time	1244.94 seconds
Started	Jul 25 05:06:07 PM PDT 24
Finished	Jul 25 05:26:52 PM PDT 24
Peak memory	261192 kb
Host	smart-002c5245-343f-4f80-a6e5-2d65e4122de0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161625953 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.4161625953
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.3726560459
Short name	T1065
Test name
Test status
Simulation time	585339200 ps
CPU time	128.9 seconds
Started	Jul 25 05:05:55 PM PDT 24
Finished	Jul 25 05:08:04 PM PDT 24
Peak memory	291236 kb
Host	smart-859a96e0-ad19-44e6-9212-9f36d1f0aa90
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726560459 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_ro.3726560459
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.2696567866
Short name	T971
Test name
Test status
Simulation time	771528200 ps
CPU time	156.28 seconds
Started	Jul 25 05:05:58 PM PDT 24
Finished	Jul 25 05:08:34 PM PDT 24
Peak memory	281576 kb
Host	smart-2b31a48f-a605-4980-9cef-de20a38556cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2696567866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2696567866
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.2386101762
Short name	T920
Test name
Test status
Simulation time	7855060500 ps
CPU time	143.38 seconds
Started	Jul 25 05:05:53 PM PDT 24
Finished	Jul 25 05:08:17 PM PDT 24
Peak memory	294368 kb
Host	smart-9dddd472-1e83-4478-8269-92aaec03a45f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386101762 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2386101762
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.4115565876
Short name	T853
Test name
Test status
Simulation time	3764661500 ps
CPU time	487.2 seconds
Started	Jul 25 05:05:52 PM PDT 24
Finished	Jul 25 05:13:59 PM PDT 24
Peak memory	314064 kb
Host	smart-ef1eb8b2-6ab2-442a-be4f-bf1dc0ad3417
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115565876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.flash_ctrl_rw.4115565876
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.2917711760
Short name	T1060
Test name
Test status
Simulation time	9645168300 ps
CPU time	606.37 seconds
Started	Jul 25 05:05:58 PM PDT 24
Finished	Jul 25 05:16:04 PM PDT 24
Peak memory	337684 kb
Host	smart-377a4d36-57f7-4a0f-91bc-b8c221f83d52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917711760 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_rw_derr.2917711760
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.300369539
Short name	T50
Test name
Test status
Simulation time	29938400 ps
CPU time	30.79 seconds
Started	Jul 25 05:05:59 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	268180 kb
Host	smart-4ca0fb26-0924-4473-9381-39fba8b73a83
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300369539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_rw_evict.300369539
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2568397620
Short name	T784
Test name
Test status
Simulation time	41686100 ps
CPU time	30.79 seconds
Started	Jul 25 05:05:59 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	267156 kb
Host	smart-55695ad8-01bd-49a2-8bfc-56edf7c807b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568397620 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2568397620
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_serr.3919685526
Short name	T211
Test name
Test status
Simulation time	3548317700 ps
CPU time	582.73 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:15:39 PM PDT 24
Peak memory	312836 kb
Host	smart-36db547d-53b8-4519-89e0-93fbdaf3b8e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919685526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s err.3919685526
Directory	/workspace/1.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.884321070
Short name	T15
Test name
Test status
Simulation time	5601468900 ps
CPU time	4829.68 seconds
Started	Jul 25 05:05:58 PM PDT 24
Finished	Jul 25 06:26:28 PM PDT 24
Peak memory	283896 kb
Host	smart-2cc318a8-d5f7-4d09-9f21-aa4d0e96b410
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884321070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.884321070
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.775731532
Short name	T1069
Test name
Test status
Simulation time	3931974900 ps
CPU time	59.1 seconds
Started	Jul 25 05:06:03 PM PDT 24
Finished	Jul 25 05:07:03 PM PDT 24
Peak memory	262988 kb
Host	smart-01c68d5f-8b43-4819-be63-016032306371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775731532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.775731532
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.1207540699
Short name	T688
Test name
Test status
Simulation time	889957000 ps
CPU time	56.12 seconds
Started	Jul 25 05:05:58 PM PDT 24
Finished	Jul 25 05:06:54 PM PDT 24
Peak memory	265088 kb
Host	smart-6810a1bb-29fc-403c-8206-a29d47a930d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207540699 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.1207540699
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.4203874456
Short name	T987
Test name
Test status
Simulation time	2614406800 ps
CPU time	73.85 seconds
Started	Jul 25 05:05:56 PM PDT 24
Finished	Jul 25 05:07:10 PM PDT 24
Peak memory	273384 kb
Host	smart-9694270a-df6a-469a-a52d-70e45a5a1d70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203874456 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_serr_counter.4203874456
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.3816120003
Short name	T1078
Test name
Test status
Simulation time	23670400 ps
CPU time	101.14 seconds
Started	Jul 25 05:05:52 PM PDT 24
Finished	Jul 25 05:07:33 PM PDT 24
Peak memory	276620 kb
Host	smart-da694b7d-6abe-4ccb-9b96-dafb6c5c081b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816120003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3816120003
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.798606544
Short name	T447
Test name
Test status
Simulation time	56155600 ps
CPU time	24.37 seconds
Started	Jul 25 05:05:51 PM PDT 24
Finished	Jul 25 05:06:16 PM PDT 24
Peak memory	259496 kb
Host	smart-7495a2fe-befa-476b-a39e-64be49ad3f92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798606544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.798606544
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.449140036
Short name	T944
Test name
Test status
Simulation time	88898300 ps
CPU time	193.35 seconds
Started	Jul 25 05:05:58 PM PDT 24
Finished	Jul 25 05:09:11 PM PDT 24
Peak memory	278492 kb
Host	smart-2af5232e-fb64-4356-ace6-1a1f33cc4084
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449140036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress _all.449140036
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.394227993
Short name	T592
Test name
Test status
Simulation time	24250700 ps
CPU time	26.52 seconds
Started	Jul 25 05:05:50 PM PDT 24
Finished	Jul 25 05:06:16 PM PDT 24
Peak memory	259444 kb
Host	smart-d6c1c37b-3f9b-40cc-bac3-a20eb7e0f8e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394227993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.394227993
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.3792524371
Short name	T632
Test name
Test status
Simulation time	2929518900 ps
CPU time	189.28 seconds
Started	Jul 25 05:05:48 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	259592 kb
Host	smart-f180ffbe-1cb3-4cef-966d-9defe84a1bac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792524371 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_wo.3792524371
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.2418097953
Short name	T8
Test name
Test status
Simulation time	44744800 ps
CPU time	14.93 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:06:21 PM PDT 24
Peak memory	260176 kb
Host	smart-458b9672-8552-4ca0-b076-b86b301d97b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418097953 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2418097953
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.966478815
Short name	T665
Test name
Test status
Simulation time	59729600 ps
CPU time	13.68 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:07:39 PM PDT 24
Peak memory	257760 kb
Host	smart-aa91349d-f4c2-4f19-af47-fd463aa3d286
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966478815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.966478815
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.2377013323
Short name	T1089
Test name
Test status
Simulation time	103377100 ps
CPU time	13.88 seconds
Started	Jul 25 05:07:19 PM PDT 24
Finished	Jul 25 05:07:33 PM PDT 24
Peak memory	284004 kb
Host	smart-f6fe0de5-3a18-482e-9a2f-6f1923f88218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377013323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2377013323
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.2591855647
Short name	T976
Test name
Test status
Simulation time	21490300 ps
CPU time	21.85 seconds
Started	Jul 25 05:07:20 PM PDT 24
Finished	Jul 25 05:07:42 PM PDT 24
Peak memory	265212 kb
Host	smart-739a60e7-58f8-4120-b4ee-2194c87c6841
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591855647 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.2591855647
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.595040709
Short name	T328
Test name
Test status
Simulation time	15606800 ps
CPU time	13.53 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:07:30 PM PDT 24
Peak memory	259716 kb
Host	smart-fb9bc761-16e2-4b4b-8a25-d2504b98e3c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595040709 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.595040709
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1299442357
Short name	T631
Test name
Test status
Simulation time	40117680900 ps
CPU time	839.64 seconds
Started	Jul 25 05:07:21 PM PDT 24
Finished	Jul 25 05:21:20 PM PDT 24
Peak memory	260720 kb
Host	smart-746a92b7-53c0-49cc-ae1f-f3ae7a88612b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299442357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.1299442357
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1493030522
Short name	T461
Test name
Test status
Simulation time	2877749200 ps
CPU time	104 seconds
Started	Jul 25 05:07:15 PM PDT 24
Finished	Jul 25 05:08:59 PM PDT 24
Peak memory	263016 kb
Host	smart-93b5eb1d-d96d-4215-bf9d-37c27e755f22
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493030522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ hw_sec_otp.1493030522
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1991394880
Short name	T863
Test name
Test status
Simulation time	12012256600 ps
CPU time	170.45 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:10:06 PM PDT 24
Peak memory	293968 kb
Host	smart-4fbec045-390a-4738-b971-c292f7469de1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991394880 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1991394880
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.3675581780
Short name	T212
Test name
Test status
Simulation time	3889150800 ps
CPU time	89.74 seconds
Started	Jul 25 05:07:21 PM PDT 24
Finished	Jul 25 05:08:51 PM PDT 24
Peak memory	260384 kb
Host	smart-2fc9db14-c7b4-4465-b64a-71758c1a23f7
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675581780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3 675581780
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3004707557
Short name	T275
Test name
Test status
Simulation time	25604900 ps
CPU time	13.39 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:07:31 PM PDT 24
Peak memory	260308 kb
Host	smart-0a207c4e-7c8b-4e7c-a261-00e974026b93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004707557 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3004707557
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.3945064774
Short name	T147
Test name
Test status
Simulation time	23890201600 ps
CPU time	312.51 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:12:30 PM PDT 24
Peak memory	274612 kb
Host	smart-78ccb57f-eb90-4bdc-ae86-5fe6b22e2e22
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945064774 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.3945064774
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.1931855247
Short name	T462
Test name
Test status
Simulation time	102788900 ps
CPU time	133.12 seconds
Started	Jul 25 05:07:18 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	261936 kb
Host	smart-519fd947-2063-432d-9e5d-cc4cb5b79002
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931855247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o tp_reset.1931855247
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3177074990
Short name	T528
Test name
Test status
Simulation time	21870500 ps
CPU time	68.59 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:08:26 PM PDT 24
Peak memory	262952 kb
Host	smart-6930f505-68ec-4aa1-810c-289cc5d7ff86
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3177074990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3177074990
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.3132152053
Short name	T697
Test name
Test status
Simulation time	39473600 ps
CPU time	13.66 seconds
Started	Jul 25 05:07:15 PM PDT 24
Finished	Jul 25 05:07:29 PM PDT 24
Peak memory	258800 kb
Host	smart-08027fe7-f176-42a5-9633-a5736cf051ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132152053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.flash_ctrl_prog_reset.3132152053
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.1599026291
Short name	T676
Test name
Test status
Simulation time	1323759400 ps
CPU time	922.54 seconds
Started	Jul 25 05:07:19 PM PDT 24
Finished	Jul 25 05:22:41 PM PDT 24
Peak memory	287140 kb
Host	smart-94895a1a-a83c-49ba-bea6-23cf0cd6c762
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599026291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1599026291
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.1386213104
Short name	T140
Test name
Test status
Simulation time	348894700 ps
CPU time	35.16 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:07:53 PM PDT 24
Peak memory	275336 kb
Host	smart-74ecd408-55a8-4e77-87a6-e63cd0a21595
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386213104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.1386213104
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.422056846
Short name	T1099
Test name
Test status
Simulation time	1947544200 ps
CPU time	116.71 seconds
Started	Jul 25 05:07:19 PM PDT 24
Finished	Jul 25 05:09:16 PM PDT 24
Peak memory	289496 kb
Host	smart-8521cfb6-3431-46c1-b200-ee45a289aa19
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422056846 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.flash_ctrl_ro.422056846
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.3697826849
Short name	T205
Test name
Test status
Simulation time	3149585900 ps
CPU time	511.72 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:15:59 PM PDT 24
Peak memory	309668 kb
Host	smart-07fb9a64-5990-4483-86ee-a9eb63a1477b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697826849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.3697826849
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.1737961828
Short name	T336
Test name
Test status
Simulation time	52370300 ps
CPU time	30.44 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	275376 kb
Host	smart-45c5fe09-d7aa-4300-80ca-ec204a17c59b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737961828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_rw_evict.1737961828
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.854033260
Short name	T880
Test name
Test status
Simulation time	29219000 ps
CPU time	31.25 seconds
Started	Jul 25 05:07:19 PM PDT 24
Finished	Jul 25 05:07:50 PM PDT 24
Peak memory	275208 kb
Host	smart-376efb88-a0d9-4cc4-a352-615eae23488d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854033260 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.854033260
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.228817152
Short name	T298
Test name
Test status
Simulation time	64177300 ps
CPU time	49.77 seconds
Started	Jul 25 05:07:19 PM PDT 24
Finished	Jul 25 05:08:09 PM PDT 24
Peak memory	271052 kb
Host	smart-d8843ce8-a00f-4ddd-809e-76206b88d0fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228817152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.228817152
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.2567551044
Short name	T607
Test name
Test status
Simulation time	11720250600 ps
CPU time	195.63 seconds
Started	Jul 25 05:07:20 PM PDT 24
Finished	Jul 25 05:10:36 PM PDT 24
Peak memory	264960 kb
Host	smart-cce4ed76-8eb9-4186-ba63-f72382d281f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567551044 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.2567551044
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.723000110
Short name	T814
Test name
Test status
Simulation time	29379200 ps
CPU time	14.11 seconds
Started	Jul 25 05:07:32 PM PDT 24
Finished	Jul 25 05:07:46 PM PDT 24
Peak memory	264920 kb
Host	smart-e58b6703-4ed5-4f51-8159-5cc5894a24d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723000110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.723000110
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.3294051534
Short name	T907
Test name
Test status
Simulation time	13441700 ps
CPU time	13.46 seconds
Started	Jul 25 05:07:31 PM PDT 24
Finished	Jul 25 05:07:44 PM PDT 24
Peak memory	282772 kb
Host	smart-b6d387c2-b20e-4655-8b31-f11d976295b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294051534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3294051534
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3637297513
Short name	T172
Test name
Test status
Simulation time	10012196200 ps
CPU time	110.6 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:09:16 PM PDT 24
Peak memory	299884 kb
Host	smart-8435369c-b663-4f59-aea5-69f3f2abd1f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637297513 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3637297513
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3931278478
Short name	T1097
Test name
Test status
Simulation time	25511200 ps
CPU time	13.51 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:07:41 PM PDT 24
Peak memory	259700 kb
Host	smart-e6d2f7c6-d978-47dc-8a7f-19560240809f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931278478 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3931278478
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3545912844
Short name	T185
Test name
Test status
Simulation time	40120321900 ps
CPU time	825.42 seconds
Started	Jul 25 05:07:28 PM PDT 24
Finished	Jul 25 05:21:13 PM PDT 24
Peak memory	264056 kb
Host	smart-3dcaf8bf-7f42-47b8-be6a-75231fb3104b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545912844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_hw_rma_reset.3545912844
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.355030146
Short name	T608
Test name
Test status
Simulation time	1026672300 ps
CPU time	46.49 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:08:12 PM PDT 24
Peak memory	260616 kb
Host	smart-48623cf5-3353-4873-9a44-69316b1f13ec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355030146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h w_sec_otp.355030146
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.402163450
Short name	T321
Test name
Test status
Simulation time	10529321100 ps
CPU time	206.49 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:10:53 PM PDT 24
Peak memory	284528 kb
Host	smart-427b5cc6-0e75-433c-85b5-551f7bf0f19d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402163450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_intr_rd.402163450
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2140098054
Short name	T418
Test name
Test status
Simulation time	6291012100 ps
CPU time	152.24 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	292220 kb
Host	smart-8c6037e6-b7d2-4a27-a5d8-cbfe15f213bd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140098054 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2140098054
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.1869366493
Short name	T812
Test name
Test status
Simulation time	2677170600 ps
CPU time	61.62 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:08:28 PM PDT 24
Peak memory	263028 kb
Host	smart-357c69ce-8144-461c-92b7-9880dd61bef3
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869366493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1 869366493
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2040576527
Short name	T753
Test name
Test status
Simulation time	47808300 ps
CPU time	13.52 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:07:41 PM PDT 24
Peak memory	259432 kb
Host	smart-0022f7c1-b07b-492d-abda-ce0b45f715fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040576527 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2040576527
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.1361159916
Short name	T586
Test name
Test status
Simulation time	77980204400 ps
CPU time	152.24 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:09:59 PM PDT 24
Peak memory	263220 kb
Host	smart-ce1a5891-5659-4be2-93e0-1ef1e1d5872f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361159916 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.1361159916
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.761005801
Short name	T18
Test name
Test status
Simulation time	36474600 ps
CPU time	111.21 seconds
Started	Jul 25 05:07:31 PM PDT 24
Finished	Jul 25 05:09:23 PM PDT 24
Peak memory	259892 kb
Host	smart-caf71825-a326-4a15-99e4-fad88e3cca25
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761005801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot p_reset.761005801
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.4279624588
Short name	T622
Test name
Test status
Simulation time	66365100 ps
CPU time	278 seconds
Started	Jul 25 05:07:28 PM PDT 24
Finished	Jul 25 05:12:06 PM PDT 24
Peak memory	262912 kb
Host	smart-d976a042-728a-4eaa-8451-ef823ebc573d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4279624588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.4279624588
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.3033991817
Short name	T614
Test name
Test status
Simulation time	47156800 ps
CPU time	13.85 seconds
Started	Jul 25 05:07:25 PM PDT 24
Finished	Jul 25 05:07:39 PM PDT 24
Peak memory	259448 kb
Host	smart-0917dc64-1d08-456d-8928-2c0db3debd1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033991817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.3033991817
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.1820674259
Short name	T795
Test name
Test status
Simulation time	39326100 ps
CPU time	250.74 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:11:37 PM PDT 24
Peak memory	279520 kb
Host	smart-a39fe884-20fa-433f-a30c-862080fcf6e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820674259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1820674259
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.3375609624
Short name	T541
Test name
Test status
Simulation time	216500500 ps
CPU time	34.15 seconds
Started	Jul 25 05:07:25 PM PDT 24
Finished	Jul 25 05:08:00 PM PDT 24
Peak memory	267184 kb
Host	smart-b2339b10-f25b-40e5-ad95-6bde8fb0b783
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375609624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_re_evict.3375609624
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.4088424397
Short name	T64
Test name
Test status
Simulation time	2020343800 ps
CPU time	124.13 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	281376 kb
Host	smart-863b0526-cbde-4d9c-9fbc-61785ea5d8a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088424397 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.4088424397
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.2887755135
Short name	T216
Test name
Test status
Simulation time	15079743300 ps
CPU time	717.74 seconds
Started	Jul 25 05:07:27 PM PDT 24
Finished	Jul 25 05:19:25 PM PDT 24
Peak memory	312976 kb
Host	smart-d2c78016-3154-4596-8f69-ed667ca679c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887755135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.2887755135
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.968481274
Short name	T718
Test name
Test status
Simulation time	36331800 ps
CPU time	30.8 seconds
Started	Jul 25 05:07:30 PM PDT 24
Finished	Jul 25 05:08:01 PM PDT 24
Peak memory	275332 kb
Host	smart-926d8115-5496-4a85-bcaf-1c9584f11f79
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968481274 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.968481274
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.1387854164
Short name	T527
Test name
Test status
Simulation time	7181693500 ps
CPU time	78.71 seconds
Started	Jul 25 05:07:30 PM PDT 24
Finished	Jul 25 05:08:49 PM PDT 24
Peak memory	263472 kb
Host	smart-ee1c902f-ed53-41f2-ba0a-da7d066491db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387854164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1387854164
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.1578918822
Short name	T371
Test name
Test status
Simulation time	24353600 ps
CPU time	126.28 seconds
Started	Jul 25 05:07:25 PM PDT 24
Finished	Jul 25 05:09:32 PM PDT 24
Peak memory	277052 kb
Host	smart-7337b351-513f-43ff-81e2-9b3454cf34fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578918822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1578918822
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.517882976
Short name	T827
Test name
Test status
Simulation time	1528337600 ps
CPU time	141.84 seconds
Started	Jul 25 05:07:25 PM PDT 24
Finished	Jul 25 05:09:47 PM PDT 24
Peak memory	260632 kb
Host	smart-4a363746-d249-4a33-91a1-7ad298cf5983
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517882976 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.flash_ctrl_wo.517882976
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.647128415
Short name	T530
Test name
Test status
Simulation time	30731000 ps
CPU time	13.38 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:07:52 PM PDT 24
Peak memory	264820 kb
Host	smart-1820f741-b0ff-487f-98d4-4935378ef34f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647128415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.647128415
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.2057210017
Short name	T441
Test name
Test status
Simulation time	145908000 ps
CPU time	15.84 seconds
Started	Jul 25 05:07:40 PM PDT 24
Finished	Jul 25 05:07:56 PM PDT 24
Peak memory	284068 kb
Host	smart-ede4a7f5-4f96-4785-9423-76a5dfd6321f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057210017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2057210017
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.298843289
Short name	T121
Test name
Test status
Simulation time	10986400 ps
CPU time	20.63 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:07:58 PM PDT 24
Peak memory	273168 kb
Host	smart-998de894-9118-442d-9deb-43b38608b7f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298843289 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.298843289
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3589413245
Short name	T980
Test name
Test status
Simulation time	10014990300 ps
CPU time	82.58 seconds
Started	Jul 25 05:07:37 PM PDT 24
Finished	Jul 25 05:08:59 PM PDT 24
Peak memory	302044 kb
Host	smart-f8ebe07e-6af5-44da-9463-db2ae9123d71
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589413245 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3589413245
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.594959907
Short name	T926
Test name
Test status
Simulation time	72065700 ps
CPU time	13.43 seconds
Started	Jul 25 05:07:37 PM PDT 24
Finished	Jul 25 05:07:51 PM PDT 24
Peak memory	264472 kb
Host	smart-6491bce5-5af5-4d7c-ade0-75a007cccfed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594959907 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.594959907
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2417864023
Short name	T116
Test name
Test status
Simulation time	160155031900 ps
CPU time	955.33 seconds
Started	Jul 25 05:07:40 PM PDT 24
Finished	Jul 25 05:23:35 PM PDT 24
Peak memory	260664 kb
Host	smart-433b9543-44ab-48a4-ac42-7431ae8ce55d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417864023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.flash_ctrl_hw_rma_reset.2417864023
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.1607909980
Short name	T771
Test name
Test status
Simulation time	3638142700 ps
CPU time	209.44 seconds
Started	Jul 25 05:07:40 PM PDT 24
Finished	Jul 25 05:11:10 PM PDT 24
Peak memory	284616 kb
Host	smart-4f7efd04-9413-471f-94e6-cc958902224d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607909980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.1607909980
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.372515651
Short name	T813
Test name
Test status
Simulation time	28283671100 ps
CPU time	304.49 seconds
Started	Jul 25 05:07:37 PM PDT 24
Finished	Jul 25 05:12:41 PM PDT 24
Peak memory	291120 kb
Host	smart-0c120bf3-d04a-44bb-88f6-a78bb790bd81
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372515651 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.372515651
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.3368487466
Short name	T420
Test name
Test status
Simulation time	3550607400 ps
CPU time	68.11 seconds
Started	Jul 25 05:07:39 PM PDT 24
Finished	Jul 25 05:08:47 PM PDT 24
Peak memory	263156 kb
Host	smart-5dfda56c-8866-41ca-a154-dab7db8814cf
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368487466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3 368487466
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1310041090
Short name	T164
Test name
Test status
Simulation time	16375300 ps
CPU time	13.88 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:07:52 PM PDT 24
Peak memory	264608 kb
Host	smart-2d96d20b-a575-4f07-824a-19d554b300f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310041090 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1310041090
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.1266971768
Short name	T135
Test name
Test status
Simulation time	28591948900 ps
CPU time	301.02 seconds
Started	Jul 25 05:07:41 PM PDT 24
Finished	Jul 25 05:12:42 PM PDT 24
Peak memory	274380 kb
Host	smart-53aca6ec-fdd5-4a15-89a0-1a7c52591b29
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266971768 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.1266971768
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.691157898
Short name	T831
Test name
Test status
Simulation time	67116800 ps
CPU time	108.55 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:09:27 PM PDT 24
Peak memory	264776 kb
Host	smart-18cfb541-4a26-41d3-8b57-dbd8a4801e99
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691157898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ot p_reset.691157898
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.2092679047
Short name	T450
Test name
Test status
Simulation time	74505700 ps
CPU time	405.98 seconds
Started	Jul 25 05:07:24 PM PDT 24
Finished	Jul 25 05:14:10 PM PDT 24
Peak memory	262904 kb
Host	smart-6617d06b-4862-4fcb-95ac-603f9ac98210
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2092679047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2092679047
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.3793034537
Short name	T978
Test name
Test status
Simulation time	4211065700 ps
CPU time	168.93 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:10:27 PM PDT 24
Peak memory	259544 kb
Host	smart-5f3ee4e9-9039-4fcd-9483-f8ec6f97d262
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793034537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.3793034537
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.4073513423
Short name	T1046
Test name
Test status
Simulation time	1198546600 ps
CPU time	742.97 seconds
Started	Jul 25 05:07:29 PM PDT 24
Finished	Jul 25 05:19:53 PM PDT 24
Peak memory	284928 kb
Host	smart-304dc514-1a0f-4653-98c0-d60a7d27dfda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073513423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.4073513423
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.3073642733
Short name	T339
Test name
Test status
Simulation time	130343000 ps
CPU time	34.06 seconds
Started	Jul 25 05:07:37 PM PDT 24
Finished	Jul 25 05:08:11 PM PDT 24
Peak memory	275352 kb
Host	smart-47e030c0-e388-4c77-84d6-6c0a563a316e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073642733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_re_evict.3073642733
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.235873639
Short name	T1081
Test name
Test status
Simulation time	2320444700 ps
CPU time	126.5 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:09:44 PM PDT 24
Peak memory	281504 kb
Host	smart-a78fe84b-89e0-4312-8a02-4d6a3f526f3b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235873639 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.flash_ctrl_ro.235873639
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.888620055
Short name	T557
Test name
Test status
Simulation time	5062464000 ps
CPU time	628.27 seconds
Started	Jul 25 05:07:38 PM PDT 24
Finished	Jul 25 05:18:07 PM PDT 24
Peak memory	309536 kb
Host	smart-dc74602d-d6a5-4e2f-aab0-752d6b892cfc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888620055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.888620055
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.3244431768
Short name	T783
Test name
Test status
Simulation time	44877400 ps
CPU time	28.51 seconds
Started	Jul 25 05:07:37 PM PDT 24
Finished	Jul 25 05:08:06 PM PDT 24
Peak memory	273316 kb
Host	smart-8c3c0746-63e5-4d14-be06-893ade579ffd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244431768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.3244431768
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.2852776215
Short name	T1105
Test name
Test status
Simulation time	37834800 ps
CPU time	172.05 seconds
Started	Jul 25 05:07:26 PM PDT 24
Finished	Jul 25 05:10:18 PM PDT 24
Peak memory	278040 kb
Host	smart-6b4eeb23-ca0c-4574-b139-ab704747b03e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852776215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2852776215
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.3956853430
Short name	T381
Test name
Test status
Simulation time	2605677300 ps
CPU time	215.95 seconds
Started	Jul 25 05:07:37 PM PDT 24
Finished	Jul 25 05:11:13 PM PDT 24
Peak memory	264952 kb
Host	smart-d60065c7-d742-4cfc-9a1f-9e70917e905f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956853430 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.flash_ctrl_wo.3956853430
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.1093617771
Short name	T678
Test name
Test status
Simulation time	48390000 ps
CPU time	14.16 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:08:02 PM PDT 24
Peak memory	257812 kb
Host	smart-3dff0b2e-6763-4d48-b037-08c270a2b204
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093617771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 1093617771
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.881735048
Short name	T637
Test name
Test status
Simulation time	14760000 ps
CPU time	15.94 seconds
Started	Jul 25 05:07:52 PM PDT 24
Finished	Jul 25 05:08:08 PM PDT 24
Peak memory	274820 kb
Host	smart-daa7c4ba-1a0a-4a21-bf39-6664e58568bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881735048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.881735048
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3890651351
Short name	T576
Test name
Test status
Simulation time	10018747300 ps
CPU time	73.98 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:09:01 PM PDT 24
Peak memory	285208 kb
Host	smart-ba133550-caa3-4f84-a6a9-03dd8412aa31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890651351 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3890651351
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.2361231366
Short name	T136
Test name
Test status
Simulation time	21839900 ps
CPU time	13.4 seconds
Started	Jul 25 05:07:53 PM PDT 24
Finished	Jul 25 05:08:07 PM PDT 24
Peak memory	264720 kb
Host	smart-7ad4e0a6-de39-42d3-b850-7a38a264cd5d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361231366 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.2361231366
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2650257257
Short name	T870
Test name
Test status
Simulation time	160159867900 ps
CPU time	802.59 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:21:10 PM PDT 24
Peak memory	264200 kb
Host	smart-bd3e95fd-0c0e-4c09-b9ea-e9bd94e37380
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650257257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.2650257257
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2966097380
Short name	T438
Test name
Test status
Simulation time	2008825900 ps
CPU time	48.48 seconds
Started	Jul 25 05:07:52 PM PDT 24
Finished	Jul 25 05:08:40 PM PDT 24
Peak memory	260904 kb
Host	smart-15e18e11-9eef-4786-a1ee-959e6301a3c0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966097380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.2966097380
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.2390675837
Short name	T471
Test name
Test status
Simulation time	1234106600 ps
CPU time	132.67 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	293720 kb
Host	smart-5d94a448-206a-487e-b3dd-6b7d5880ec97
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390675837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.2390675837
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.617017411
Short name	T1085
Test name
Test status
Simulation time	8777833000 ps
CPU time	192.49 seconds
Started	Jul 25 05:07:52 PM PDT 24
Finished	Jul 25 05:11:05 PM PDT 24
Peak memory	292756 kb
Host	smart-f0bdc244-ec29-4d19-88e3-d3ffe47d7153
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617017411 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.617017411
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.3241188252
Short name	T818
Test name
Test status
Simulation time	6493760500 ps
CPU time	68.63 seconds
Started	Jul 25 05:07:51 PM PDT 24
Finished	Jul 25 05:09:00 PM PDT 24
Peak memory	259864 kb
Host	smart-273d0579-43e3-4244-8b2c-d1cde2c34e32
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241188252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3 241188252
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2816860571
Short name	T690
Test name
Test status
Simulation time	42993200 ps
CPU time	13.53 seconds
Started	Jul 25 05:07:52 PM PDT 24
Finished	Jul 25 05:08:06 PM PDT 24
Peak memory	260404 kb
Host	smart-ded4e7a3-60f9-4117-ba5a-09bb094976ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816860571 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2816860571
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.4045869399
Short name	T80
Test name
Test status
Simulation time	11781932500 ps
CPU time	660.02 seconds
Started	Jul 25 05:07:55 PM PDT 24
Finished	Jul 25 05:18:55 PM PDT 24
Peak memory	275316 kb
Host	smart-90d5172a-f787-4aff-a4ce-43eab2c0b252
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045869399 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.4045869399
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.1015959004
Short name	T663
Test name
Test status
Simulation time	119544300 ps
CPU time	133.69 seconds
Started	Jul 25 05:07:50 PM PDT 24
Finished	Jul 25 05:10:04 PM PDT 24
Peak memory	259808 kb
Host	smart-7cb9aa18-f9e2-4517-a8dc-7870c6d799e2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015959004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.1015959004
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.642709777
Short name	T517
Test name
Test status
Simulation time	46249900 ps
CPU time	181.21 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:10:48 PM PDT 24
Peak memory	262856 kb
Host	smart-465ad988-11a1-4eb1-ac87-331095b7a89b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=642709777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.642709777
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.1298880126
Short name	T382
Test name
Test status
Simulation time	35090700 ps
CPU time	13.62 seconds
Started	Jul 25 05:07:50 PM PDT 24
Finished	Jul 25 05:08:04 PM PDT 24
Peak memory	258772 kb
Host	smart-f6d07c44-3b21-4b24-8287-02d5845fec27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298880126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.1298880126
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.91636369
Short name	T1093
Test name
Test status
Simulation time	48209600 ps
CPU time	348.36 seconds
Started	Jul 25 05:07:48 PM PDT 24
Finished	Jul 25 05:13:37 PM PDT 24
Peak memory	281248 kb
Host	smart-5cc11c07-f6df-4b8f-a5b2-493ab6b6814f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91636369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.91636369
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.3116123440
Short name	T112
Test name
Test status
Simulation time	264634800 ps
CPU time	35.35 seconds
Started	Jul 25 05:07:48 PM PDT 24
Finished	Jul 25 05:08:23 PM PDT 24
Peak memory	275260 kb
Host	smart-62d2d072-2125-44f3-b095-038400249231
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116123440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.3116123440
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.2205487034
Short name	T267
Test name
Test status
Simulation time	4934566000 ps
CPU time	123.2 seconds
Started	Jul 25 05:07:54 PM PDT 24
Finished	Jul 25 05:09:57 PM PDT 24
Peak memory	289780 kb
Host	smart-ebe99d08-a466-4bf5-87a6-cda930021c02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205487034 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.2205487034
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw.3024697300
Short name	T197
Test name
Test status
Simulation time	4320348800 ps
CPU time	515.74 seconds
Started	Jul 25 05:07:51 PM PDT 24
Finished	Jul 25 05:16:27 PM PDT 24
Peak memory	308988 kb
Host	smart-2608c2c3-9970-45d8-8274-07477cec5538
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024697300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.flash_ctrl_rw.3024697300
Directory	/workspace/13.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1973759550
Short name	T969
Test name
Test status
Simulation time	67996700 ps
CPU time	27.76 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:08:15 PM PDT 24
Peak memory	273412 kb
Host	smart-68be2d19-edb3-4921-b44f-aae50296ba7f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973759550 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1973759550
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.3892056622
Short name	T666
Test name
Test status
Simulation time	2241799600 ps
CPU time	76.98 seconds
Started	Jul 25 05:07:51 PM PDT 24
Finished	Jul 25 05:09:08 PM PDT 24
Peak memory	263824 kb
Host	smart-1b1e4c93-3a1a-42ec-9c08-a0465544dd4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3892056622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3892056622
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.99041408
Short name	T513
Test name
Test status
Simulation time	26951900 ps
CPU time	99.77 seconds
Started	Jul 25 05:07:40 PM PDT 24
Finished	Jul 25 05:09:20 PM PDT 24
Peak memory	277072 kb
Host	smart-516a1f5b-e99c-4432-bfef-bf8d09978d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99041408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.99041408
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.1559097241
Short name	T459
Test name
Test status
Simulation time	26969764500 ps
CPU time	227.6 seconds
Started	Jul 25 05:07:47 PM PDT 24
Finished	Jul 25 05:11:35 PM PDT 24
Peak memory	259536 kb
Host	smart-f20ef0d1-e8ae-4be4-b92f-af4f9e437e67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559097241 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.flash_ctrl_wo.1559097241
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.3453777307
Short name	T793
Test name
Test status
Simulation time	26287300 ps
CPU time	13.94 seconds
Started	Jul 25 05:07:56 PM PDT 24
Finished	Jul 25 05:08:11 PM PDT 24
Peak memory	264744 kb
Host	smart-d7519713-ebcf-46b9-9cfb-d9c37f098e9f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453777307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 3453777307
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.3817286567
Short name	T1021
Test name
Test status
Simulation time	44903200 ps
CPU time	15.86 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:08:13 PM PDT 24
Peak memory	284276 kb
Host	smart-f223abfa-411c-47cf-bef6-1730be230ff1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817286567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3817286567
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.4040784376
Short name	T546
Test name
Test status
Simulation time	10012088500 ps
CPU time	122.58 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	331188 kb
Host	smart-81238ebc-20db-4969-bb19-b89d0a98304a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040784376 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.4040784376
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.3217006522
Short name	T161
Test name
Test status
Simulation time	54328200 ps
CPU time	13.44 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:08:21 PM PDT 24
Peak memory	259852 kb
Host	smart-175af46a-819f-4531-80b4-e31d3dddc36f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217006522 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.3217006522
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.347078102
Short name	T473
Test name
Test status
Simulation time	40126741000 ps
CPU time	859.34 seconds
Started	Jul 25 05:07:49 PM PDT 24
Finished	Jul 25 05:22:08 PM PDT 24
Peak memory	260780 kb
Host	smart-55f43d27-28f7-4f56-a9e5-06fc93741b11
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347078102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.flash_ctrl_hw_rma_reset.347078102
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1632594431
Short name	T126
Test name
Test status
Simulation time	3976340000 ps
CPU time	140.97 seconds
Started	Jul 25 05:07:49 PM PDT 24
Finished	Jul 25 05:10:10 PM PDT 24
Peak memory	263044 kb
Host	smart-fd5b042e-35cb-457d-9828-07a082b34798
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632594431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ hw_sec_otp.1632594431
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.3397086156
Short name	T935
Test name
Test status
Simulation time	679259700 ps
CPU time	126.6 seconds
Started	Jul 25 05:07:58 PM PDT 24
Finished	Jul 25 05:10:05 PM PDT 24
Peak memory	293848 kb
Host	smart-56a68f3c-95a6-4770-8018-4665498e3076
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397086156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_intr_rd.3397086156
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.837571490
Short name	T497
Test name
Test status
Simulation time	11720766300 ps
CPU time	149.58 seconds
Started	Jul 25 05:07:56 PM PDT 24
Finished	Jul 25 05:10:25 PM PDT 24
Peak memory	292160 kb
Host	smart-db5ca4de-9e08-4271-949a-a25256745fbe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837571490 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.837571490
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.1583629033
Short name	T278
Test name
Test status
Simulation time	1008509400 ps
CPU time	86.79 seconds
Started	Jul 25 05:07:59 PM PDT 24
Finished	Jul 25 05:09:26 PM PDT 24
Peak memory	260360 kb
Host	smart-4fcd00b2-8cc0-4ee2-acc5-7ce6e634f94b
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583629033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1 583629033
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2419016343
Short name	T598
Test name
Test status
Simulation time	30959200 ps
CPU time	13.43 seconds
Started	Jul 25 05:07:56 PM PDT 24
Finished	Jul 25 05:08:10 PM PDT 24
Peak memory	260452 kb
Host	smart-e2d1eb1f-011d-4e85-90ee-0a410f0b95b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419016343 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2419016343
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.2340404563
Short name	T143
Test name
Test status
Simulation time	10021995700 ps
CPU time	665.09 seconds
Started	Jul 25 05:07:48 PM PDT 24
Finished	Jul 25 05:18:53 PM PDT 24
Peak memory	274468 kb
Host	smart-f64e097d-9d1d-4f4a-8fa2-eab1642ef258
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340404563 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2340404563
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.3898016333
Short name	T779
Test name
Test status
Simulation time	479191800 ps
CPU time	130.89 seconds
Started	Jul 25 05:07:51 PM PDT 24
Finished	Jul 25 05:10:02 PM PDT 24
Peak memory	260668 kb
Host	smart-c0e28f13-4b2d-4bed-8f93-d76a9658db3b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898016333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o tp_reset.3898016333
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.1133350307
Short name	T433
Test name
Test status
Simulation time	1033789900 ps
CPU time	410.94 seconds
Started	Jul 25 05:07:54 PM PDT 24
Finished	Jul 25 05:14:45 PM PDT 24
Peak memory	262816 kb
Host	smart-2c67c8a4-f502-414f-9811-ebcf93722e52
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1133350307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1133350307
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.1171142677
Short name	T502
Test name
Test status
Simulation time	21436200 ps
CPU time	13.51 seconds
Started	Jul 25 05:07:58 PM PDT 24
Finished	Jul 25 05:08:12 PM PDT 24
Peak memory	258964 kb
Host	smart-ea180860-3fd3-43b8-9c52-2dc758e2e706
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171142677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.1171142677
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.207978333
Short name	T141
Test name
Test status
Simulation time	1409600500 ps
CPU time	598.18 seconds
Started	Jul 25 05:07:50 PM PDT 24
Finished	Jul 25 05:17:48 PM PDT 24
Peak memory	285108 kb
Host	smart-0519c146-c0c3-4b93-bd81-c1209ac5ae6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207978333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.207978333
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.76585862
Short name	T209
Test name
Test status
Simulation time	113176000 ps
CPU time	35.52 seconds
Started	Jul 25 05:08:01 PM PDT 24
Finished	Jul 25 05:08:37 PM PDT 24
Peak memory	268108 kb
Host	smart-8ad8449f-2236-49d0-aa1f-c92109e97277
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76585862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas h_ctrl_re_evict.76585862
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.3010044140
Short name	T260
Test name
Test status
Simulation time	455069500 ps
CPU time	134.59 seconds
Started	Jul 25 05:08:05 PM PDT 24
Finished	Jul 25 05:10:20 PM PDT 24
Peak memory	291196 kb
Host	smart-ddd9be58-5077-40b7-985d-d5f203e44169
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010044140 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 14.flash_ctrl_ro.3010044140
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.4074360424
Short name	T719
Test name
Test status
Simulation time	9701294000 ps
CPU time	659.6 seconds
Started	Jul 25 05:07:56 PM PDT 24
Finished	Jul 25 05:18:56 PM PDT 24
Peak memory	309668 kb
Host	smart-a327fce3-d67b-4c18-884b-0805cc17d7d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074360424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.flash_ctrl_rw.4074360424
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.1056762031
Short name	T342
Test name
Test status
Simulation time	39355800 ps
CPU time	28.05 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:08:25 PM PDT 24
Peak memory	275284 kb
Host	smart-de9fe91c-0ef3-4468-b6bd-5ebc0f61477e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056762031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.1056762031
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3959265135
Short name	T535
Test name
Test status
Simulation time	66518200 ps
CPU time	29.26 seconds
Started	Jul 25 05:07:56 PM PDT 24
Finished	Jul 25 05:08:26 PM PDT 24
Peak memory	268164 kb
Host	smart-d10682f0-9d81-4fb6-9098-57904ed80b38
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959265135 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3959265135
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.1460545933
Short name	T726
Test name
Test status
Simulation time	10711716100 ps
CPU time	65.3 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:09:03 PM PDT 24
Peak memory	262808 kb
Host	smart-c510280a-f236-4cef-99ca-d1ae6f3b4b74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460545933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1460545933
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.3399031255
Short name	T913
Test name
Test status
Simulation time	123839200 ps
CPU time	100.34 seconds
Started	Jul 25 05:07:50 PM PDT 24
Finished	Jul 25 05:09:30 PM PDT 24
Peak memory	275924 kb
Host	smart-7c265f66-502c-4465-8a1f-67fb46c17649
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399031255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3399031255
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.1730282887
Short name	T258
Test name
Test status
Simulation time	2119009400 ps
CPU time	174.88 seconds
Started	Jul 25 05:07:58 PM PDT 24
Finished	Jul 25 05:10:53 PM PDT 24
Peak memory	264836 kb
Host	smart-03e7c7cc-f2a2-4da9-9d01-ce5499e91a7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730282887 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.1730282887
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.2982952168
Short name	T1015
Test name
Test status
Simulation time	105574500 ps
CPU time	14.02 seconds
Started	Jul 25 05:08:05 PM PDT 24
Finished	Jul 25 05:08:20 PM PDT 24
Peak memory	257920 kb
Host	smart-7033ea3b-3d1a-4e04-9f9e-964e20051b25
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982952168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 2982952168
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.1937159915
Short name	T874
Test name
Test status
Simulation time	15009000 ps
CPU time	13.27 seconds
Started	Jul 25 05:08:05 PM PDT 24
Finished	Jul 25 05:08:18 PM PDT 24
Peak memory	284156 kb
Host	smart-678b39e3-e614-4551-8a49-a105c906c1ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937159915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1937159915
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.4217052301
Short name	T359
Test name
Test status
Simulation time	158917600 ps
CPU time	21.87 seconds
Started	Jul 25 05:08:08 PM PDT 24
Finished	Jul 25 05:08:30 PM PDT 24
Peak memory	273280 kb
Host	smart-874906db-b448-4c56-8fd8-e7cd17e432ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217052301 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.4217052301
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1288825084
Short name	T653
Test name
Test status
Simulation time	10104342400 ps
CPU time	36.44 seconds
Started	Jul 25 05:08:08 PM PDT 24
Finished	Jul 25 05:08:45 PM PDT 24
Peak memory	264692 kb
Host	smart-c9a62806-d2b8-405a-9989-c5067c959ae7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288825084 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1288825084
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.4093053
Short name	T627
Test name
Test status
Simulation time	15903300 ps
CPU time	13.79 seconds
Started	Jul 25 05:08:04 PM PDT 24
Finished	Jul 25 05:08:18 PM PDT 24
Peak memory	264856 kb
Host	smart-24abdcb1-8858-4c0e-a3e7-e600aa184e6a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093053 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.4093053
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2356929546
Short name	T668
Test name
Test status
Simulation time	40120717600 ps
CPU time	823.06 seconds
Started	Jul 25 05:08:05 PM PDT 24
Finished	Jul 25 05:21:48 PM PDT 24
Peak memory	263664 kb
Host	smart-a6354310-c444-4350-80c9-f50fe2b22aee
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356929546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.flash_ctrl_hw_rma_reset.2356929546
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.41822082
Short name	T628
Test name
Test status
Simulation time	6623207000 ps
CPU time	215.58 seconds
Started	Jul 25 05:07:56 PM PDT 24
Finished	Jul 25 05:11:32 PM PDT 24
Peak memory	261908 kb
Host	smart-09064cfd-9331-49f8-bf1e-8a9d502b6e08
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41822082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw _sec_otp.41822082
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.1764433121
Short name	T936
Test name
Test status
Simulation time	1869143700 ps
CPU time	190.96 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:11:09 PM PDT 24
Peak memory	284524 kb
Host	smart-31abae71-b799-4a05-a3da-67ceddeb23f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764433121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.1764433121
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.243018477
Short name	T834
Test name
Test status
Simulation time	44325128800 ps
CPU time	233.45 seconds
Started	Jul 25 05:08:05 PM PDT 24
Finished	Jul 25 05:11:59 PM PDT 24
Peak memory	291060 kb
Host	smart-fa5fc1ae-b747-4a04-ac97-48e03ede9e1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243018477 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.243018477
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2831923644
Short name	T873
Test name
Test status
Simulation time	45398200 ps
CPU time	13.35 seconds
Started	Jul 25 05:08:06 PM PDT 24
Finished	Jul 25 05:08:19 PM PDT 24
Peak memory	259600 kb
Host	smart-a82947d2-304d-4d62-a46d-95347593a692
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831923644 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.2831923644
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.690410228
Short name	T788
Test name
Test status
Simulation time	5113840100 ps
CPU time	144.28 seconds
Started	Jul 25 05:08:00 PM PDT 24
Finished	Jul 25 05:10:25 PM PDT 24
Peak memory	262764 kb
Host	smart-4b53eb1c-cbac-4541-84df-6a0895ad7ded
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690410228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.690410228
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.1337424937
Short name	T744
Test name
Test status
Simulation time	131391700 ps
CPU time	129.97 seconds
Started	Jul 25 05:08:04 PM PDT 24
Finished	Jul 25 05:10:14 PM PDT 24
Peak memory	259976 kb
Host	smart-61ece143-8699-4f6c-a026-3fd3fea91d2e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337424937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o tp_reset.1337424937
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.1907546743
Short name	T903
Test name
Test status
Simulation time	5537873700 ps
CPU time	497.41 seconds
Started	Jul 25 05:08:02 PM PDT 24
Finished	Jul 25 05:16:19 PM PDT 24
Peak memory	263080 kb
Host	smart-df54d658-f847-4228-bbf3-daa4d1e75e0b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1907546743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1907546743
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.713732831
Short name	T696
Test name
Test status
Simulation time	19507600 ps
CPU time	13.57 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:08:20 PM PDT 24
Peak memory	258812 kb
Host	smart-7593cdfe-fc0e-4d8d-8b97-99e50caae097
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713732831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.flash_ctrl_prog_reset.713732831
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.1057808625
Short name	T805
Test name
Test status
Simulation time	163610000 ps
CPU time	916.87 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:23:14 PM PDT 24
Peak memory	284724 kb
Host	smart-33e0700c-0942-428f-a245-3eac5e336220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057808625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1057808625
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.1996519664
Short name	T699
Test name
Test status
Simulation time	66175000 ps
CPU time	34.2 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:08:41 PM PDT 24
Peak memory	276960 kb
Host	smart-10e458af-e8a8-4d2b-9945-e3844425de9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996519664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.1996519664
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.1564658991
Short name	T716
Test name
Test status
Simulation time	605081400 ps
CPU time	144.89 seconds
Started	Jul 25 05:07:58 PM PDT 24
Finished	Jul 25 05:10:24 PM PDT 24
Peak memory	281580 kb
Host	smart-77456b72-0f99-4437-af12-768b3afac8f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564658991 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.flash_ctrl_ro.1564658991
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.3808499492
Short name	T332
Test name
Test status
Simulation time	15325935800 ps
CPU time	601.41 seconds
Started	Jul 25 05:07:57 PM PDT 24
Finished	Jul 25 05:17:58 PM PDT 24
Peak memory	313920 kb
Host	smart-f32b9c91-2446-42c0-9b0c-9eb6eaa36991
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808499492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.3808499492
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.934370697
Short name	T571
Test name
Test status
Simulation time	40927300 ps
CPU time	31.43 seconds
Started	Jul 25 05:08:06 PM PDT 24
Finished	Jul 25 05:08:37 PM PDT 24
Peak memory	268164 kb
Host	smart-77a28193-265c-4ece-a444-27cea1cafebe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934370697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_rw_evict.934370697
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.2532745678
Short name	T525
Test name
Test status
Simulation time	37038500 ps
CPU time	28.13 seconds
Started	Jul 25 05:08:10 PM PDT 24
Finished	Jul 25 05:08:39 PM PDT 24
Peak memory	268164 kb
Host	smart-396bb972-fd8a-4a69-922c-4debf8703313
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532745678 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.2532745678
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.1992254161
Short name	T645
Test name
Test status
Simulation time	379226900 ps
CPU time	58.61 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	263932 kb
Host	smart-68a3310b-77f9-44e8-a010-bdb9e8aed3bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992254161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1992254161
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.4104819512
Short name	T1104
Test name
Test status
Simulation time	63070000 ps
CPU time	127.51 seconds
Started	Jul 25 05:08:04 PM PDT 24
Finished	Jul 25 05:10:12 PM PDT 24
Peak memory	276076 kb
Host	smart-e4524109-9ae6-4e79-a727-d7e6aad67c27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104819512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.4104819512
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.404768014
Short name	T754
Test name
Test status
Simulation time	17804013600 ps
CPU time	186.34 seconds
Started	Jul 25 05:08:00 PM PDT 24
Finished	Jul 25 05:11:07 PM PDT 24
Peak memory	264856 kb
Host	smart-48421117-54e9-4099-a9a1-bcb7c105ee60
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404768014 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 15.flash_ctrl_wo.404768014
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.376120694
Short name	T440
Test name
Test status
Simulation time	63061300 ps
CPU time	13.83 seconds
Started	Jul 25 05:08:13 PM PDT 24
Finished	Jul 25 05:08:27 PM PDT 24
Peak memory	264880 kb
Host	smart-570a11ff-02e8-4568-b7e1-5b53f3555138
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376120694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.376120694
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.1217097428
Short name	T781
Test name
Test status
Simulation time	47797200 ps
CPU time	13.24 seconds
Started	Jul 25 05:08:14 PM PDT 24
Finished	Jul 25 05:08:28 PM PDT 24
Peak memory	284080 kb
Host	smart-f4be99db-7204-4d1a-a7ae-1cf6e857de18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217097428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1217097428
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.3020249885
Short name	T884
Test name
Test status
Simulation time	24453400 ps
CPU time	21.19 seconds
Started	Jul 25 05:08:16 PM PDT 24
Finished	Jul 25 05:08:38 PM PDT 24
Peak memory	273276 kb
Host	smart-1f6dab57-ae77-404d-84a1-fe7aa9b8029b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020249885 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.3020249885
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.396883751
Short name	T610
Test name
Test status
Simulation time	10012706400 ps
CPU time	150.83 seconds
Started	Jul 25 05:08:17 PM PDT 24
Finished	Jul 25 05:10:47 PM PDT 24
Peak memory	397524 kb
Host	smart-850e9365-33be-4ac3-b418-0e47e4677a22
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396883751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.396883751
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.1683226324
Short name	T1051
Test name
Test status
Simulation time	69996600 ps
CPU time	13.67 seconds
Started	Jul 25 05:08:20 PM PDT 24
Finished	Jul 25 05:08:34 PM PDT 24
Peak memory	264832 kb
Host	smart-82fb9cfa-9840-46b5-9166-30a3ed416223
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683226324 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.1683226324
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1022656346
Short name	T704
Test name
Test status
Simulation time	160168887100 ps
CPU time	828.8 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:21:57 PM PDT 24
Peak memory	264260 kb
Host	smart-dd09f0a3-a385-4016-9032-69b5e5abfe7a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022656346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.flash_ctrl_hw_rma_reset.1022656346
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3710579798
Short name	T651
Test name
Test status
Simulation time	6156703300 ps
CPU time	57.39 seconds
Started	Jul 25 05:08:06 PM PDT 24
Finished	Jul 25 05:09:03 PM PDT 24
Peak memory	260484 kb
Host	smart-97e16106-be72-4480-ae1d-3b12505ccbe3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710579798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.3710579798
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.1437140388
Short name	T643
Test name
Test status
Simulation time	1507261800 ps
CPU time	185.1 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:11:13 PM PDT 24
Peak memory	284688 kb
Host	smart-436d7bef-bd2b-4e7a-87ec-bf3d58ba8aab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437140388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_intr_rd.1437140388
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.4113236600
Short name	T674
Test name
Test status
Simulation time	25300303500 ps
CPU time	310.67 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:13:18 PM PDT 24
Peak memory	292784 kb
Host	smart-a28d694e-060c-4e3d-9ccd-99cc33b1ef8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113236600 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.4113236600
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.1416989598
Short name	T600
Test name
Test status
Simulation time	12971016900 ps
CPU time	63.51 seconds
Started	Jul 25 05:08:10 PM PDT 24
Finished	Jul 25 05:09:13 PM PDT 24
Peak memory	260432 kb
Host	smart-2e026e03-c53e-4976-b9e6-2d238130f77c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416989598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.1 416989598
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1358902658
Short name	T960
Test name
Test status
Simulation time	55787700 ps
CPU time	13.17 seconds
Started	Jul 25 05:08:17 PM PDT 24
Finished	Jul 25 05:08:30 PM PDT 24
Peak memory	259568 kb
Host	smart-21ce1413-56e9-4543-a1b1-deb331285069
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358902658 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1358902658
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.1571628648
Short name	T221
Test name
Test status
Simulation time	11272298200 ps
CPU time	150.14 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:10:38 PM PDT 24
Peak memory	263412 kb
Host	smart-7b3fc01a-d7c3-4e19-9beb-abe3a2ebd3a1
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571628648 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1571628648
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.3982049
Short name	T165
Test name
Test status
Simulation time	57462400 ps
CPU time	133.72 seconds
Started	Jul 25 05:08:07 PM PDT 24
Finished	Jul 25 05:10:21 PM PDT 24
Peak memory	264472 kb
Host	smart-488085ee-7bec-468a-a029-c03bbeaf3102
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_ reset.3982049
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.3942697173
Short name	T542
Test name
Test status
Simulation time	2229072600 ps
CPU time	248.72 seconds
Started	Jul 25 05:08:06 PM PDT 24
Finished	Jul 25 05:12:15 PM PDT 24
Peak memory	262884 kb
Host	smart-10edf53a-58e0-4304-9fec-0dbcc8b02f01
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3942697173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3942697173
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.2222976551
Short name	T498
Test name
Test status
Simulation time	39396600 ps
CPU time	13.69 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:08:29 PM PDT 24
Peak memory	258156 kb
Host	smart-c4520829-4d4d-474d-a46b-d8f9a88e810e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222976551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.2222976551
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.235410119
Short name	T81
Test name
Test status
Simulation time	1729705500 ps
CPU time	636.24 seconds
Started	Jul 25 05:08:06 PM PDT 24
Finished	Jul 25 05:18:42 PM PDT 24
Peak memory	285976 kb
Host	smart-588daf5f-a1dd-45e0-9800-5a72dc1d63ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235410119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.235410119
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.1718647328
Short name	T939
Test name
Test status
Simulation time	56657000 ps
CPU time	32.5 seconds
Started	Jul 25 05:08:14 PM PDT 24
Finished	Jul 25 05:08:47 PM PDT 24
Peak memory	275280 kb
Host	smart-a0735860-fa32-41b2-818c-4b49ec9e4369
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718647328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_re_evict.1718647328
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.1372474596
Short name	T883
Test name
Test status
Simulation time	1902488600 ps
CPU time	122.65 seconds
Started	Jul 25 05:08:10 PM PDT 24
Finished	Jul 25 05:10:13 PM PDT 24
Peak memory	291096 kb
Host	smart-9312e6ad-c7ce-4568-99d5-ad32eafb7b01
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372474596 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.1372474596
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.1249223429
Short name	T1086
Test name
Test status
Simulation time	6770911600 ps
CPU time	600.94 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:18:16 PM PDT 24
Peak memory	313492 kb
Host	smart-0e5af818-c651-46d8-8abb-0d10b425e6cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249223429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.flash_ctrl_rw.1249223429
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict.4027718288
Short name	T950
Test name
Test status
Simulation time	93718800 ps
CPU time	31.22 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:08:47 PM PDT 24
Peak memory	267408 kb
Host	smart-200456d8-20ea-48d0-b9c3-25c14f02680e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027718288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_rw_evict.4027718288
Directory	/workspace/16.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.1136537998
Short name	T1014
Test name
Test status
Simulation time	29257000 ps
CPU time	31.43 seconds
Started	Jul 25 05:08:10 PM PDT 24
Finished	Jul 25 05:08:41 PM PDT 24
Peak memory	275332 kb
Host	smart-22b8f4a0-a8bf-49e6-9fa0-48846bc5d85e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136537998 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.1136537998
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.909234490
Short name	T981
Test name
Test status
Simulation time	1334023300 ps
CPU time	64.17 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:09:19 PM PDT 24
Peak memory	262924 kb
Host	smart-f46d2b2d-f88f-4f16-a5a0-54647a9dc1b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909234490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.909234490
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.2403517756
Short name	T865
Test name
Test status
Simulation time	49530600 ps
CPU time	123.07 seconds
Started	Jul 25 05:08:08 PM PDT 24
Finished	Jul 25 05:10:12 PM PDT 24
Peak memory	268376 kb
Host	smart-382839a9-a7f3-41da-be1b-8c386e26da6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403517756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2403517756
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.1587023030
Short name	T694
Test name
Test status
Simulation time	6440914100 ps
CPU time	222.66 seconds
Started	Jul 25 05:08:08 PM PDT 24
Finished	Jul 25 05:11:51 PM PDT 24
Peak memory	259640 kb
Host	smart-3b77a1db-eaf1-47d9-96e7-3528f95a4c16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587023030 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.1587023030
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.4235564586
Short name	T994
Test name
Test status
Simulation time	30187300 ps
CPU time	13.63 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:08:38 PM PDT 24
Peak memory	257904 kb
Host	smart-b69b5924-ef9a-4866-b25c-6d515cbbef0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235564586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 4235564586
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.1345107341
Short name	T658
Test name
Test status
Simulation time	18389200 ps
CPU time	13.78 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:08:38 PM PDT 24
Peak memory	284136 kb
Host	smart-d0ec5714-195b-4230-a3cf-ed98f0690c68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345107341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1345107341
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.3358081487
Short name	T951
Test name
Test status
Simulation time	29520600 ps
CPU time	22.23 seconds
Started	Jul 25 05:08:25 PM PDT 24
Finished	Jul 25 05:08:47 PM PDT 24
Peak memory	273372 kb
Host	smart-65e48f00-0493-4d8c-8165-8abd92860998
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358081487 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.3358081487
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.4086574035
Short name	T526
Test name
Test status
Simulation time	25340700 ps
CPU time	13.58 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:08:37 PM PDT 24
Peak memory	264476 kb
Host	smart-6bcb1201-0ff0-4183-bb40-4a7122b2d25d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086574035 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.4086574035
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1609327357
Short name	T1066
Test name
Test status
Simulation time	40124956500 ps
CPU time	872.78 seconds
Started	Jul 25 05:08:14 PM PDT 24
Finished	Jul 25 05:22:47 PM PDT 24
Peak memory	264044 kb
Host	smart-e0fe93c8-5391-4c71-b438-d04c6b2fb28e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609327357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.1609327357
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4033398470
Short name	T862
Test name
Test status
Simulation time	760212400 ps
CPU time	41.41 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:08:56 PM PDT 24
Peak memory	260428 kb
Host	smart-7b09063f-f7e2-4e53-b0e9-c6541f7abf45
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033398470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.4033398470
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.3359761355
Short name	T683
Test name
Test status
Simulation time	3115023700 ps
CPU time	138.09 seconds
Started	Jul 25 05:08:16 PM PDT 24
Finished	Jul 25 05:10:34 PM PDT 24
Peak memory	292716 kb
Host	smart-7f006d04-09d6-4653-a31f-986495bb8799
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359761355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_intr_rd.3359761355
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1786521324
Short name	T961
Test name
Test status
Simulation time	25364529600 ps
CPU time	269.29 seconds
Started	Jul 25 05:08:17 PM PDT 24
Finished	Jul 25 05:12:46 PM PDT 24
Peak memory	290684 kb
Host	smart-8e5b03e2-ec7a-446c-856e-1f1b33f8da46
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786521324 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.1786521324
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.3477991529
Short name	T579
Test name
Test status
Simulation time	10726692800 ps
CPU time	85.36 seconds
Started	Jul 25 05:08:16 PM PDT 24
Finished	Jul 25 05:09:42 PM PDT 24
Peak memory	260392 kb
Host	smart-e766b653-c884-4f25-a6f8-9e9e8add4b96
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477991529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3 477991529
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.2489633920
Short name	T364
Test name
Test status
Simulation time	13565859400 ps
CPU time	178.87 seconds
Started	Jul 25 05:08:16 PM PDT 24
Finished	Jul 25 05:11:15 PM PDT 24
Peak memory	264940 kb
Host	smart-ae9b3b6e-04fc-4029-9104-239acc1cfae8
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489633920 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.2489633920
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.613217550
Short name	T840
Test name
Test status
Simulation time	145628600 ps
CPU time	131.63 seconds
Started	Jul 25 05:08:13 PM PDT 24
Finished	Jul 25 05:10:25 PM PDT 24
Peak memory	259668 kb
Host	smart-bc07647a-fddc-422f-b2fd-a7858d9164f7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613217550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot p_reset.613217550
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.231014229
Short name	T1084
Test name
Test status
Simulation time	91234500 ps
CPU time	274.87 seconds
Started	Jul 25 05:08:17 PM PDT 24
Finished	Jul 25 05:12:52 PM PDT 24
Peak memory	262936 kb
Host	smart-72fa9817-dec0-448a-9af1-96806976d794
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=231014229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.231014229
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.4035514271
Short name	T187
Test name
Test status
Simulation time	28160100 ps
CPU time	13.67 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:08:29 PM PDT 24
Peak memory	264832 kb
Host	smart-a15a5a5c-4f58-4ae3-bf6b-52eee180310d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035514271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.4035514271
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.415576805
Short name	T558
Test name
Test status
Simulation time	27440000 ps
CPU time	56.9 seconds
Started	Jul 25 05:08:15 PM PDT 24
Finished	Jul 25 05:09:12 PM PDT 24
Peak memory	271000 kb
Host	smart-5dff2a63-b9cf-4055-b931-1995fc6203da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415576805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.415576805
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.600551643
Short name	T773
Test name
Test status
Simulation time	689428800 ps
CPU time	35.64 seconds
Started	Jul 25 05:08:22 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	276316 kb
Host	smart-d20c746c-e416-4c48-b0c6-743746681aa8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600551643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_re_evict.600551643
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.1169233984
Short name	T39
Test name
Test status
Simulation time	2141822800 ps
CPU time	104.63 seconds
Started	Jul 25 05:08:17 PM PDT 24
Finished	Jul 25 05:10:02 PM PDT 24
Peak memory	280820 kb
Host	smart-455e5b48-aec3-4216-b871-f6ee25db6a22
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169233984 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.flash_ctrl_ro.1169233984
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.1228361909
Short name	T590
Test name
Test status
Simulation time	6458303500 ps
CPU time	698.83 seconds
Started	Jul 25 05:08:14 PM PDT 24
Finished	Jul 25 05:19:53 PM PDT 24
Peak memory	310020 kb
Host	smart-f8bd6ae4-79f7-4b03-b827-6e5732ce1b47
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228361909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.flash_ctrl_rw.1228361909
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.383419976
Short name	T340
Test name
Test status
Simulation time	27930500 ps
CPU time	28.77 seconds
Started	Jul 25 05:08:51 PM PDT 24
Finished	Jul 25 05:09:20 PM PDT 24
Peak memory	268156 kb
Host	smart-f92f69fb-bffb-4e81-bc1a-da326b4a6d18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383419976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_rw_evict.383419976
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.953627456
Short name	T545
Test name
Test status
Simulation time	31176200 ps
CPU time	30.81 seconds
Started	Jul 25 05:08:25 PM PDT 24
Finished	Jul 25 05:08:56 PM PDT 24
Peak memory	273204 kb
Host	smart-ca5ab3e7-0db8-4fa8-9eb8-1e7c3a805a10
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953627456 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.953627456
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.3089994073
Short name	T488
Test name
Test status
Simulation time	42928000 ps
CPU time	76.31 seconds
Started	Jul 25 05:08:16 PM PDT 24
Finished	Jul 25 05:09:33 PM PDT 24
Peak memory	275364 kb
Host	smart-bca4feba-2f77-4e6c-968a-5c3d863fb111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089994073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3089994073
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.987460600
Short name	T819
Test name
Test status
Simulation time	3791486300 ps
CPU time	172.37 seconds
Started	Jul 25 05:08:13 PM PDT 24
Finished	Jul 25 05:11:06 PM PDT 24
Peak memory	259028 kb
Host	smart-0d524ca5-c00d-4463-9a06-0469363339cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987460600 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 17.flash_ctrl_wo.987460600
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.1309916857
Short name	T711
Test name
Test status
Simulation time	24534100 ps
CPU time	13.58 seconds
Started	Jul 25 05:08:35 PM PDT 24
Finished	Jul 25 05:08:48 PM PDT 24
Peak memory	257844 kb
Host	smart-f34a13a7-ea74-478a-a851-511e467f9789
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309916857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 1309916857
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.2937298961
Short name	T1053
Test name
Test status
Simulation time	17220500 ps
CPU time	13.26 seconds
Started	Jul 25 05:08:37 PM PDT 24
Finished	Jul 25 05:08:50 PM PDT 24
Peak memory	284124 kb
Host	smart-89340b18-7c73-446c-bf92-0aaee87e993e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937298961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2937298961
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.2736835356
Short name	T41
Test name
Test status
Simulation time	49319000 ps
CPU time	22.38 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:08:46 PM PDT 24
Peak memory	273272 kb
Host	smart-7f6e33be-5de6-40e8-8544-6a55d49ba87a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736835356 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.2736835356
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.739189298
Short name	T872
Test name
Test status
Simulation time	10033104500 ps
CPU time	54.8 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:09:28 PM PDT 24
Peak memory	282220 kb
Host	smart-fc950878-7fa3-4778-b91c-58b9f55fc8c5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739189298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.739189298
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.996284665
Short name	T774
Test name
Test status
Simulation time	80137642200 ps
CPU time	854.3 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:22:38 PM PDT 24
Peak memory	260528 kb
Host	smart-7cc59719-2397-4ec5-9339-243a931b5815
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996284665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.flash_ctrl_hw_rma_reset.996284665
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.3978384381
Short name	T107
Test name
Test status
Simulation time	5868073700 ps
CPU time	265.54 seconds
Started	Jul 25 05:08:27 PM PDT 24
Finished	Jul 25 05:12:53 PM PDT 24
Peak memory	260708 kb
Host	smart-2f53010b-8291-4411-9c51-809e5d04d720
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978384381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ hw_sec_otp.3978384381
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.692962826
Short name	T1018
Test name
Test status
Simulation time	1274203100 ps
CPU time	207.1 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:11:51 PM PDT 24
Peak memory	293676 kb
Host	smart-021b6d7f-3f90-4978-8db6-2aaab76be0cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692962826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas h_ctrl_intr_rd.692962826
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1389058103
Short name	T835
Test name
Test status
Simulation time	12335576000 ps
CPU time	299.34 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:13:23 PM PDT 24
Peak memory	292692 kb
Host	smart-5cd01d94-2af2-4c11-a151-e9b6144cdbbf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389058103 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1389058103
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.4202738568
Short name	T1071
Test name
Test status
Simulation time	3247062300 ps
CPU time	68.35 seconds
Started	Jul 25 05:08:22 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	263432 kb
Host	smart-c26199a9-149c-4c21-aa12-e260cd3ace90
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202738568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.4 202738568
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.342767033
Short name	T941
Test name
Test status
Simulation time	207843700 ps
CPU time	13.53 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:08:46 PM PDT 24
Peak memory	260348 kb
Host	smart-a84aa755-4c81-4395-b55e-099c58f3ef66
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342767033 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.342767033
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.3366343770
Short name	T134
Test name
Test status
Simulation time	97968449900 ps
CPU time	302.41 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:13:27 PM PDT 24
Peak memory	274636 kb
Host	smart-66f99f12-1430-4d26-b55c-a16ee18285c5
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366343770 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.3366343770
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.260662430
Short name	T734
Test name
Test status
Simulation time	73390400 ps
CPU time	132.56 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:10:36 PM PDT 24
Peak memory	260040 kb
Host	smart-fb7421e1-d57a-4810-aa28-06e10915bb60
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260662430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ot p_reset.260662430
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.1649343096
Short name	T26
Test name
Test status
Simulation time	331650100 ps
CPU time	141.88 seconds
Started	Jul 25 05:08:26 PM PDT 24
Finished	Jul 25 05:10:48 PM PDT 24
Peak memory	262912 kb
Host	smart-e18d8424-34fe-4d74-a6a1-69c7ec1121c9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1649343096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1649343096
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.3359345679
Short name	T302
Test name
Test status
Simulation time	63687500 ps
CPU time	13.83 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:08:38 PM PDT 24
Peak memory	258776 kb
Host	smart-2c1fb84e-d350-4789-adc2-9f463b7f0b06
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359345679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.flash_ctrl_prog_reset.3359345679
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.3783686402
Short name	T20
Test name
Test status
Simulation time	146656000 ps
CPU time	549.9 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:17:34 PM PDT 24
Peak memory	282464 kb
Host	smart-f79fec8b-cdda-4581-991d-0057e19edba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783686402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3783686402
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.1104381430
Short name	T331
Test name
Test status
Simulation time	130472500 ps
CPU time	33.39 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	278412 kb
Host	smart-9f2aafe8-11af-4d0b-8155-5f3337ffea46
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104381430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.1104381430
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.1681523200
Short name	T848
Test name
Test status
Simulation time	476477500 ps
CPU time	101.52 seconds
Started	Jul 25 05:08:25 PM PDT 24
Finished	Jul 25 05:10:07 PM PDT 24
Peak memory	280864 kb
Host	smart-7a730df2-fda5-4fc4-98c2-c43b865c94e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681523200 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.1681523200
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.3636861067
Short name	T375
Test name
Test status
Simulation time	8098195200 ps
CPU time	637.59 seconds
Started	Jul 25 05:08:27 PM PDT 24
Finished	Jul 25 05:19:05 PM PDT 24
Peak memory	314096 kb
Host	smart-48c8219d-9f4b-4889-9060-b5fbfbde8bfe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636861067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.3636861067
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.4020719504
Short name	T702
Test name
Test status
Simulation time	48307000 ps
CPU time	31.27 seconds
Started	Jul 25 05:08:25 PM PDT 24
Finished	Jul 25 05:08:57 PM PDT 24
Peak memory	268044 kb
Host	smart-d5f81f50-a6b3-4231-88c0-0113f4a99e02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020719504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.4020719504
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.1363799971
Short name	T937
Test name
Test status
Simulation time	27327400 ps
CPU time	30.63 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:08:54 PM PDT 24
Peak memory	273300 kb
Host	smart-fa994de5-1809-4640-b55e-5722816a0df2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363799971 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.1363799971
Directory	/workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.2046749271
Short name	T406
Test name
Test status
Simulation time	3430867500 ps
CPU time	58.72 seconds
Started	Jul 25 05:08:32 PM PDT 24
Finished	Jul 25 05:09:30 PM PDT 24
Peak memory	262848 kb
Host	smart-92043aca-ee97-4f43-b45e-e88003ecc43e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046749271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2046749271
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.1672143762
Short name	T577
Test name
Test status
Simulation time	45811000 ps
CPU time	99.25 seconds
Started	Jul 25 05:08:24 PM PDT 24
Finished	Jul 25 05:10:04 PM PDT 24
Peak memory	276020 kb
Host	smart-38d9bf16-a74f-4ac1-b933-d798b30395ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672143762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1672143762
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.1756182138
Short name	T857
Test name
Test status
Simulation time	8827021700 ps
CPU time	177.41 seconds
Started	Jul 25 05:08:23 PM PDT 24
Finished	Jul 25 05:11:21 PM PDT 24
Peak memory	259608 kb
Host	smart-801c9d96-9db3-45e5-8db3-ffb646e6c5f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756182138 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.flash_ctrl_wo.1756182138
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.2424073544
Short name	T417
Test name
Test status
Simulation time	96805100 ps
CPU time	13.52 seconds
Started	Jul 25 05:08:37 PM PDT 24
Finished	Jul 25 05:08:51 PM PDT 24
Peak memory	257972 kb
Host	smart-056354ad-6758-41ea-847b-47cac95028ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424073544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 2424073544
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.1353320081
Short name	T791
Test name
Test status
Simulation time	15720500 ps
CPU time	15.62 seconds
Started	Jul 25 05:08:39 PM PDT 24
Finished	Jul 25 05:08:55 PM PDT 24
Peak memory	284156 kb
Host	smart-5f10a176-256f-4d59-a445-f158496ebc1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353320081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1353320081
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.2656741442
Short name	T132
Test name
Test status
Simulation time	12980200 ps
CPU time	22.33 seconds
Started	Jul 25 05:08:36 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	273212 kb
Host	smart-52513bd2-eda2-49db-ab3d-07bf100a95df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656741442 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.2656741442
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3673904699
Short name	T75
Test name
Test status
Simulation time	26517000 ps
CPU time	13.28 seconds
Started	Jul 25 05:08:39 PM PDT 24
Finished	Jul 25 05:08:53 PM PDT 24
Peak memory	258768 kb
Host	smart-500f5086-693a-41a4-a996-16145eab0fd4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673904699 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3673904699
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1050502316
Short name	T1063
Test name
Test status
Simulation time	3518965200 ps
CPU time	109.53 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:10:23 PM PDT 24
Peak memory	260576 kb
Host	smart-cda29362-734c-469d-bd2f-fc5dd90b1ce8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050502316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.1050502316
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.1970319880
Short name	T547
Test name
Test status
Simulation time	3036563800 ps
CPU time	133.56 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:10:47 PM PDT 24
Peak memory	293872 kb
Host	smart-5123c1b2-59a9-4829-8c86-f31b3aa47f9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970319880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.1970319880
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2501904018
Short name	T930
Test name
Test status
Simulation time	83285704100 ps
CPU time	249.62 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:12:42 PM PDT 24
Peak memory	291128 kb
Host	smart-fc277d4f-8233-4a99-8bc7-0e23b8a758e3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501904018 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.2501904018
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.3810197015
Short name	T636
Test name
Test status
Simulation time	12518621900 ps
CPU time	82.83 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:09:57 PM PDT 24
Peak memory	263188 kb
Host	smart-deb349fc-67f3-4e17-b74c-7f051cd14bf1
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810197015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3 810197015
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.11068136
Short name	T1017
Test name
Test status
Simulation time	15040800 ps
CPU time	13.5 seconds
Started	Jul 25 05:08:36 PM PDT 24
Finished	Jul 25 05:08:49 PM PDT 24
Peak memory	259600 kb
Host	smart-b843a469-0882-4331-9c1e-8e4c158eee02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068136 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.11068136
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.1182214609
Short name	T1062
Test name
Test status
Simulation time	64792024400 ps
CPU time	534.97 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:17:28 PM PDT 24
Peak memory	273956 kb
Host	smart-f7f26680-b4fe-482d-95d7-3122cecaa0c2
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182214609 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1182214609
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.767829516
Short name	T465
Test name
Test status
Simulation time	845451500 ps
CPU time	77.57 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:09:52 PM PDT 24
Peak memory	264900 kb
Host	smart-b99f79fd-eb54-414e-b5df-22bfab3b03df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767829516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.flash_ctrl_prog_reset.767829516
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.2962028016
Short name	T1038
Test name
Test status
Simulation time	145410900 ps
CPU time	551.42 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:17:45 PM PDT 24
Peak memory	283084 kb
Host	smart-4927e715-f49d-4e42-89b1-182ad35987ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962028016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2962028016
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.1280702775
Short name	T261
Test name
Test status
Simulation time	391913000 ps
CPU time	33.86 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:09:08 PM PDT 24
Peak memory	275336 kb
Host	smart-22b4a581-ce15-4ff4-ad15-3b5f427043ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280702775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_re_evict.1280702775
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.1600257364
Short name	T1037
Test name
Test status
Simulation time	1980904800 ps
CPU time	112.5 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:10:27 PM PDT 24
Peak memory	281400 kb
Host	smart-a0c1e873-df82-4f95-92c7-188e1b08cb1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600257364 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_ro.1600257364
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.1865758176
Short name	T490
Test name
Test status
Simulation time	13951007200 ps
CPU time	579.74 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:18:14 PM PDT 24
Peak memory	309472 kb
Host	smart-447d39f4-2e01-4fb9-b956-b520e1a093b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865758176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.flash_ctrl_rw.1865758176
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.85812883
Short name	T778
Test name
Test status
Simulation time	31516400 ps
CPU time	31.26 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	275292 kb
Host	smart-886fe859-5485-4bac-91e3-458ad8e75358
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85812883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas h_ctrl_rw_evict.85812883
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1275574000
Short name	T597
Test name
Test status
Simulation time	44091200 ps
CPU time	30.99 seconds
Started	Jul 25 05:08:35 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	275332 kb
Host	smart-e1ebdb98-3c8a-490f-addc-8a30b478130d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275574000 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1275574000
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.1691377312
Short name	T397
Test name
Test status
Simulation time	1630177000 ps
CPU time	56.65 seconds
Started	Jul 25 05:08:36 PM PDT 24
Finished	Jul 25 05:09:33 PM PDT 24
Peak memory	264824 kb
Host	smart-5e6d5c3c-79cc-4345-9e1c-8f636ba37078
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1691377312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1691377312
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.1522492221
Short name	T1108
Test name
Test status
Simulation time	68160500 ps
CPU time	121.43 seconds
Started	Jul 25 05:08:36 PM PDT 24
Finished	Jul 25 05:10:37 PM PDT 24
Peak memory	277044 kb
Host	smart-f3771ca0-d4c5-4283-a122-d470c86f1238
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522492221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1522492221
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.1252748254
Short name	T767
Test name
Test status
Simulation time	3238297400 ps
CPU time	271.79 seconds
Started	Jul 25 05:08:34 PM PDT 24
Finished	Jul 25 05:13:06 PM PDT 24
Peak memory	264948 kb
Host	smart-898c84ba-e305-41d1-9940-bd86488f9318
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252748254 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.1252748254
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.1443894084
Short name	T370
Test name
Test status
Simulation time	21701300 ps
CPU time	13.85 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:06:45 PM PDT 24
Peak memory	257976 kb
Host	smart-7f10e3d2-5bc8-41ad-b9b9-7491cc386339
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443894084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1 443894084
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.4212765345
Short name	T717
Test name
Test status
Simulation time	21999700 ps
CPU time	14.02 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	264604 kb
Host	smart-1734e72f-1320-4888-afca-dfe6c192d195
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212765345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.4212765345
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.2915539494
Short name	T617
Test name
Test status
Simulation time	16880200 ps
CPU time	15.7 seconds
Started	Jul 25 05:06:13 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	282776 kb
Host	smart-a758a7f9-055d-465c-9e52-7ad8a3863e09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915539494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2915539494
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.2892710586
Short name	T122
Test name
Test status
Simulation time	10982800 ps
CPU time	22.45 seconds
Started	Jul 25 05:06:19 PM PDT 24
Finished	Jul 25 05:06:41 PM PDT 24
Peak memory	273348 kb
Host	smart-55db89ee-2223-42d9-bcbd-485223fb9a0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892710586 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.2892710586
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.337862701
Short name	T71
Test name
Test status
Simulation time	13931625500 ps
CPU time	554.93 seconds
Started	Jul 25 05:06:04 PM PDT 24
Finished	Jul 25 05:15:19 PM PDT 24
Peak memory	263188 kb
Host	smart-d37a8a69-75be-4401-862a-34b0ac45600f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=337862701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.337862701
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.564460119
Short name	T927
Test name
Test status
Simulation time	676950600 ps
CPU time	1742.74 seconds
Started	Jul 25 05:06:10 PM PDT 24
Finished	Jul 25 05:35:13 PM PDT 24
Peak memory	264240 kb
Host	smart-857975cb-9bd2-459e-bc47-7dba4bb763ad
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564460119 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_error_prog_type.564460119
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.1988411094
Short name	T823
Test name
Test status
Simulation time	1488069800 ps
CPU time	957.53 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:22:04 PM PDT 24
Peak memory	270208 kb
Host	smart-71a425af-46ef-482e-9b3a-c14f35026e2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988411094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1988411094
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.3222645220
Short name	T43
Test name
Test status
Simulation time	775715600 ps
CPU time	25.7 seconds
Started	Jul 25 05:06:09 PM PDT 24
Finished	Jul 25 05:06:35 PM PDT 24
Peak memory	262216 kb
Host	smart-32ad1fd3-d70c-4a17-a50a-700675150e5c
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222645220 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3222645220
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.336935219
Short name	T130
Test name
Test status
Simulation time	89932330200 ps
CPU time	2304.28 seconds
Started	Jul 25 05:06:11 PM PDT 24
Finished	Jul 25 05:44:35 PM PDT 24
Peak memory	261540 kb
Host	smart-403df910-e9a3-4695-ae99-537297390746
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336935219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_full_mem_access.336935219
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.2158820181
Short name	T566
Test name
Test status
Simulation time	27161900 ps
CPU time	27.91 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:06:52 PM PDT 24
Peak memory	268180 kb
Host	smart-cf04981f-af1a-4a88-95f8-e7ba728d1639
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158820181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_host_addr_infection.2158820181
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3303595508
Short name	T483
Test name
Test status
Simulation time	2021401973900 ps
CPU time	1899.27 seconds
Started	Jul 25 05:06:10 PM PDT 24
Finished	Jul 25 05:37:49 PM PDT 24
Peak memory	265052 kb
Host	smart-acb741e0-5062-4c0a-9d49-26d72ac388f1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303595508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.3303595508
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.3406701568
Short name	T830
Test name
Test status
Simulation time	61611400 ps
CPU time	114.64 seconds
Started	Jul 25 05:06:07 PM PDT 24
Finished	Jul 25 05:08:02 PM PDT 24
Peak memory	264960 kb
Host	smart-e34eb952-d024-4201-832f-c0d106bc0af0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3406701568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3406701568
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2562258417
Short name	T271
Test name
Test status
Simulation time	10011735800 ps
CPU time	115.32 seconds
Started	Jul 25 05:06:22 PM PDT 24
Finished	Jul 25 05:08:17 PM PDT 24
Peak memory	331912 kb
Host	smart-17fefbff-a8fc-4694-99d3-a42a167678bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562258417 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2562258417
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1201045329
Short name	T816
Test name
Test status
Simulation time	180437700 ps
CPU time	13.79 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	259792 kb
Host	smart-9ffbdbe8-afd2-4442-8990-cb759c4a1434
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201045329 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1201045329
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.680470704
Short name	T91
Test name
Test status
Simulation time	140748943400 ps
CPU time	2343.56 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:45:10 PM PDT 24
Peak memory	264904 kb
Host	smart-6ee45be5-920d-46f1-be98-7afb87b68863
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680470704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_hw_rma.680470704
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.1303230060
Short name	T74
Test name
Test status
Simulation time	50123828900 ps
CPU time	803.25 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:19:29 PM PDT 24
Peak memory	264256 kb
Host	smart-74192b6c-79c2-4f58-bd47-eee41af69ae7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303230060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_hw_rma_reset.1303230060
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1301211879
Short name	T422
Test name
Test status
Simulation time	24460802500 ps
CPU time	177.22 seconds
Started	Jul 25 05:06:08 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	262780 kb
Host	smart-d25d653a-4213-4c31-82f8-8eea3b04fc8d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301211879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.1301211879
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.3374981092
Short name	T236
Test name
Test status
Simulation time	8424873300 ps
CPU time	738.23 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:18:33 PM PDT 24
Peak memory	335500 kb
Host	smart-8761169c-e497-4625-934c-dade11e78d57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374981092 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.3374981092
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.2490702224
Short name	T691
Test name
Test status
Simulation time	5408359800 ps
CPU time	125.89 seconds
Started	Jul 25 05:06:16 PM PDT 24
Finished	Jul 25 05:08:22 PM PDT 24
Peak memory	293728 kb
Host	smart-4e125581-f8d6-4f69-b41a-f6a5315130b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490702224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_intr_rd.2490702224
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.4250704598
Short name	T99
Test name
Test status
Simulation time	72291022100 ps
CPU time	289.05 seconds
Started	Jul 25 05:06:13 PM PDT 24
Finished	Jul 25 05:11:03 PM PDT 24
Peak memory	292708 kb
Host	smart-3fc30ed7-9506-48e1-8650-46919c9052bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250704598 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.4250704598
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.4240316429
Short name	T713
Test name
Test status
Simulation time	13970792800 ps
CPU time	79.94 seconds
Started	Jul 25 05:06:16 PM PDT 24
Finished	Jul 25 05:07:36 PM PDT 24
Peak memory	260352 kb
Host	smart-173b6b82-c10d-43bf-a604-2748fd62ef6d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240316429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.4240316429
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1193869968
Short name	T491
Test name
Test status
Simulation time	92023415900 ps
CPU time	277.74 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	260052 kb
Host	smart-5dded778-a459-4c39-be72-08e476d7cced
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119 3869968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1193869968
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.1580795134
Short name	T213
Test name
Test status
Simulation time	1934129900 ps
CPU time	88.97 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:07:35 PM PDT 24
Peak memory	260352 kb
Host	smart-0c131c9e-49de-4665-a9b0-c222dc2a18e2
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580795134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1580795134
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1098762549
Short name	T580
Test name
Test status
Simulation time	25935200 ps
CPU time	13.53 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:06:27 PM PDT 24
Peak memory	259460 kb
Host	smart-262acd7b-2703-477d-8438-6a3f2535b169
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098762549 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1098762549
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.1690024159
Short name	T146
Test name
Test status
Simulation time	22903925200 ps
CPU time	269.65 seconds
Started	Jul 25 05:06:08 PM PDT 24
Finished	Jul 25 05:10:37 PM PDT 24
Peak memory	273756 kb
Host	smart-e4dc68e2-95b8-4ee2-84f1-6e9588c73005
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690024159 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.1690024159
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.1439208023
Short name	T494
Test name
Test status
Simulation time	71658200 ps
CPU time	132.01 seconds
Started	Jul 25 05:06:07 PM PDT 24
Finished	Jul 25 05:08:19 PM PDT 24
Peak memory	259868 kb
Host	smart-da9080b9-383b-4ef7-ba8f-3a668776b541
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439208023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot p_reset.1439208023
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.13960636
Short name	T40
Test name
Test status
Simulation time	1121456500 ps
CPU time	184.22 seconds
Started	Jul 25 05:06:18 PM PDT 24
Finished	Jul 25 05:09:22 PM PDT 24
Peak memory	281452 kb
Host	smart-3fa9cdbd-e010-451f-ac1f-28f59f794b65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13960636 -assert nopo stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.13960636
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.1139784682
Short name	T990
Test name
Test status
Simulation time	2841693300 ps
CPU time	339.47 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:11:45 PM PDT 24
Peak memory	262816 kb
Host	smart-777e5c87-6cea-4555-b425-89f938614d3b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1139784682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1139784682
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1370579394
Short name	T191
Test name
Test status
Simulation time	49878600 ps
CPU time	13.69 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	262464 kb
Host	smart-169f5914-15fc-44de-9036-4808b9775688
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370579394 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1370579394
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.3085497823
Short name	T928
Test name
Test status
Simulation time	20462800 ps
CPU time	13.47 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:06:27 PM PDT 24
Peak memory	264916 kb
Host	smart-ccd36e06-29f8-4289-b1e7-0b864f702442
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085497823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_prog_reset.3085497823
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.3476357609
Short name	T157
Test name
Test status
Simulation time	92456600 ps
CPU time	306.1 seconds
Started	Jul 25 05:06:05 PM PDT 24
Finished	Jul 25 05:11:11 PM PDT 24
Peak memory	277484 kb
Host	smart-0e1eb7d3-454a-4faa-a28e-26209f331cca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476357609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3476357609
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.301233894
Short name	T680
Test name
Test status
Simulation time	756013200 ps
CPU time	116.73 seconds
Started	Jul 25 05:06:08 PM PDT 24
Finished	Jul 25 05:08:05 PM PDT 24
Peak memory	262404 kb
Host	smart-ba63d66a-7c7b-44ab-b034-832f21e93049
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=301233894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.301233894
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.2146471751
Short name	T263
Test name
Test status
Simulation time	200447100 ps
CPU time	29.85 seconds
Started	Jul 25 05:06:16 PM PDT 24
Finished	Jul 25 05:06:46 PM PDT 24
Peak memory	268092 kb
Host	smart-bf170071-5327-498b-a12b-204562709ec5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146471751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.2146471751
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2607474371
Short name	T669
Test name
Test status
Simulation time	208659500 ps
CPU time	23.18 seconds
Started	Jul 25 05:06:19 PM PDT 24
Finished	Jul 25 05:06:42 PM PDT 24
Peak memory	264624 kb
Host	smart-097b8ece-4dca-44d4-9465-655f80abf2c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607474371 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2607474371
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2696212082
Short name	T374
Test name
Test status
Simulation time	24952200 ps
CPU time	21.52 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:06:37 PM PDT 24
Peak memory	265032 kb
Host	smart-0f42d58d-5fa6-4cf4-bbdb-88eb5a1f3044
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696212082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.2696212082
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.1886759438
Short name	T1052
Test name
Test status
Simulation time	2397369600 ps
CPU time	120.32 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:08:07 PM PDT 24
Peak memory	281552 kb
Host	smart-fb1a9ca5-2f19-42ca-aaec-db65dff3ffa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886759438 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_ro.1886759438
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.2849490914
Short name	T237
Test name
Test status
Simulation time	973707200 ps
CPU time	111.17 seconds
Started	Jul 25 05:06:17 PM PDT 24
Finished	Jul 25 05:08:08 PM PDT 24
Peak memory	281436 kb
Host	smart-3877583d-ca17-4433-af7b-987cab434735
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2849490914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2849490914
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.3769114721
Short name	T423
Test name
Test status
Simulation time	4017836300 ps
CPU time	134.34 seconds
Started	Jul 25 05:06:16 PM PDT 24
Finished	Jul 25 05:08:31 PM PDT 24
Peak memory	290028 kb
Host	smart-01f35b69-e936-4e02-9260-30978566cb50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769114721 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3769114721
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.1673336030
Short name	T672
Test name
Test status
Simulation time	77737200 ps
CPU time	30.42 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:06:46 PM PDT 24
Peak memory	275388 kb
Host	smart-732bcfe7-ff2a-42a0-9b2c-3b116b1be2f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673336030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_rw_evict.1673336030
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.3875329372
Short name	T942
Test name
Test status
Simulation time	40613800 ps
CPU time	31.37 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:06:46 PM PDT 24
Peak memory	273204 kb
Host	smart-a73ff8fd-0c38-48b5-a922-6c5db63141bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875329372 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.3875329372
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.441484975
Short name	T120
Test name
Test status
Simulation time	1492668500 ps
CPU time	4742.26 seconds
Started	Jul 25 05:06:19 PM PDT 24
Finished	Jul 25 06:25:22 PM PDT 24
Peak memory	285888 kb
Host	smart-da6a1027-87ec-4a9c-947f-1d2231f327b8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441484975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.441484975
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.2221018803
Short name	T416
Test name
Test status
Simulation time	9864660400 ps
CPU time	81.82 seconds
Started	Jul 25 05:06:17 PM PDT 24
Finished	Jul 25 05:07:39 PM PDT 24
Peak memory	262908 kb
Host	smart-0439c1ef-e316-4cc9-959a-9c008b100eea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221018803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2221018803
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.449494426
Short name	T1011
Test name
Test status
Simulation time	708137600 ps
CPU time	74.93 seconds
Started	Jul 25 05:06:15 PM PDT 24
Finished	Jul 25 05:07:30 PM PDT 24
Peak memory	265076 kb
Host	smart-af1a1360-817d-4933-ab1e-3785cfbf5895
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449494426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr_address.449494426
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.114481075
Short name	T943
Test name
Test status
Simulation time	2180133900 ps
CPU time	66.16 seconds
Started	Jul 25 05:06:13 PM PDT 24
Finished	Jul 25 05:07:20 PM PDT 24
Peak memory	273300 kb
Host	smart-d6594dd8-8296-4dab-ae4b-50a21842cc73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114481075 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_counter.114481075
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.3204375775
Short name	T521
Test name
Test status
Simulation time	24242600 ps
CPU time	74.35 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	276284 kb
Host	smart-eba16efd-d95a-4c21-ae19-a994eda538d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204375775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3204375775
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.138846941
Short name	T881
Test name
Test status
Simulation time	44018000 ps
CPU time	23.59 seconds
Started	Jul 25 05:06:06 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	259436 kb
Host	smart-e2c342ee-7ce4-46ab-82f4-40e07a5e11bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138846941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.138846941
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.2204409793
Short name	T1096
Test name
Test status
Simulation time	9251198800 ps
CPU time	1021.94 seconds
Started	Jul 25 05:06:16 PM PDT 24
Finished	Jul 25 05:23:18 PM PDT 24
Peak memory	287900 kb
Host	smart-c7957cbe-11c5-4369-b0aa-0b7d21956932
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204409793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.2204409793
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.2624274371
Short name	T695
Test name
Test status
Simulation time	124542200 ps
CPU time	26.71 seconds
Started	Jul 25 05:06:08 PM PDT 24
Finished	Jul 25 05:06:34 PM PDT 24
Peak memory	259400 kb
Host	smart-320d723c-b1c4-419f-98de-92e156c6eac8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624274371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2624274371
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.1482736931
Short name	T915
Test name
Test status
Simulation time	1987061200 ps
CPU time	163.11 seconds
Started	Jul 25 05:06:08 PM PDT 24
Finished	Jul 25 05:08:51 PM PDT 24
Peak memory	258992 kb
Host	smart-6e1ffdb0-5f31-494e-a9de-a4065e17c340
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482736931 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_wo.1482736931
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.2900263504
Short name	T22
Test name
Test status
Simulation time	152602300 ps
CPU time	15.06 seconds
Started	Jul 25 05:06:14 PM PDT 24
Finished	Jul 25 05:06:29 PM PDT 24
Peak memory	260492 kb
Host	smart-58a30dde-8212-4994-9742-7383f93a52cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900263504 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2900263504
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.542268387
Short name	T646
Test name
Test status
Simulation time	198788900 ps
CPU time	13.52 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:08:57 PM PDT 24
Peak memory	257888 kb
Host	smart-7e4104f8-62b1-4141-8181-ae31a4eb6b74
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542268387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.542268387
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.1044551505
Short name	T451
Test name
Test status
Simulation time	78392300 ps
CPU time	15.73 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:09:00 PM PDT 24
Peak memory	282812 kb
Host	smart-83e37c0a-7eb9-410c-af19-432a67bcbee6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044551505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1044551505
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.1468657320
Short name	T183
Test name
Test status
Simulation time	27443700 ps
CPU time	20.64 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:09:05 PM PDT 24
Peak memory	273368 kb
Host	smart-5c257693-7181-4a7f-adac-5d3b1e79568a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468657320 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.1468657320
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2204825547
Short name	T428
Test name
Test status
Simulation time	4549371300 ps
CPU time	84.81 seconds
Started	Jul 25 05:08:35 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	262252 kb
Host	smart-2f06df5b-06c0-4302-969b-7f0873f1900c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204825547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.2204825547
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.2031410500
Short name	T714
Test name
Test status
Simulation time	4527932100 ps
CPU time	120.21 seconds
Started	Jul 25 05:08:33 PM PDT 24
Finished	Jul 25 05:10:33 PM PDT 24
Peak memory	284376 kb
Host	smart-7518b0c6-b5d6-45b9-a139-305816d9f2ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031410500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.2031410500
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3940175975
Short name	T1033
Test name
Test status
Simulation time	12143762500 ps
CPU time	265.29 seconds
Started	Jul 25 05:08:45 PM PDT 24
Finished	Jul 25 05:13:10 PM PDT 24
Peak memory	290872 kb
Host	smart-b551e7f7-3fe6-4cc8-856c-7b0df8bd2a74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940175975 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3940175975
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.3765075291
Short name	T499
Test name
Test status
Simulation time	42181100 ps
CPU time	130.29 seconds
Started	Jul 25 05:08:36 PM PDT 24
Finished	Jul 25 05:10:47 PM PDT 24
Peak memory	260160 kb
Host	smart-5cf3749b-d22c-40bf-9d3e-5cbddfdadb8c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765075291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o tp_reset.3765075291
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.3642851564
Short name	T532
Test name
Test status
Simulation time	564666600 ps
CPU time	46.61 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:09:29 PM PDT 24
Peak memory	260032 kb
Host	smart-0b28b164-e63a-4acf-abb7-5a3e64442493
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642851564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.flash_ctrl_prog_reset.3642851564
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict.4274181111
Short name	T650
Test name
Test status
Simulation time	39858600 ps
CPU time	29.62 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:09:13 PM PDT 24
Peak memory	268108 kb
Host	smart-af3b921a-6d79-4b89-932f-a3ca000b2a6b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274181111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl ash_ctrl_rw_evict.4274181111
Directory	/workspace/20.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.387657161
Short name	T731
Test name
Test status
Simulation time	45784400 ps
CPU time	31.14 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:09:15 PM PDT 24
Peak memory	268184 kb
Host	smart-4d7e6dd6-2b18-43c9-aeb5-b53df58461c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387657161 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.387657161
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.364233673
Short name	T404
Test name
Test status
Simulation time	2288783700 ps
CPU time	67.95 seconds
Started	Jul 25 05:08:45 PM PDT 24
Finished	Jul 25 05:09:53 PM PDT 24
Peak memory	264372 kb
Host	smart-5eadaee2-2b95-4c4e-a20c-f6bd7414acf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364233673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.364233673
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.2235073043
Short name	T826
Test name
Test status
Simulation time	374062000 ps
CPU time	170.77 seconds
Started	Jul 25 05:08:37 PM PDT 24
Finished	Jul 25 05:11:28 PM PDT 24
Peak memory	280472 kb
Host	smart-46433611-3374-418c-a795-bac834961139
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235073043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2235073043
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.509759110
Short name	T641
Test name
Test status
Simulation time	100823300 ps
CPU time	13.81 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:08:57 PM PDT 24
Peak memory	264832 kb
Host	smart-df634340-8070-4644-b36c-455b262e1eaf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509759110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.509759110
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.2867073808
Short name	T715
Test name
Test status
Simulation time	16620000 ps
CPU time	15.57 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:09:00 PM PDT 24
Peak memory	284180 kb
Host	smart-d19169c1-f365-476a-a5ef-140e89704f6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867073808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2867073808
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.3058898904
Short name	T1100
Test name
Test status
Simulation time	13085900 ps
CPU time	21.88 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	273240 kb
Host	smart-1b7e0755-9ff0-4524-9ebb-e854e5e0b8d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058898904 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.3058898904
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2422701990
Short name	T103
Test name
Test status
Simulation time	1085201500 ps
CPU time	103.34 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	262976 kb
Host	smart-5ea2aca8-82af-400b-a45d-e9c3fda0530d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422701990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.2422701990
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.1869451090
Short name	T32
Test name
Test status
Simulation time	11187918700 ps
CPU time	207.18 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:12:11 PM PDT 24
Peak memory	290600 kb
Host	smart-5ca71438-129e-4bc7-a550-a59648cd62b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869451090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_intr_rd.1869451090
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.941950809
Short name	T829
Test name
Test status
Simulation time	49713488300 ps
CPU time	263.54 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:13:08 PM PDT 24
Peak memory	284636 kb
Host	smart-f1d24f47-2dcc-4aaa-ab23-63f86cb344be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941950809 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.941950809
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.3583747561
Short name	T1095
Test name
Test status
Simulation time	442746100 ps
CPU time	136.45 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:11:01 PM PDT 24
Peak memory	259948 kb
Host	smart-af541b22-492f-4a54-923a-6c5d850680f7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583747561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o tp_reset.3583747561
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.402739906
Short name	T380
Test name
Test status
Simulation time	71673500 ps
CPU time	14.01 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	264780 kb
Host	smart-bfe6c46b-96cc-4d28-911b-a5846fac9869
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402739906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.flash_ctrl_prog_reset.402739906
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.1747025905
Short name	T602
Test name
Test status
Simulation time	28079100 ps
CPU time	31.69 seconds
Started	Jul 25 05:08:46 PM PDT 24
Finished	Jul 25 05:09:18 PM PDT 24
Peak memory	275348 kb
Host	smart-f02b84bb-9622-448f-8036-6402eb3db17d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747025905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl ash_ctrl_rw_evict.1747025905
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.654307967
Short name	T567
Test name
Test status
Simulation time	134972000 ps
CPU time	28.94 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:09:13 PM PDT 24
Peak memory	275376 kb
Host	smart-22fd7c0d-bd5a-44f3-9b98-46f6402de7f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654307967 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.654307967
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.3447150979
Short name	T414
Test name
Test status
Simulation time	1156995800 ps
CPU time	71.18 seconds
Started	Jul 25 05:08:45 PM PDT 24
Finished	Jul 25 05:09:56 PM PDT 24
Peak memory	263028 kb
Host	smart-3bcd5ae3-0c92-44eb-b97c-f286ccbb14a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447150979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3447150979
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.1565214512
Short name	T630
Test name
Test status
Simulation time	72995100 ps
CPU time	168.07 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:11:33 PM PDT 24
Peak memory	280464 kb
Host	smart-38710c3c-664f-491c-9b57-d0b4a98dbffb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565214512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1565214512
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.2311266513
Short name	T604
Test name
Test status
Simulation time	50137300 ps
CPU time	13.3 seconds
Started	Jul 25 05:08:55 PM PDT 24
Finished	Jul 25 05:09:09 PM PDT 24
Peak memory	264936 kb
Host	smart-16707197-c473-4606-ac16-e2f92d666d7b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311266513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test. 2311266513
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.3091953849
Short name	T504
Test name
Test status
Simulation time	14393600 ps
CPU time	13.24 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:09:07 PM PDT 24
Peak memory	282868 kb
Host	smart-096beb1d-7ffc-4286-962a-435aa0473f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091953849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3091953849
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.1681352874
Short name	T393
Test name
Test status
Simulation time	12581600 ps
CPU time	21.37 seconds
Started	Jul 25 05:08:55 PM PDT 24
Finished	Jul 25 05:09:17 PM PDT 24
Peak memory	273368 kb
Host	smart-74315a19-8cbb-4799-bc91-8621eec83a57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681352874 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.1681352874
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3012249089
Short name	T519
Test name
Test status
Simulation time	1043951300 ps
CPU time	98.1 seconds
Started	Jul 25 05:08:44 PM PDT 24
Finished	Jul 25 05:10:22 PM PDT 24
Peak memory	260684 kb
Host	smart-e075e64b-ff50-4dac-8590-2f1f78ee6730
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012249089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.3012249089
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.4155469874
Short name	T297
Test name
Test status
Simulation time	1129022100 ps
CPU time	140.99 seconds
Started	Jul 25 05:08:45 PM PDT 24
Finished	Jul 25 05:11:06 PM PDT 24
Peak memory	293820 kb
Host	smart-737ef2aa-181a-4b13-bb96-98e5faacb230
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155469874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_intr_rd.4155469874
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.55921558
Short name	T486
Test name
Test status
Simulation time	24431821800 ps
CPU time	278.22 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:13:22 PM PDT 24
Peak memory	290688 kb
Host	smart-712940d8-8461-469f-8430-4682d8b9ddbf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55921558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.55921558
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.1045758411
Short name	T476
Test name
Test status
Simulation time	132947000 ps
CPU time	129.78 seconds
Started	Jul 25 05:08:43 PM PDT 24
Finished	Jul 25 05:10:53 PM PDT 24
Peak memory	259968 kb
Host	smart-327a8537-5f94-483a-b091-c1eae7df9107
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045758411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o tp_reset.1045758411
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.3544656034
Short name	T639
Test name
Test status
Simulation time	23290600 ps
CPU time	13.83 seconds
Started	Jul 25 05:08:55 PM PDT 24
Finished	Jul 25 05:09:09 PM PDT 24
Peak memory	264932 kb
Host	smart-d6de799b-9b80-4080-9d20-ed5930dde60e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544656034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.3544656034
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.859461348
Short name	T335
Test name
Test status
Simulation time	47129500 ps
CPU time	30.71 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:09:25 PM PDT 24
Peak memory	273356 kb
Host	smart-f2b4d8a8-a35b-431d-93db-154f90ce6183
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859461348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_rw_evict.859461348
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2071921131
Short name	T660
Test name
Test status
Simulation time	146111800 ps
CPU time	31.84 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:09:25 PM PDT 24
Peak memory	275316 kb
Host	smart-f9902dc0-e277-456a-bd04-86770affc484
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071921131 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2071921131
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.1168703626
Short name	T886
Test name
Test status
Simulation time	1602433800 ps
CPU time	65.62 seconds
Started	Jul 25 05:08:52 PM PDT 24
Finished	Jul 25 05:09:57 PM PDT 24
Peak memory	263400 kb
Host	smart-72a0e5de-0abb-4c4a-86bf-63739ef1f21d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168703626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1168703626
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.489205735
Short name	T368
Test name
Test status
Simulation time	21818900 ps
CPU time	75.53 seconds
Started	Jul 25 05:08:45 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	275220 kb
Host	smart-c9718e96-ab68-4ee6-992a-df277e371578
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489205735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.489205735
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.84967832
Short name	T889
Test name
Test status
Simulation time	43255800 ps
CPU time	13.82 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:09:08 PM PDT 24
Peak memory	264824 kb
Host	smart-4219ae1d-8330-446c-aeb7-42780f216fff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84967832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.84967832
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.1603327597
Short name	T437
Test name
Test status
Simulation time	15016300 ps
CPU time	13.3 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	284036 kb
Host	smart-e7bd219a-fd4e-4431-bd29-304cfa3c3fb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603327597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1603327597
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.3105808813
Short name	T493
Test name
Test status
Simulation time	13436000 ps
CPU time	21.59 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:09:14 PM PDT 24
Peak memory	273236 kb
Host	smart-96434c59-866c-4214-824b-cdbcd18670e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105808813 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.3105808813
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.688202984
Short name	T307
Test name
Test status
Simulation time	5446090000 ps
CPU time	235.4 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:12:49 PM PDT 24
Peak memory	262964 kb
Host	smart-02de911e-68df-4b69-847f-e6b4e0412a9a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688202984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h w_sec_otp.688202984
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.1660868325
Short name	T3
Test name
Test status
Simulation time	8120679400 ps
CPU time	222.09 seconds
Started	Jul 25 05:08:55 PM PDT 24
Finished	Jul 25 05:12:37 PM PDT 24
Peak memory	290676 kb
Host	smart-a349f854-721e-491b-b179-a8f6b30d07d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660868325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_intr_rd.1660868325
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.4071105057
Short name	T319
Test name
Test status
Simulation time	24659328700 ps
CPU time	331.39 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:14:24 PM PDT 24
Peak memory	284616 kb
Host	smart-ce076c2f-d3e4-4537-bdd7-8b6d65c600b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071105057 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.4071105057
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.2338126984
Short name	T453
Test name
Test status
Simulation time	40777300 ps
CPU time	131.41 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:11:04 PM PDT 24
Peak memory	260744 kb
Host	smart-0e2d30a1-7df7-423e-acae-2a1e307a4f6d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338126984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o tp_reset.2338126984
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.136152970
Short name	T385
Test name
Test status
Simulation time	124394800 ps
CPU time	19.53 seconds
Started	Jul 25 05:08:55 PM PDT 24
Finished	Jul 25 05:09:14 PM PDT 24
Peak memory	259048 kb
Host	smart-d668909e-3b23-4fd6-8d6e-c3a099a126ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136152970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.flash_ctrl_prog_reset.136152970
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.3776502975
Short name	T687
Test name
Test status
Simulation time	28570800 ps
CPU time	29.41 seconds
Started	Jul 25 05:08:51 PM PDT 24
Finished	Jul 25 05:09:21 PM PDT 24
Peak memory	275244 kb
Host	smart-4f77cbc4-b0b2-45f1-bd03-19e3a9a2122b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776502975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl ash_ctrl_rw_evict.3776502975
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.600512741
Short name	T478
Test name
Test status
Simulation time	26521300 ps
CPU time	31.31 seconds
Started	Jul 25 05:08:53 PM PDT 24
Finished	Jul 25 05:09:24 PM PDT 24
Peak memory	275360 kb
Host	smart-d213fb3f-6cb6-4c9b-a178-768fd71528db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600512741 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.600512741
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.3644785372
Short name	T603
Test name
Test status
Simulation time	2725231900 ps
CPU time	71.87 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:10:06 PM PDT 24
Peak memory	262956 kb
Host	smart-8b136717-16c4-4301-bcf8-d3ff92f20790
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644785372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3644785372
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.398895149
Short name	T495
Test name
Test status
Simulation time	99105200 ps
CPU time	149.06 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:11:23 PM PDT 24
Peak memory	278160 kb
Host	smart-00cc7ac9-6652-4c7e-b468-2a0d77135408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398895149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.398895149
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.2823206964
Short name	T588
Test name
Test status
Simulation time	101715100 ps
CPU time	14.25 seconds
Started	Jul 25 05:09:01 PM PDT 24
Finished	Jul 25 05:09:15 PM PDT 24
Peak memory	257836 kb
Host	smart-14cda770-728d-469a-8daa-3d8e14c00499
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823206964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test. 2823206964
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.1000777492
Short name	T457
Test name
Test status
Simulation time	17337200 ps
CPU time	13.26 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:09:13 PM PDT 24
Peak memory	284032 kb
Host	smart-4c0d98dd-0720-4cf3-8fc9-fdc786cb3c18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000777492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1000777492
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.716561079
Short name	T760
Test name
Test status
Simulation time	10748700 ps
CPU time	20.55 seconds
Started	Jul 25 05:09:01 PM PDT 24
Finished	Jul 25 05:09:21 PM PDT 24
Peak memory	266032 kb
Host	smart-ce5cef01-acd6-418f-b4ef-f553b300670c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716561079 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.716561079
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.708672081
Short name	T5
Test name
Test status
Simulation time	3959460800 ps
CPU time	151.71 seconds
Started	Jul 25 05:08:52 PM PDT 24
Finished	Jul 25 05:11:24 PM PDT 24
Peak memory	263164 kb
Host	smart-5957fb21-ca92-4781-a77a-dafac9006a19
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708672081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h w_sec_otp.708672081
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2383508645
Short name	T794
Test name
Test status
Simulation time	15574704200 ps
CPU time	122.06 seconds
Started	Jul 25 05:08:52 PM PDT 24
Finished	Jul 25 05:10:54 PM PDT 24
Peak memory	292332 kb
Host	smart-2b8e73e4-d5e6-405e-83b5-2ab9a74b803e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383508645 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.2383508645
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.1113921685
Short name	T562
Test name
Test status
Simulation time	40253600 ps
CPU time	110.14 seconds
Started	Jul 25 05:08:55 PM PDT 24
Finished	Jul 25 05:10:45 PM PDT 24
Peak memory	264872 kb
Host	smart-e4db2637-d6c5-4560-9265-71b53da809fd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113921685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.1113921685
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.3195687470
Short name	T1041
Test name
Test status
Simulation time	26674500 ps
CPU time	13.49 seconds
Started	Jul 25 05:08:52 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	258752 kb
Host	smart-df7b8854-26fa-4b76-a48f-8359158bfadc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195687470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.3195687470
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.1802587151
Short name	T506
Test name
Test status
Simulation time	28281800 ps
CPU time	30.79 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:09:24 PM PDT 24
Peak memory	275280 kb
Host	smart-83a86994-ea25-4848-bc03-0afdff908aca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802587151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl ash_ctrl_rw_evict.1802587151
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.1167241719
Short name	T918
Test name
Test status
Simulation time	549274100 ps
CPU time	61.12 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:10:01 PM PDT 24
Peak memory	264008 kb
Host	smart-865765ca-6a58-468b-b34b-529fd1a5c0f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167241719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1167241719
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.31725802
Short name	T689
Test name
Test status
Simulation time	1417239600 ps
CPU time	148.91 seconds
Started	Jul 25 05:08:54 PM PDT 24
Finished	Jul 25 05:11:23 PM PDT 24
Peak memory	281100 kb
Host	smart-effa2723-9eb9-4b76-94c8-5230734bbff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31725802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.31725802
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.2721055890
Short name	T549
Test name
Test status
Simulation time	24827300 ps
CPU time	13.14 seconds
Started	Jul 25 05:09:01 PM PDT 24
Finished	Jul 25 05:09:15 PM PDT 24
Peak memory	282936 kb
Host	smart-077550dc-fbb6-4413-a931-c51224ccf266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721055890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2721055890
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.3753091432
Short name	T585
Test name
Test status
Simulation time	91495000 ps
CPU time	21.97 seconds
Started	Jul 25 05:09:04 PM PDT 24
Finished	Jul 25 05:09:26 PM PDT 24
Peak memory	273272 kb
Host	smart-37b8a7e3-fb7b-49f0-8645-d7aad5448746
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753091432 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.3753091432
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3161282432
Short name	T1098
Test name
Test status
Simulation time	2897588500 ps
CPU time	88.8 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:10:29 PM PDT 24
Peak memory	260504 kb
Host	smart-5ba952f1-cd35-47a6-8d0d-a6d82000f21d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161282432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.3161282432
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.3681667839
Short name	T1045
Test name
Test status
Simulation time	4525465600 ps
CPU time	144.38 seconds
Started	Jul 25 05:09:02 PM PDT 24
Finished	Jul 25 05:11:26 PM PDT 24
Peak memory	294772 kb
Host	smart-dd574cf1-ec29-415a-a77c-f964a6f63e53
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681667839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_intr_rd.3681667839
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2288985569
Short name	T670
Test name
Test status
Simulation time	6146929600 ps
CPU time	145.51 seconds
Started	Jul 25 05:09:01 PM PDT 24
Finished	Jul 25 05:11:27 PM PDT 24
Peak memory	290716 kb
Host	smart-92deded1-a3c0-4b98-b85f-ef1a1f40c1da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288985569 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2288985569
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.1686282435
Short name	T151
Test name
Test status
Simulation time	59244300 ps
CPU time	133.08 seconds
Started	Jul 25 05:09:04 PM PDT 24
Finished	Jul 25 05:11:17 PM PDT 24
Peak memory	259792 kb
Host	smart-93f346b4-dd54-40ba-baf1-58df1c27f35b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686282435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o tp_reset.1686282435
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.1318274162
Short name	T986
Test name
Test status
Simulation time	20380500 ps
CPU time	13.64 seconds
Started	Jul 25 05:09:03 PM PDT 24
Finished	Jul 25 05:09:17 PM PDT 24
Peak memory	264840 kb
Host	smart-273e3d35-38a8-40eb-9d04-2f23a074d749
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318274162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.flash_ctrl_prog_reset.1318274162
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.177537925
Short name	T341
Test name
Test status
Simulation time	300132400 ps
CPU time	28.69 seconds
Started	Jul 25 05:09:02 PM PDT 24
Finished	Jul 25 05:09:30 PM PDT 24
Peak memory	275400 kb
Host	smart-d2b210d3-99bc-4d00-a0af-c2cd5bdf125f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177537925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_rw_evict.177537925
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.4208565943
Short name	T208
Test name
Test status
Simulation time	29424300 ps
CPU time	28.97 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:09:29 PM PDT 24
Peak memory	273328 kb
Host	smart-2f14ece9-41d6-4ae8-9e87-d715bfa009cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208565943 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.4208565943
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.1547062737
Short name	T470
Test name
Test status
Simulation time	420005200 ps
CPU time	58.95 seconds
Started	Jul 25 05:08:59 PM PDT 24
Finished	Jul 25 05:09:58 PM PDT 24
Peak memory	262964 kb
Host	smart-1964d288-7e8c-4f51-925b-d614e08faacc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547062737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1547062737
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.2611948409
Short name	T1047
Test name
Test status
Simulation time	19308500 ps
CPU time	52.26 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:09:52 PM PDT 24
Peak memory	270924 kb
Host	smart-e5b9d3cc-3540-4663-8b27-4a9f131186c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611948409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2611948409
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.2456603334
Short name	T745
Test name
Test status
Simulation time	81701900 ps
CPU time	13.97 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:09:24 PM PDT 24
Peak memory	264404 kb
Host	smart-559c618c-b88d-48da-a9ab-1b937b7ce7f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456603334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test. 2456603334
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.889169237
Short name	T620
Test name
Test status
Simulation time	63848400 ps
CPU time	16.35 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:09:17 PM PDT 24
Peak memory	274692 kb
Host	smart-acdf4edf-7333-45dd-9a02-99d53581db30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889169237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.889169237
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2625684690
Short name	T565
Test name
Test status
Simulation time	7066812400 ps
CPU time	71.7 seconds
Started	Jul 25 05:09:02 PM PDT 24
Finished	Jul 25 05:10:14 PM PDT 24
Peak memory	261920 kb
Host	smart-f614b5c8-4404-49bd-935f-74c11c2dc7dc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625684690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.2625684690
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.3194066398
Short name	T322
Test name
Test status
Simulation time	712239900 ps
CPU time	148.23 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:11:28 PM PDT 24
Peak memory	293612 kb
Host	smart-6b886902-26bc-4903-8ae4-d74ab244412c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194066398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.3194066398
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.1271340878
Short name	T173
Test name
Test status
Simulation time	65615300 ps
CPU time	133.86 seconds
Started	Jul 25 05:09:02 PM PDT 24
Finished	Jul 25 05:11:16 PM PDT 24
Peak memory	259996 kb
Host	smart-a188a131-2f82-494a-9356-a3f10ecb1d05
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271340878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.1271340878
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.4113047681
Short name	T849
Test name
Test status
Simulation time	10278751400 ps
CPU time	174.55 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:11:55 PM PDT 24
Peak memory	259700 kb
Host	smart-51c92f3d-0881-419d-9712-5107f5ee09b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113047681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.4113047681
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.3205850556
Short name	T838
Test name
Test status
Simulation time	41424600 ps
CPU time	31.33 seconds
Started	Jul 25 05:09:00 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	275244 kb
Host	smart-8066520e-acf0-42ce-8a1c-b2216132c296
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205850556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl ash_ctrl_rw_evict.3205850556
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.4104432652
Short name	T703
Test name
Test status
Simulation time	28361700 ps
CPU time	30.59 seconds
Started	Jul 25 05:09:04 PM PDT 24
Finished	Jul 25 05:09:35 PM PDT 24
Peak memory	275376 kb
Host	smart-5a274fef-e91e-42b3-ac5b-efbd9a9e980d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104432652 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.4104432652
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.2228118710
Short name	T924
Test name
Test status
Simulation time	2446011900 ps
CPU time	68.03 seconds
Started	Jul 25 05:09:02 PM PDT 24
Finished	Jul 25 05:10:10 PM PDT 24
Peak memory	264008 kb
Host	smart-a57b5b21-6e82-4006-8cce-19e1df179a70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228118710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2228118710
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.1606537500
Short name	T1077
Test name
Test status
Simulation time	877107100 ps
CPU time	128.58 seconds
Started	Jul 25 05:09:04 PM PDT 24
Finished	Jul 25 05:11:13 PM PDT 24
Peak memory	281368 kb
Host	smart-b3dfec1c-df47-4cee-bd3d-0fc93f5c5c83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606537500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1606537500
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.2134820144
Short name	T1000
Test name
Test status
Simulation time	24240100 ps
CPU time	13.8 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:09:24 PM PDT 24
Peak memory	257968 kb
Host	smart-21a14b48-d893-4244-a38a-2b5ad33a05a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134820144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test. 2134820144
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.4107772530
Short name	T904
Test name
Test status
Simulation time	15100900 ps
CPU time	15.81 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:09:26 PM PDT 24
Peak memory	282824 kb
Host	smart-390de8cd-9ba6-4744-8553-68704b212e59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107772530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.4107772530
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1145398900
Short name	T436
Test name
Test status
Simulation time	1157379300 ps
CPU time	44.06 seconds
Started	Jul 25 05:09:09 PM PDT 24
Finished	Jul 25 05:09:54 PM PDT 24
Peak memory	260452 kb
Host	smart-2f8ac631-7e82-441b-9fef-ad984fe6cadb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145398900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ hw_sec_otp.1145398900
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.2885460745
Short name	T747
Test name
Test status
Simulation time	1757359100 ps
CPU time	190.08 seconds
Started	Jul 25 05:09:11 PM PDT 24
Finished	Jul 25 05:12:22 PM PDT 24
Peak memory	290696 kb
Host	smart-e62dec57-1a6f-47f4-b3a5-3722e53410ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885460745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.2885460745
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1764378967
Short name	T1002
Test name
Test status
Simulation time	49425471200 ps
CPU time	308.18 seconds
Started	Jul 25 05:09:09 PM PDT 24
Finished	Jul 25 05:14:18 PM PDT 24
Peak memory	290792 kb
Host	smart-01e88837-5fb2-498b-a41a-ece1d421334e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764378967 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1764378967
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.70110003
Short name	T861
Test name
Test status
Simulation time	42596400 ps
CPU time	111.03 seconds
Started	Jul 25 05:09:11 PM PDT 24
Finished	Jul 25 05:11:02 PM PDT 24
Peak memory	259776 kb
Host	smart-dbd05372-af15-4383-bd28-7a86de0dcf1c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70110003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp _reset.70110003
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.2420612259
Short name	T606
Test name
Test status
Simulation time	56806300 ps
CPU time	13.63 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:09:23 PM PDT 24
Peak memory	258824 kb
Host	smart-e81521f2-58f5-450e-beca-7c5c7e2a5dc6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420612259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.2420612259
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.3387175085
Short name	T593
Test name
Test status
Simulation time	77623600 ps
CPU time	28.87 seconds
Started	Jul 25 05:09:13 PM PDT 24
Finished	Jul 25 05:09:42 PM PDT 24
Peak memory	267180 kb
Host	smart-13b8cf39-eaf5-4ac2-ba0c-d465176d270e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387175085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl ash_ctrl_rw_evict.3387175085
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2350544910
Short name	T446
Test name
Test status
Simulation time	29534900 ps
CPU time	30.72 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:09:41 PM PDT 24
Peak memory	275368 kb
Host	smart-07e22200-447a-4322-b02d-451daafb4390
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350544910 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2350544910
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.950247993
Short name	T802
Test name
Test status
Simulation time	2023143800 ps
CPU time	75.55 seconds
Started	Jul 25 05:09:09 PM PDT 24
Finished	Jul 25 05:10:25 PM PDT 24
Peak memory	263276 kb
Host	smart-6089ee66-c70b-4137-a60e-772db9a287c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950247993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.950247993
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.1795188722
Short name	T652
Test name
Test status
Simulation time	28958000 ps
CPU time	75.06 seconds
Started	Jul 25 05:09:10 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	276488 kb
Host	smart-705e8ff9-2e39-40c6-ba15-e6c2f2d349ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795188722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1795188722
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.664280388
Short name	T309
Test name
Test status
Simulation time	21800500 ps
CPU time	13.39 seconds
Started	Jul 25 05:09:24 PM PDT 24
Finished	Jul 25 05:09:38 PM PDT 24
Peak memory	257972 kb
Host	smart-de453db1-c55a-4751-8b35-d4398d72f130
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664280388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.664280388
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.1505269321
Short name	T780
Test name
Test status
Simulation time	23935200 ps
CPU time	15.44 seconds
Started	Jul 25 05:09:24 PM PDT 24
Finished	Jul 25 05:09:40 PM PDT 24
Peak memory	282884 kb
Host	smart-0d950938-f126-4bcb-a345-5e5f0f98bf42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505269321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1505269321
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.1911226275
Short name	T892
Test name
Test status
Simulation time	14015100 ps
CPU time	21.99 seconds
Started	Jul 25 05:09:22 PM PDT 24
Finished	Jul 25 05:09:44 PM PDT 24
Peak memory	273248 kb
Host	smart-e6d47b5f-e67d-4da9-b73c-967a79d5234e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911226275 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.1911226275
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1885777858
Short name	T306
Test name
Test status
Simulation time	18589745900 ps
CPU time	123.18 seconds
Started	Jul 25 05:09:11 PM PDT 24
Finished	Jul 25 05:11:14 PM PDT 24
Peak memory	261940 kb
Host	smart-d117f738-ea1b-4dfd-ac9b-c6c3cd40d5fa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885777858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.1885777858
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.1385211053
Short name	T869
Test name
Test status
Simulation time	1903982700 ps
CPU time	206.87 seconds
Started	Jul 25 05:09:12 PM PDT 24
Finished	Jul 25 05:12:39 PM PDT 24
Peak memory	284536 kb
Host	smart-196f8c5e-768e-4087-bc31-709394dd165a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385211053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_intr_rd.1385211053
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3061535953
Short name	T832
Test name
Test status
Simulation time	23707651600 ps
CPU time	152.37 seconds
Started	Jul 25 05:09:08 PM PDT 24
Finished	Jul 25 05:11:41 PM PDT 24
Peak memory	292288 kb
Host	smart-f1b5925c-c728-4586-b378-3a8132da806a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061535953 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3061535953
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.768515109
Short name	T584
Test name
Test status
Simulation time	177000800 ps
CPU time	130.99 seconds
Started	Jul 25 05:09:12 PM PDT 24
Finished	Jul 25 05:11:23 PM PDT 24
Peak memory	259760 kb
Host	smart-808b4537-dc6f-4c3d-96de-39742a68a9b1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768515109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot p_reset.768515109
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.3706193289
Short name	T798
Test name
Test status
Simulation time	53261200 ps
CPU time	13.25 seconds
Started	Jul 25 05:09:24 PM PDT 24
Finished	Jul 25 05:09:37 PM PDT 24
Peak memory	258808 kb
Host	smart-f53b4bc2-2896-4ac2-bd17-47dd643dd96b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706193289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.flash_ctrl_prog_reset.3706193289
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.1986130900
Short name	T825
Test name
Test status
Simulation time	77033000 ps
CPU time	28.7 seconds
Started	Jul 25 05:09:24 PM PDT 24
Finished	Jul 25 05:09:53 PM PDT 24
Peak memory	268160 kb
Host	smart-50cd12b0-2972-4ca2-ab47-4a8e525b5512
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986130900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.1986130900
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1223234010
Short name	T265
Test name
Test status
Simulation time	37334300 ps
CPU time	31.55 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:09:49 PM PDT 24
Peak memory	273304 kb
Host	smart-d15dd9b6-cb7a-48ba-b1fd-05463f275814
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223234010 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1223234010
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.4090429483
Short name	T475
Test name
Test status
Simulation time	1773814600 ps
CPU time	64.43 seconds
Started	Jul 25 05:09:19 PM PDT 24
Finished	Jul 25 05:10:24 PM PDT 24
Peak memory	261984 kb
Host	smart-a2da707f-5e66-45ec-9a7f-a2d146b0af09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090429483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.4090429483
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.151473106
Short name	T503
Test name
Test status
Simulation time	114720600 ps
CPU time	124.54 seconds
Started	Jul 25 05:09:09 PM PDT 24
Finished	Jul 25 05:11:14 PM PDT 24
Peak memory	276100 kb
Host	smart-ebc08109-5187-47d4-a869-f1298751d5be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151473106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.151473106
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.1008591695
Short name	T1040
Test name
Test status
Simulation time	378057900 ps
CPU time	13.77 seconds
Started	Jul 25 05:09:21 PM PDT 24
Finished	Jul 25 05:09:35 PM PDT 24
Peak memory	257892 kb
Host	smart-8cad94ab-6efa-4ba4-ba03-d48d9a6ff6f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008591695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 1008591695
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.3285881380
Short name	T968
Test name
Test status
Simulation time	16958000 ps
CPU time	15.64 seconds
Started	Jul 25 05:09:20 PM PDT 24
Finished	Jul 25 05:09:36 PM PDT 24
Peak memory	282892 kb
Host	smart-5402027c-5516-4f8f-ab5e-0a5b3b68549a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285881380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3285881380
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2495852483
Short name	T743
Test name
Test status
Simulation time	16953926800 ps
CPU time	111.37 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:11:10 PM PDT 24
Peak memory	263000 kb
Host	smart-eb032a8e-eaad-47b4-8ec0-195461a231d7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495852483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ hw_sec_otp.2495852483
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.2070926025
Short name	T701
Test name
Test status
Simulation time	4443633900 ps
CPU time	142.17 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:11:40 PM PDT 24
Peak memory	293772 kb
Host	smart-16f944c9-9160-433c-805d-4e048c21125b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070926025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.2070926025
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3343245796
Short name	T304
Test name
Test status
Simulation time	24482056700 ps
CPU time	151.01 seconds
Started	Jul 25 05:09:19 PM PDT 24
Finished	Jul 25 05:11:50 PM PDT 24
Peak memory	294064 kb
Host	smart-8a6e0f85-0d31-4245-85e1-04f749239d9f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343245796 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.3343245796
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.3542030134
Short name	T572
Test name
Test status
Simulation time	39321600 ps
CPU time	130.58 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:11:29 PM PDT 24
Peak memory	259956 kb
Host	smart-45dbe98c-3241-4348-a07c-5c8077d255e2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542030134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o tp_reset.3542030134
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.2402681845
Short name	T376
Test name
Test status
Simulation time	69950400 ps
CPU time	13.76 seconds
Started	Jul 25 05:09:19 PM PDT 24
Finished	Jul 25 05:09:33 PM PDT 24
Peak memory	264912 kb
Host	smart-9d681d41-4c9b-4aff-ab75-48784ec046c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402681845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.flash_ctrl_prog_reset.2402681845
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.258851977
Short name	T997
Test name
Test status
Simulation time	73914300 ps
CPU time	31.12 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:09:49 PM PDT 24
Peak memory	275372 kb
Host	smart-3cf8580d-d794-4fba-acff-c00aa0cad356
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258851977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_rw_evict.258851977
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1948742230
Short name	T708
Test name
Test status
Simulation time	45034700 ps
CPU time	31.02 seconds
Started	Jul 25 05:09:19 PM PDT 24
Finished	Jul 25 05:09:50 PM PDT 24
Peak memory	275352 kb
Host	smart-a8af54e7-4bee-4e03-90e1-b220ccb08365
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948742230 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1948742230
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.1483013633
Short name	T891
Test name
Test status
Simulation time	1362937400 ps
CPU time	52.24 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:10:11 PM PDT 24
Peak memory	264584 kb
Host	smart-e1fc94ef-0107-415c-a908-380c0ffd1cbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483013633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1483013633
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.703331736
Short name	T1101
Test name
Test status
Simulation time	35382500 ps
CPU time	49.43 seconds
Started	Jul 25 05:09:18 PM PDT 24
Finished	Jul 25 05:10:08 PM PDT 24
Peak memory	270988 kb
Host	smart-268aa9fc-0df7-4324-b0f2-dfba7e9276ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703331736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.703331736
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.546084606
Short name	T101
Test name
Test status
Simulation time	23423400 ps
CPU time	13.67 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:06:48 PM PDT 24
Peak memory	257832 kb
Host	smart-a9706d59-be8b-4931-9e22-0be05d0280a9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546084606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.546084606
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.2964418666
Short name	T220
Test name
Test status
Simulation time	77744500 ps
CPU time	13.97 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:06:48 PM PDT 24
Peak memory	261364 kb
Host	smart-a3457d0b-f438-4d4f-8b63-238b949db55f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964418666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.2964418666
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.1858228292
Short name	T786
Test name
Test status
Simulation time	57021300 ps
CPU time	15.87 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:06:50 PM PDT 24
Peak memory	284124 kb
Host	smart-9ee6dc3a-2dd9-4905-a7a4-45bcccf5dc06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858228292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1858228292
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.192976417
Short name	T991
Test name
Test status
Simulation time	53428800 ps
CPU time	20.99 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:06:52 PM PDT 24
Peak memory	265176 kb
Host	smart-7056e01a-0984-4485-a08c-03b7216dcc9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192976417 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.192976417
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.4033776370
Short name	T1042
Test name
Test status
Simulation time	1451492500 ps
CPU time	361.68 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:12:26 PM PDT 24
Peak memory	263124 kb
Host	smart-96f8ce5c-7d7c-4a84-813f-1d91657a3a03
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4033776370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.4033776370
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.307827930
Short name	T1111
Test name
Test status
Simulation time	2468045400 ps
CPU time	2255.99 seconds
Started	Jul 25 05:06:22 PM PDT 24
Finished	Jul 25 05:43:59 PM PDT 24
Peak memory	262588 kb
Host	smart-faf0e03f-3b16-422e-adab-e252b9d1e5a8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=307827930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.307827930
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.3321107473
Short name	T1025
Test name
Test status
Simulation time	2933115700 ps
CPU time	1911.83 seconds
Started	Jul 25 05:06:27 PM PDT 24
Finished	Jul 25 05:38:19 PM PDT 24
Peak memory	261720 kb
Host	smart-596bb486-1ed8-473f-84dd-8bcc61fa594d
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321107473 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3321107473
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.3142117891
Short name	T953
Test name
Test status
Simulation time	4294528300 ps
CPU time	868.41 seconds
Started	Jul 25 05:06:25 PM PDT 24
Finished	Jul 25 05:20:54 PM PDT 24
Peak memory	272280 kb
Host	smart-2816ff0e-81a0-49d7-8852-0425f3dfb798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142117891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3142117891
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.2874165930
Short name	T852
Test name
Test status
Simulation time	618421200 ps
CPU time	27.84 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:06:52 PM PDT 24
Peak memory	263288 kb
Host	smart-e7d2ec0f-29de-4d4b-b2f6-dbd63aab85eb
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874165930 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2874165930
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.2475118064
Short name	T929
Test name
Test status
Simulation time	333227700 ps
CPU time	39.55 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:07:14 PM PDT 24
Peak memory	262636 kb
Host	smart-6083ba10-2942-4ff1-92a2-98a360c39a26
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475118064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_fs_sup.2475118064
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1610444260
Short name	T179
Test name
Test status
Simulation time	228636471000 ps
CPU time	2520.34 seconds
Started	Jul 25 05:06:29 PM PDT 24
Finished	Jul 25 05:48:30 PM PDT 24
Peak memory	263776 kb
Host	smart-b6638c17-bfbf-471a-a234-857ef4186d9d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610444260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.1610444260
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.2364453136
Short name	T912
Test name
Test status
Simulation time	25697200 ps
CPU time	34.96 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:06:59 PM PDT 24
Peak memory	262464 kb
Host	smart-cf68102a-ec26-440f-af0e-4fefb46b0d27
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2364453136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2364453136
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2999613603
Short name	T171
Test name
Test status
Simulation time	10012129300 ps
CPU time	119.78 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:08:33 PM PDT 24
Peak memory	313060 kb
Host	smart-20961155-577d-455e-8bd1-9a623d185470
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999613603 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2999613603
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.4101236215
Short name	T524
Test name
Test status
Simulation time	16067400 ps
CPU time	13.7 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:06:46 PM PDT 24
Peak memory	264964 kb
Host	smart-fb90c1da-10ba-42f2-96f2-58ccbc8844ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101236215 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.4101236215
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.362943492
Short name	T662
Test name
Test status
Simulation time	160189001300 ps
CPU time	859.75 seconds
Started	Jul 25 05:06:22 PM PDT 24
Finished	Jul 25 05:20:42 PM PDT 24
Peak memory	260576 kb
Host	smart-70b2c173-3209-4c1b-9d2f-27810f9a1eb0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362943492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_hw_rma_reset.362943492
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3919120723
Short name	T559
Test name
Test status
Simulation time	1835064900 ps
CPU time	75.2 seconds
Started	Jul 25 05:06:25 PM PDT 24
Finished	Jul 25 05:07:41 PM PDT 24
Peak memory	260848 kb
Host	smart-d92a1b28-d9bf-48e3-b396-3513907db3dd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919120723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h w_sec_otp.3919120723
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.3712810612
Short name	T217
Test name
Test status
Simulation time	3554846200 ps
CPU time	134.09 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:08:47 PM PDT 24
Peak memory	293204 kb
Host	smart-9c743af4-f4a3-46cd-a6ac-3586070d2cb4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712810612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.3712810612
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3112767987
Short name	T1068
Test name
Test status
Simulation time	64498448100 ps
CPU time	258.49 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	289660 kb
Host	smart-3a16e3db-8d83-4486-9e67-ad06f744a5be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112767987 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3112767987
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.659698517
Short name	T458
Test name
Test status
Simulation time	2201867100 ps
CPU time	64.11 seconds
Started	Jul 25 05:06:39 PM PDT 24
Finished	Jul 25 05:07:43 PM PDT 24
Peak memory	260284 kb
Host	smart-4bb65188-3a0b-49c4-9fc0-92d67728fe92
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659698517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_intr_wr.659698517
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3279565462
Short name	T764
Test name
Test status
Simulation time	41471151800 ps
CPU time	177.05 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:09:29 PM PDT 24
Peak memory	259516 kb
Host	smart-09abdd16-64f8-4157-a87d-97f2f03b4702
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327 9565462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3279565462
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1519649229
Short name	T516
Test name
Test status
Simulation time	31785200 ps
CPU time	13.48 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:06:47 PM PDT 24
Peak memory	259600 kb
Host	smart-4fb1dd49-864f-425b-97e1-2366040c0b37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519649229 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.1519649229
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.2777893984
Short name	T56
Test name
Test status
Simulation time	1644162400 ps
CPU time	72.85 seconds
Started	Jul 25 05:06:27 PM PDT 24
Finished	Jul 25 05:07:40 PM PDT 24
Peak memory	260532 kb
Host	smart-d14fc05d-0fcd-4679-aaea-0bbfe0ffb326
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777893984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2777893984
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.285797542
Short name	T887
Test name
Test status
Simulation time	33746002300 ps
CPU time	657.82 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:17:30 PM PDT 24
Peak memory	275300 kb
Host	smart-a9f8ffd7-8ec4-4b05-a0a9-147675993941
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285797542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.285797542
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.559191040
Short name	T1034
Test name
Test status
Simulation time	139222000 ps
CPU time	130.4 seconds
Started	Jul 25 05:06:22 PM PDT 24
Finished	Jul 25 05:08:32 PM PDT 24
Peak memory	260828 kb
Host	smart-b8c66ea0-2565-4ee5-bc0d-53d52f3ec548
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559191040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp _reset.559191040
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1358044383
Short name	T195
Test name
Test status
Simulation time	141764800 ps
CPU time	13.88 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:06:47 PM PDT 24
Peak memory	261408 kb
Host	smart-fba12e23-aff5-4d61-aae9-848e51057272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1358044383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1358044383
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.3763378741
Short name	T900
Test name
Test status
Simulation time	1414348000 ps
CPU time	257.47 seconds
Started	Jul 25 05:06:22 PM PDT 24
Finished	Jul 25 05:10:40 PM PDT 24
Peak memory	262948 kb
Host	smart-6d5ab911-6b36-4678-beec-a9496ceb185b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3763378741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3763378741
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.747204019
Short name	T520
Test name
Test status
Simulation time	23595700 ps
CPU time	13.41 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:06:45 PM PDT 24
Peak memory	259124 kb
Host	smart-b413f27e-a5d1-4b68-ba37-87ebd6071acd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747204019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.flash_ctrl_prog_reset.747204019
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.1241430130
Short name	T1020
Test name
Test status
Simulation time	805843700 ps
CPU time	1029.74 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:23:34 PM PDT 24
Peak memory	287488 kb
Host	smart-b72382f5-70a6-4c6b-a3ea-cda813cc470a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1241430130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1241430130
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.703158036
Short name	T1067
Test name
Test status
Simulation time	75935100 ps
CPU time	99.74 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:08:11 PM PDT 24
Peak memory	262540 kb
Host	smart-84da6988-0bbd-47d1-b80b-c0c02d3c6bde
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=703158036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.703158036
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3362958528
Short name	T511
Test name
Test status
Simulation time	61073200 ps
CPU time	21.25 seconds
Started	Jul 25 05:06:26 PM PDT 24
Finished	Jul 25 05:06:48 PM PDT 24
Peak memory	265056 kb
Host	smart-2674c534-88d8-4a89-9ff0-598a33849809
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362958528 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3362958528
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1646491410
Short name	T386
Test name
Test status
Simulation time	23434400 ps
CPU time	23.19 seconds
Started	Jul 25 05:06:27 PM PDT 24
Finished	Jul 25 05:06:51 PM PDT 24
Peak memory	265076 kb
Host	smart-55840b63-bd3a-4ebc-88b3-0e89c4d9894b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646491410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_read_word_sweep_serr.1646491410
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.1695636655
Short name	T901
Test name
Test status
Simulation time	2083146100 ps
CPU time	120.21 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:08:24 PM PDT 24
Peak memory	281500 kb
Host	smart-6691ab2c-5858-4c7d-a5c8-15d2b6fec61f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695636655 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_ro.1695636655
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.4176081209
Short name	T51
Test name
Test status
Simulation time	647267500 ps
CPU time	136.51 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:08:51 PM PDT 24
Peak memory	281544 kb
Host	smart-397b093b-fdc1-471a-86a6-d4a9e1105d1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4176081209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.4176081209
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.635687441
Short name	T864
Test name
Test status
Simulation time	1616212300 ps
CPU time	145.84 seconds
Started	Jul 25 05:06:23 PM PDT 24
Finished	Jul 25 05:08:49 PM PDT 24
Peak memory	294752 kb
Host	smart-b5b2b520-fc2c-4d73-b2e1-28221ba276d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635687441 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.635687441
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.2769980382
Short name	T206
Test name
Test status
Simulation time	59069638400 ps
CPU time	592.63 seconds
Started	Jul 25 05:06:23 PM PDT 24
Finished	Jul 25 05:16:15 PM PDT 24
Peak memory	309272 kb
Host	smart-40a9963d-8152-493a-a8ba-e1c8b3e201fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769980382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.flash_ctrl_rw.2769980382
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict.2826227103
Short name	T634
Test name
Test status
Simulation time	67948800 ps
CPU time	30.32 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:07:02 PM PDT 24
Peak memory	273268 kb
Host	smart-168e13e2-faf5-4f24-9359-4a943db827f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826227103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_rw_evict.2826227103
Directory	/workspace/3.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.4092617562
Short name	T487
Test name
Test status
Simulation time	76009800 ps
CPU time	30.7 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:29 PM PDT 24
Peak memory	275244 kb
Host	smart-32e2d785-521d-4f28-b53b-5c870e6af884
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092617562 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.4092617562
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.2120982135
Short name	T735
Test name
Test status
Simulation time	4018463000 ps
CPU time	659.26 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:17:31 PM PDT 24
Peak memory	320604 kb
Host	smart-bae80e47-1496-40db-b8fb-0ad9161ba2cb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120982135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s err.2120982135
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.1969319360
Short name	T409
Test name
Test status
Simulation time	27122861300 ps
CPU time	74.56 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	264520 kb
Host	smart-004a2508-e332-4b5b-99c4-831dbcc7c5e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969319360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1969319360
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.268092814
Short name	T556
Test name
Test status
Simulation time	8954601700 ps
CPU time	83.73 seconds
Started	Jul 25 05:06:23 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	273196 kb
Host	smart-7fb54adf-5481-4763-9b2f-b9e6785dd0a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268092814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr_address.268092814
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.3127749308
Short name	T751
Test name
Test status
Simulation time	543340700 ps
CPU time	61.93 seconds
Started	Jul 25 05:06:27 PM PDT 24
Finished	Jul 25 05:07:30 PM PDT 24
Peak memory	274348 kb
Host	smart-a2aed199-c176-492b-8fa5-5f80b3f24dd7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127749308 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_serr_counter.3127749308
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.2205422754
Short name	T681
Test name
Test status
Simulation time	147757600 ps
CPU time	171.51 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:09:22 PM PDT 24
Peak memory	276884 kb
Host	smart-b47a1936-c221-40de-b2e5-a154cde5f0f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205422754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2205422754
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.2274693480
Short name	T62
Test name
Test status
Simulation time	16061800 ps
CPU time	26.15 seconds
Started	Jul 25 05:06:25 PM PDT 24
Finished	Jul 25 05:06:51 PM PDT 24
Peak memory	259444 kb
Host	smart-5696ff40-3f88-40d9-b710-bf12a6581a1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274693480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2274693480
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.3337349577
Short name	T762
Test name
Test status
Simulation time	334322500 ps
CPU time	282.75 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:11:17 PM PDT 24
Peak memory	272048 kb
Host	smart-d33f6b6a-2998-4812-8061-197287a1bc5e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337349577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.3337349577
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.1491638384
Short name	T540
Test name
Test status
Simulation time	25972500 ps
CPU time	23.95 seconds
Started	Jul 25 05:06:23 PM PDT 24
Finished	Jul 25 05:06:47 PM PDT 24
Peak memory	259520 kb
Host	smart-db0b1dcf-3ee6-411f-850e-f1e0256c73e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491638384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1491638384
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.3607619872
Short name	T686
Test name
Test status
Simulation time	2363874600 ps
CPU time	203.63 seconds
Started	Jul 25 05:06:24 PM PDT 24
Finished	Jul 25 05:09:48 PM PDT 24
Peak memory	259512 kb
Host	smart-e214d0e6-0bbb-4f80-b94c-5add3d4bc1a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607619872 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.3607619872
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.1186019864
Short name	T1003
Test name
Test status
Simulation time	33257000 ps
CPU time	14.02 seconds
Started	Jul 25 05:09:30 PM PDT 24
Finished	Jul 25 05:09:45 PM PDT 24
Peak memory	264836 kb
Host	smart-8c204cac-6033-442c-8b23-223bef5f66ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186019864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test. 1186019864
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.2500351890
Short name	T111
Test name
Test status
Simulation time	15894000 ps
CPU time	15.54 seconds
Started	Jul 25 05:09:31 PM PDT 24
Finished	Jul 25 05:09:47 PM PDT 24
Peak memory	274792 kb
Host	smart-664d1962-1bdd-4482-9b0a-85038cccbff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500351890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2500351890
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.888178569
Short name	T303
Test name
Test status
Simulation time	5215049700 ps
CPU time	148.54 seconds
Started	Jul 25 05:09:20 PM PDT 24
Finished	Jul 25 05:11:48 PM PDT 24
Peak memory	263236 kb
Host	smart-c1bf6c62-673f-4322-a195-48cdd7bef21b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888178569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h w_sec_otp.888178569
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.587111049
Short name	T324
Test name
Test status
Simulation time	1450684700 ps
CPU time	156.72 seconds
Started	Jul 25 05:09:25 PM PDT 24
Finished	Jul 25 05:12:03 PM PDT 24
Peak memory	293716 kb
Host	smart-a3f54d8b-7835-49d6-821d-9b0134b025ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587111049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas h_ctrl_intr_rd.587111049
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1476480180
Short name	T327
Test name
Test status
Simulation time	61594803200 ps
CPU time	286.43 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:14:14 PM PDT 24
Peak memory	290660 kb
Host	smart-b22cde00-2e27-489b-a4fb-28985a3f8fb1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476480180 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.1476480180
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.765456086
Short name	T728
Test name
Test status
Simulation time	162905200 ps
CPU time	112.17 seconds
Started	Jul 25 05:09:21 PM PDT 24
Finished	Jul 25 05:11:13 PM PDT 24
Peak memory	261008 kb
Host	smart-c5c42d76-ef2d-4dd7-ade9-aef5781f3b64
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765456086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_ot p_reset.765456086
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict.2531535980
Short name	T563
Test name
Test status
Simulation time	40622700 ps
CPU time	30.5 seconds
Started	Jul 25 05:09:26 PM PDT 24
Finished	Jul 25 05:09:57 PM PDT 24
Peak memory	268200 kb
Host	smart-3af9d857-1bbf-43ef-b19b-9c0b6aaf8e4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531535980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl ash_ctrl_rw_evict.2531535980
Directory	/workspace/30.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3938417835
Short name	T770
Test name
Test status
Simulation time	44388200 ps
CPU time	31.45 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:09:58 PM PDT 24
Peak memory	275396 kb
Host	smart-27a09128-930d-4d9d-a85e-866ffb64be6a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938417835 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3938417835
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.932094760
Short name	T411
Test name
Test status
Simulation time	2159111200 ps
CPU time	58.35 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	264492 kb
Host	smart-22b0bc5f-f58c-4633-8f2d-7f0e29d7c40c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932094760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.932094760
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.2374269667
Short name	T222
Test name
Test status
Simulation time	2682432700 ps
CPU time	182.34 seconds
Started	Jul 25 05:09:19 PM PDT 24
Finished	Jul 25 05:12:22 PM PDT 24
Peak memory	281012 kb
Host	smart-a1b00f35-16cd-4b09-8c90-e178444747c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374269667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2374269667
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.3349984483
Short name	T946
Test name
Test status
Simulation time	107689800 ps
CPU time	13.84 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:09:41 PM PDT 24
Peak memory	257876 kb
Host	smart-87ff966b-6e65-41de-826b-58223eca6e2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349984483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 3349984483
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.2557332647
Short name	T1004
Test name
Test status
Simulation time	150532300 ps
CPU time	12.98 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:09:40 PM PDT 24
Peak memory	282748 kb
Host	smart-4cf77b4d-16c3-4ab7-9b40-da41961239f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557332647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2557332647
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.1529471295
Short name	T897
Test name
Test status
Simulation time	44105000 ps
CPU time	22.06 seconds
Started	Jul 25 05:09:30 PM PDT 24
Finished	Jul 25 05:09:53 PM PDT 24
Peak memory	265064 kb
Host	smart-d983d1e7-61ba-42cf-ae94-ca17ab6d6545
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529471295 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.1529471295
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.903484284
Short name	T633
Test name
Test status
Simulation time	5003658900 ps
CPU time	104.17 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:11:12 PM PDT 24
Peak memory	261328 kb
Host	smart-dc19868c-3bd4-438b-9b36-b061de7767db
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903484284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_h w_sec_otp.903484284
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.3089880768
Short name	T720
Test name
Test status
Simulation time	10497417700 ps
CPU time	228.11 seconds
Started	Jul 25 05:09:26 PM PDT 24
Finished	Jul 25 05:13:14 PM PDT 24
Peak memory	284508 kb
Host	smart-10e1a9cb-d7f2-45e1-9e78-d629404c295b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089880768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.3089880768
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.477088769
Short name	T801
Test name
Test status
Simulation time	48193364800 ps
CPU time	286.15 seconds
Started	Jul 25 05:09:26 PM PDT 24
Finished	Jul 25 05:14:13 PM PDT 24
Peak memory	289612 kb
Host	smart-e78943a4-1cc9-4998-b68a-a9eb58a6851f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477088769 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.477088769
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.2383765345
Short name	T448
Test name
Test status
Simulation time	37065000 ps
CPU time	113.02 seconds
Started	Jul 25 05:09:29 PM PDT 24
Finished	Jul 25 05:11:22 PM PDT 24
Peak memory	260732 kb
Host	smart-fce198a4-86c5-409f-b146-805502be639c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383765345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.2383765345
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict.729975060
Short name	T1110
Test name
Test status
Simulation time	33508300 ps
CPU time	31.85 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:09:59 PM PDT 24
Peak memory	273276 kb
Host	smart-d04eeaab-c230-4ee4-a2c4-7878b0f1d391
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729975060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_rw_evict.729975060
Directory	/workspace/31.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.525541100
Short name	T962
Test name
Test status
Simulation time	233513600 ps
CPU time	30.72 seconds
Started	Jul 25 05:09:29 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	275284 kb
Host	smart-ab1b6d4a-29c3-4832-b6e4-b671fbcf5ea8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525541100 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.525541100
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.3054523099
Short name	T408
Test name
Test status
Simulation time	2604530600 ps
CPU time	68.52 seconds
Started	Jul 25 05:09:28 PM PDT 24
Finished	Jul 25 05:10:37 PM PDT 24
Peak memory	263016 kb
Host	smart-9d7635fc-3089-4900-9306-62be55096b6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054523099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3054523099
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.2498613137
Short name	T846
Test name
Test status
Simulation time	60675300 ps
CPU time	53.12 seconds
Started	Jul 25 05:09:26 PM PDT 24
Finished	Jul 25 05:10:20 PM PDT 24
Peak memory	270932 kb
Host	smart-d8857eb9-f81b-4c12-8c55-4561c13bd740
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498613137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2498613137
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.2462741402
Short name	T867
Test name
Test status
Simulation time	32890900 ps
CPU time	13.57 seconds
Started	Jul 25 05:09:39 PM PDT 24
Finished	Jul 25 05:09:53 PM PDT 24
Peak memory	258112 kb
Host	smart-9ff2cdfd-364a-4b8d-af52-455fb23a0858
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462741402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test. 2462741402
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.2298768810
Short name	T466
Test name
Test status
Simulation time	14588600 ps
CPU time	15.85 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:09:54 PM PDT 24
Peak memory	284052 kb
Host	smart-b1026711-1ce4-4c53-a6ca-013f32f976ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298768810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2298768810
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.600177394
Short name	T106
Test name
Test status
Simulation time	12250600 ps
CPU time	21.4 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:09:59 PM PDT 24
Peak memory	273508 kb
Host	smart-294f9779-687f-426b-83f2-b714bcb9a9b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600177394 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.600177394
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.969831674
Short name	T895
Test name
Test status
Simulation time	9243458900 ps
CPU time	77.1 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:10:44 PM PDT 24
Peak memory	263056 kb
Host	smart-eb835916-82b6-4335-b6c3-e851799bd892
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969831674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h w_sec_otp.969831674
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.2647357470
Short name	T553
Test name
Test status
Simulation time	2988647800 ps
CPU time	178.49 seconds
Started	Jul 25 05:09:27 PM PDT 24
Finished	Jul 25 05:12:26 PM PDT 24
Peak memory	290572 kb
Host	smart-7257c649-5631-4fa6-926f-6d3e8b8943c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647357470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.2647357470
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1379020100
Short name	T98
Test name
Test status
Simulation time	13069744300 ps
CPU time	287.04 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:14:25 PM PDT 24
Peak memory	292612 kb
Host	smart-adc85985-3038-4db6-9f89-762bf82f67b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379020100 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1379020100
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.281464840
Short name	T922
Test name
Test status
Simulation time	40404800 ps
CPU time	110.69 seconds
Started	Jul 25 05:09:26 PM PDT 24
Finished	Jul 25 05:11:17 PM PDT 24
Peak memory	263732 kb
Host	smart-1df64580-71ad-4c0b-9c8a-959283b5a936
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281464840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot p_reset.281464840
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.2667998054
Short name	T452
Test name
Test status
Simulation time	80527500 ps
CPU time	31.62 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:10:09 PM PDT 24
Peak memory	275300 kb
Host	smart-758cca96-e4a1-43b7-8740-8948e8267ef8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667998054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.2667998054
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.4161021291
Short name	T333
Test name
Test status
Simulation time	91693400 ps
CPU time	31.24 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:10:08 PM PDT 24
Peak memory	275380 kb
Host	smart-74eabeb0-9e07-4d1f-9e3b-2bf110e3901e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161021291 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.4161021291
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.1879938879
Short name	T596
Test name
Test status
Simulation time	1143577300 ps
CPU time	68.23 seconds
Started	Jul 25 05:09:41 PM PDT 24
Finished	Jul 25 05:10:49 PM PDT 24
Peak memory	263516 kb
Host	smart-12d9ad05-ccc7-429a-b676-12f4a006a463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879938879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1879938879
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.3014927235
Short name	T148
Test name
Test status
Simulation time	14924400 ps
CPU time	76.92 seconds
Started	Jul 25 05:09:28 PM PDT 24
Finished	Jul 25 05:10:45 PM PDT 24
Peak memory	276496 kb
Host	smart-e39561dd-1d3e-4453-abd8-efabdb620275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014927235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3014927235
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.3996913859
Short name	T223
Test name
Test status
Simulation time	85689000 ps
CPU time	13.63 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:09:50 PM PDT 24
Peak memory	257964 kb
Host	smart-d3d45359-de4a-4aad-9aca-4d8406b057d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996913859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 3996913859
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.3154785984
Short name	T427
Test name
Test status
Simulation time	52870700 ps
CPU time	16.15 seconds
Started	Jul 25 05:09:39 PM PDT 24
Finished	Jul 25 05:09:55 PM PDT 24
Peak memory	283992 kb
Host	smart-f0b6e402-d97b-4c5b-8b5d-d3425d21718f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154785984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3154785984
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.1671798252
Short name	T850
Test name
Test status
Simulation time	10939100 ps
CPU time	22.11 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:10:01 PM PDT 24
Peak memory	273344 kb
Host	smart-799d30e6-3b55-43c9-9c44-8ccd1a6d6dad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671798252 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.1671798252
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.470846578
Short name	T125
Test name
Test status
Simulation time	2996418000 ps
CPU time	108.81 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:11:26 PM PDT 24
Peak memory	260776 kb
Host	smart-b6e9014b-cc4d-4f70-86fa-ed23491f52ab
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470846578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_h w_sec_otp.470846578
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.3184714771
Short name	T898
Test name
Test status
Simulation time	763593200 ps
CPU time	140.57 seconds
Started	Jul 25 05:09:39 PM PDT 24
Finished	Jul 25 05:11:59 PM PDT 24
Peak memory	293736 kb
Host	smart-aba9c318-0957-4257-b78c-717052cc4b94
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184714771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.3184714771
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.203480295
Short name	T485
Test name
Test status
Simulation time	23892256300 ps
CPU time	129.58 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:11:47 PM PDT 24
Peak memory	292340 kb
Host	smart-e643006d-6d4b-47a5-b27d-d356abcd7959
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203480295 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.203480295
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.1051017360
Short name	T635
Test name
Test status
Simulation time	162402100 ps
CPU time	130.99 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:11:49 PM PDT 24
Peak memory	259872 kb
Host	smart-a9acf48b-e255-46cb-800e-914807399d8a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051017360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.1051017360
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.4232968527
Short name	T301
Test name
Test status
Simulation time	73832200 ps
CPU time	30.92 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:10:10 PM PDT 24
Peak memory	275340 kb
Host	smart-f9665663-c2d1-4cec-85f6-215ef1566c00
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232968527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.4232968527
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2133533159
Short name	T824
Test name
Test status
Simulation time	28934700 ps
CPU time	31.36 seconds
Started	Jul 25 05:09:39 PM PDT 24
Finished	Jul 25 05:10:10 PM PDT 24
Peak memory	275336 kb
Host	smart-c387bcf0-f588-4cd3-bd1f-7d455ac0f6dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133533159 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2133533159
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.1298750197
Short name	T828
Test name
Test status
Simulation time	5936939000 ps
CPU time	68.4 seconds
Started	Jul 25 05:09:43 PM PDT 24
Finished	Jul 25 05:10:51 PM PDT 24
Peak memory	263488 kb
Host	smart-01b0e65f-2063-4f28-85b4-435af6311835
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298750197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1298750197
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.1669209765
Short name	T599
Test name
Test status
Simulation time	19636600 ps
CPU time	50.01 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:10:27 PM PDT 24
Peak memory	271044 kb
Host	smart-b022920f-f89b-477a-a909-bd41ae01d929
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669209765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1669209765
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.149674001
Short name	T432
Test name
Test status
Simulation time	83575000 ps
CPU time	13.74 seconds
Started	Jul 25 05:09:39 PM PDT 24
Finished	Jul 25 05:09:52 PM PDT 24
Peak memory	257884 kb
Host	smart-8e101e52-6bd1-4746-a227-7886747a39e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149674001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.149674001
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.4012740547
Short name	T741
Test name
Test status
Simulation time	17155600 ps
CPU time	16.14 seconds
Started	Jul 25 05:09:43 PM PDT 24
Finished	Jul 25 05:09:59 PM PDT 24
Peak memory	284132 kb
Host	smart-da3f311c-22db-4870-a944-32fcb53e8e9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012740547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.4012740547
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.1997773459
Short name	T361
Test name
Test status
Simulation time	14996800 ps
CPU time	22.37 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:10:00 PM PDT 24
Peak memory	273148 kb
Host	smart-71ebb617-c0e3-498a-a984-d2e6f84da605
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997773459 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.1997773459
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3434804228
Short name	T995
Test name
Test status
Simulation time	1128261600 ps
CPU time	40.6 seconds
Started	Jul 25 05:09:40 PM PDT 24
Finished	Jul 25 05:10:21 PM PDT 24
Peak memory	262820 kb
Host	smart-57550897-f285-4bb7-8e01-03d72ac4d434
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434804228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ hw_sec_otp.3434804228
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.884746852
Short name	T323
Test name
Test status
Simulation time	3337225900 ps
CPU time	212.6 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:13:10 PM PDT 24
Peak memory	284436 kb
Host	smart-f2768178-a71b-498c-b2ea-55f85ba07420
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884746852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas h_ctrl_intr_rd.884746852
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.203023513
Short name	T431
Test name
Test status
Simulation time	5533524300 ps
CPU time	123.82 seconds
Started	Jul 25 05:09:36 PM PDT 24
Finished	Jul 25 05:11:40 PM PDT 24
Peak memory	292728 kb
Host	smart-c01b9543-debd-4107-83c8-9c599b7b599b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203023513 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.203023513
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.580007653
Short name	T999
Test name
Test status
Simulation time	47897500 ps
CPU time	112.25 seconds
Started	Jul 25 05:09:39 PM PDT 24
Finished	Jul 25 05:11:31 PM PDT 24
Peak memory	259800 kb
Host	smart-d9947a03-51a2-400a-8a83-3f5405981356
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580007653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ot p_reset.580007653
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict.2160597728
Short name	T61
Test name
Test status
Simulation time	86638900 ps
CPU time	28 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:10:07 PM PDT 24
Peak memory	268172 kb
Host	smart-61860941-ad4c-4420-b61b-a2f05a1413ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160597728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl ash_ctrl_rw_evict.2160597728
Directory	/workspace/34.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2741948851
Short name	T989
Test name
Test status
Simulation time	67501900 ps
CPU time	30.38 seconds
Started	Jul 25 05:09:37 PM PDT 24
Finished	Jul 25 05:10:07 PM PDT 24
Peak memory	268184 kb
Host	smart-ca9b0a58-1665-44f5-9a70-795144d3e84a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741948851 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2741948851
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.1029605484
Short name	T402
Test name
Test status
Simulation time	1516179200 ps
CPU time	56.17 seconds
Started	Jul 25 05:09:41 PM PDT 24
Finished	Jul 25 05:10:38 PM PDT 24
Peak memory	263384 kb
Host	smart-b2d4d3ab-e59f-46da-b0f8-27e75a50246a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029605484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1029605484
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.1554271439
Short name	T1109
Test name
Test status
Simulation time	131570800 ps
CPU time	129.55 seconds
Started	Jul 25 05:09:38 PM PDT 24
Finished	Jul 25 05:11:48 PM PDT 24
Peak memory	276020 kb
Host	smart-dad99520-e78b-402f-822c-3154f9b5f415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554271439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1554271439
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.3887924196
Short name	T1083
Test name
Test status
Simulation time	438247800 ps
CPU time	14.34 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:10:02 PM PDT 24
Peak memory	257816 kb
Host	smart-023191c9-e8ca-4b68-9f41-f77856812df0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887924196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 3887924196
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.1586972845
Short name	T996
Test name
Test status
Simulation time	7049911700 ps
CPU time	216.66 seconds
Started	Jul 25 05:09:49 PM PDT 24
Finished	Jul 25 05:13:26 PM PDT 24
Peak memory	284552 kb
Host	smart-475240ae-1537-4842-bb21-1b66b20b0f2a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586972845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.1586972845
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.3886661845
Short name	T742
Test name
Test status
Simulation time	29660600 ps
CPU time	30.93 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:10:19 PM PDT 24
Peak memory	272856 kb
Host	smart-c25993cd-2cc7-401d-bf3f-96318fc97e67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886661845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.3886661845
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1319949232
Short name	T343
Test name
Test status
Simulation time	71833500 ps
CPU time	30.83 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:10:18 PM PDT 24
Peak memory	273264 kb
Host	smart-6d42dde1-a0f2-49d2-9886-9edda2883a1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319949232 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1319949232
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.883719630
Short name	T855
Test name
Test status
Simulation time	8718445400 ps
CPU time	69.77 seconds
Started	Jul 25 05:09:52 PM PDT 24
Finished	Jul 25 05:11:02 PM PDT 24
Peak memory	263548 kb
Host	smart-f6b09135-d684-4469-a01e-74f617348f6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883719630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.883719630
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.696967842
Short name	T757
Test name
Test status
Simulation time	21300800 ps
CPU time	121.35 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:11:49 PM PDT 24
Peak memory	277600 kb
Host	smart-3b62a81e-d81d-4ead-a7ea-bb25db241b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696967842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.696967842
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.1170098086
Short name	T921
Test name
Test status
Simulation time	105952700 ps
CPU time	14.08 seconds
Started	Jul 25 05:09:52 PM PDT 24
Finished	Jul 25 05:10:06 PM PDT 24
Peak memory	257808 kb
Host	smart-b43fb9fa-0253-40d0-9e8b-9b469edb25c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170098086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test. 1170098086
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.3904551838
Short name	T837
Test name
Test status
Simulation time	26154400 ps
CPU time	13.82 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:10:01 PM PDT 24
Peak memory	282752 kb
Host	smart-e3028170-a867-4e41-b3a3-fd17c01060e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904551838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3904551838
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.1132453648
Short name	T363
Test name
Test status
Simulation time	28572600 ps
CPU time	22.25 seconds
Started	Jul 25 05:09:49 PM PDT 24
Finished	Jul 25 05:10:11 PM PDT 24
Peak memory	273204 kb
Host	smart-1035ddd2-f390-4f25-8c9c-f0cb375755bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132453648 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.1132453648
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1327903450
Short name	T736
Test name
Test status
Simulation time	15807811500 ps
CPU time	95.18 seconds
Started	Jul 25 05:09:49 PM PDT 24
Finished	Jul 25 05:11:24 PM PDT 24
Peak memory	260260 kb
Host	smart-204fa74d-0cf6-402c-bc0e-0762979a9174
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327903450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ hw_sec_otp.1327903450
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.1659702761
Short name	T740
Test name
Test status
Simulation time	1452854300 ps
CPU time	219.69 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:13:27 PM PDT 24
Peak memory	284572 kb
Host	smart-0d9d9038-1193-4480-9ad8-730e9aafee15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659702761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.1659702761
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3913218190
Short name	T1074
Test name
Test status
Simulation time	12479335400 ps
CPU time	269.1 seconds
Started	Jul 25 05:09:49 PM PDT 24
Finished	Jul 25 05:14:18 PM PDT 24
Peak memory	284608 kb
Host	smart-d2a46fcb-ee82-4603-8eff-14042bb14202
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913218190 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3913218190
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.3055854447
Short name	T1058
Test name
Test status
Simulation time	301692400 ps
CPU time	109.56 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:11:36 PM PDT 24
Peak memory	265032 kb
Host	smart-db2cfbb1-614c-4aef-9c3e-2a8cb5e20b77
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055854447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.3055854447
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.449852793
Short name	T1
Test name
Test status
Simulation time	65410400 ps
CPU time	31.77 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:10:20 PM PDT 24
Peak memory	275300 kb
Host	smart-e4d24f5e-fc0f-4c43-b5b3-34b73f063474
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449852793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_rw_evict.449852793
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2317628536
Short name	T552
Test name
Test status
Simulation time	27592800 ps
CPU time	31.49 seconds
Started	Jul 25 05:09:52 PM PDT 24
Finished	Jul 25 05:10:23 PM PDT 24
Peak memory	275332 kb
Host	smart-21c8a2bb-9f54-4486-9d41-bf13b4586792
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317628536 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2317628536
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.2985953919
Short name	T160
Test name
Test status
Simulation time	1537797400 ps
CPU time	61.21 seconds
Started	Jul 25 05:09:46 PM PDT 24
Finished	Jul 25 05:10:48 PM PDT 24
Peak memory	264636 kb
Host	smart-7cf5d821-1495-4c3e-b80f-03924b7288ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985953919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2985953919
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.3764877424
Short name	T973
Test name
Test status
Simulation time	17459400 ps
CPU time	122.04 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:11:50 PM PDT 24
Peak memory	277364 kb
Host	smart-72bbd107-8ee6-4cb0-a6d9-7205a7127a8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764877424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3764877424
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.3092926826
Short name	T439
Test name
Test status
Simulation time	31150900 ps
CPU time	13.67 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:10:15 PM PDT 24
Peak memory	264928 kb
Host	smart-c3ef7b3f-0956-4f71-8443-8c73346939e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092926826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 3092926826
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.480408069
Short name	T449
Test name
Test status
Simulation time	15097500 ps
CPU time	13.41 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:14 PM PDT 24
Peak memory	284168 kb
Host	smart-22c0dfec-678a-4ddb-8695-af47534a8b37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480408069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.480408069
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.93947367
Short name	T189
Test name
Test status
Simulation time	15709100 ps
CPU time	21.67 seconds
Started	Jul 25 05:09:51 PM PDT 24
Finished	Jul 25 05:10:13 PM PDT 24
Peak memory	273268 kb
Host	smart-ab5674a3-6104-4319-9dfa-7f0fe0ee0da1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93947367 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 37.flash_ctrl_disable.93947367
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2223916335
Short name	T1082
Test name
Test status
Simulation time	12707719500 ps
CPU time	133.28 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:12:01 PM PDT 24
Peak memory	260748 kb
Host	smart-99ac5273-c0cd-4c77-a96a-569903f414b5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223916335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ hw_sec_otp.2223916335
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.3092472048
Short name	T320
Test name
Test status
Simulation time	684274000 ps
CPU time	150.09 seconds
Started	Jul 25 05:09:49 PM PDT 24
Finished	Jul 25 05:12:19 PM PDT 24
Peak memory	297272 kb
Host	smart-bbdaf4aa-9847-4826-8f17-6b65837f1887
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092472048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.3092472048
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.171698289
Short name	T860
Test name
Test status
Simulation time	51561383900 ps
CPU time	314.2 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:15:03 PM PDT 24
Peak memory	290696 kb
Host	smart-655a0c20-f99b-4af6-84a5-0c979aa507b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171698289 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.171698289
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.654021371
Short name	T518
Test name
Test status
Simulation time	137478100 ps
CPU time	111.77 seconds
Started	Jul 25 05:09:48 PM PDT 24
Finished	Jul 25 05:11:40 PM PDT 24
Peak memory	260692 kb
Host	smart-8c4471fb-118f-4f90-a810-a63bbf0a7993
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654021371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ot p_reset.654021371
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3678453893
Short name	T1103
Test name
Test status
Simulation time	67877600 ps
CPU time	28.05 seconds
Started	Jul 25 05:09:47 PM PDT 24
Finished	Jul 25 05:10:16 PM PDT 24
Peak memory	275352 kb
Host	smart-c92e1f31-0d50-4188-9269-18bddc0c0cd9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678453893 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3678453893
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.3373196807
Short name	T413
Test name
Test status
Simulation time	1785889300 ps
CPU time	57.95 seconds
Started	Jul 25 05:09:59 PM PDT 24
Finished	Jul 25 05:10:57 PM PDT 24
Peak memory	263440 kb
Host	smart-5d524d24-aaa1-4149-9eb4-32c97ddb27eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373196807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3373196807
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.3051910854
Short name	T705
Test name
Test status
Simulation time	107617700 ps
CPU time	145.21 seconds
Started	Jul 25 05:09:50 PM PDT 24
Finished	Jul 25 05:12:15 PM PDT 24
Peak memory	280028 kb
Host	smart-853cbc34-bc85-4517-a40c-8fb4f8d0dbce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051910854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3051910854
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.1259423784
Short name	T514
Test name
Test status
Simulation time	133586700 ps
CPU time	13.71 seconds
Started	Jul 25 05:10:02 PM PDT 24
Finished	Jul 25 05:10:15 PM PDT 24
Peak memory	257852 kb
Host	smart-372973c1-7dd5-418b-a583-908c05165514
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259423784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 1259423784
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.3516467232
Short name	T875
Test name
Test status
Simulation time	142344400 ps
CPU time	15.66 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:16 PM PDT 24
Peak memory	284196 kb
Host	smart-b38aaaf4-8dff-4126-9918-6167b37e4db0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516467232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3516467232
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.1225123452
Short name	T809
Test name
Test status
Simulation time	10285000 ps
CPU time	20.79 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:21 PM PDT 24
Peak memory	273236 kb
Host	smart-631c46a9-ca98-46d8-b10d-cb001e3b2466
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225123452 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.1225123452
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.3712999063
Short name	T1029
Test name
Test status
Simulation time	4275615600 ps
CPU time	51.85 seconds
Started	Jul 25 05:10:02 PM PDT 24
Finished	Jul 25 05:10:54 PM PDT 24
Peak memory	260444 kb
Host	smart-4476c961-ef40-4c79-bd3e-185931c2ae22
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712999063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.3712999063
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.295639120
Short name	T923
Test name
Test status
Simulation time	2916606900 ps
CPU time	157.61 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:12:38 PM PDT 24
Peak memory	294936 kb
Host	smart-f6ad018d-1072-4a57-ba8b-42d45b35ac60
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295639120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas h_ctrl_intr_rd.295639120
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1491076061
Short name	T763
Test name
Test status
Simulation time	5774588400 ps
CPU time	142.15 seconds
Started	Jul 25 05:09:59 PM PDT 24
Finished	Jul 25 05:12:22 PM PDT 24
Peak memory	292336 kb
Host	smart-f086d14a-8faa-4eb9-a7cb-02fbe7869f35
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491076061 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1491076061
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.2690449830
Short name	T605
Test name
Test status
Simulation time	76495000 ps
CPU time	134.4 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:12:16 PM PDT 24
Peak memory	259960 kb
Host	smart-01ec78d2-9614-4866-b736-f88910c40a8f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690449830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o tp_reset.2690449830
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.4275815507
Short name	T766
Test name
Test status
Simulation time	30438800 ps
CPU time	31.4 seconds
Started	Jul 25 05:10:03 PM PDT 24
Finished	Jul 25 05:10:34 PM PDT 24
Peak memory	275328 kb
Host	smart-2e787e8d-f202-4067-a202-571c3cb17170
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275815507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl ash_ctrl_rw_evict.4275815507
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.644026107
Short name	T966
Test name
Test status
Simulation time	62128300 ps
CPU time	31.38 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:32 PM PDT 24
Peak memory	268148 kb
Host	smart-a7f8aa04-557a-4319-a62a-bae4e45bbb14
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644026107 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.644026107
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.2266062717
Short name	T396
Test name
Test status
Simulation time	7358045000 ps
CPU time	63.32 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:11:04 PM PDT 24
Peak memory	262972 kb
Host	smart-b7f3010d-fe7f-4e2f-b471-c927f773301d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266062717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2266062717
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.3868766737
Short name	T1048
Test name
Test status
Simulation time	117729400 ps
CPU time	51.56 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:51 PM PDT 24
Peak memory	271108 kb
Host	smart-7a028a92-5c66-45a8-b7ed-e1b3a4059612
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3868766737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3868766737
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.2967220512
Short name	T564
Test name
Test status
Simulation time	73555300 ps
CPU time	14.39 seconds
Started	Jul 25 05:10:02 PM PDT 24
Finished	Jul 25 05:10:16 PM PDT 24
Peak memory	264908 kb
Host	smart-92f42461-8063-42b8-a436-86f931ce4db4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967220512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 2967220512
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.2005001527
Short name	T510
Test name
Test status
Simulation time	16975100 ps
CPU time	15.93 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:16 PM PDT 24
Peak memory	282848 kb
Host	smart-b5e62243-e43d-43a5-b765-5f862c8922dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005001527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2005001527
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.1334993159
Short name	T190
Test name
Test status
Simulation time	17602400 ps
CPU time	20.85 seconds
Started	Jul 25 05:10:03 PM PDT 24
Finished	Jul 25 05:10:24 PM PDT 24
Peak memory	266144 kb
Host	smart-be6e1ad9-69a1-47c0-b4c5-100deab69a3b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334993159 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.1334993159
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.998425763
Short name	T727
Test name
Test status
Simulation time	2173934900 ps
CPU time	94.92 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:11:36 PM PDT 24
Peak memory	263132 kb
Host	smart-cfe7e056-8d67-4d1d-8c88-b55913827833
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998425763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h w_sec_otp.998425763
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.1577449434
Short name	T624
Test name
Test status
Simulation time	4259973400 ps
CPU time	134.58 seconds
Started	Jul 25 05:10:02 PM PDT 24
Finished	Jul 25 05:12:17 PM PDT 24
Peak memory	284928 kb
Host	smart-cacec77f-fe52-4336-9bcf-3379e4313a1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577449434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.1577449434
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.729639721
Short name	T33
Test name
Test status
Simulation time	7929639100 ps
CPU time	132.68 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:12:13 PM PDT 24
Peak memory	289728 kb
Host	smart-6bccdca2-0713-40d0-ba09-459365f981f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729639721 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.729639721
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.3916471981
Short name	T655
Test name
Test status
Simulation time	38950600 ps
CPU time	108.67 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:11:50 PM PDT 24
Peak memory	264060 kb
Host	smart-8c0a49dd-c333-4b7e-8cd8-2b6d3f2df181
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916471981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o tp_reset.3916471981
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1615186886
Short name	T963
Test name
Test status
Simulation time	27724200 ps
CPU time	30.52 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:10:31 PM PDT 24
Peak memory	267148 kb
Host	smart-bf784f88-0dac-4a1a-a6f5-9387a3804021
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615186886 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1615186886
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.3192476461
Short name	T398
Test name
Test status
Simulation time	2636222800 ps
CPU time	56.8 seconds
Started	Jul 25 05:10:02 PM PDT 24
Finished	Jul 25 05:10:59 PM PDT 24
Peak memory	262860 kb
Host	smart-917de4b9-dc44-49d5-ad11-ee5c5c7c76f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192476461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.3192476461
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.1901764200
Short name	T365
Test name
Test status
Simulation time	189558900 ps
CPU time	100.44 seconds
Started	Jul 25 05:10:02 PM PDT 24
Finished	Jul 25 05:11:43 PM PDT 24
Peak memory	275988 kb
Host	smart-3486674e-227d-45d9-9d05-79f5b05e5967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901764200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1901764200
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.3623691038
Short name	T803
Test name
Test status
Simulation time	152166000 ps
CPU time	14.04 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:06:58 PM PDT 24
Peak memory	264760 kb
Host	smart-a853c22e-3ad1-42ad-8807-2b5416da7151
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623691038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3 623691038
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.871356802
Short name	T1087
Test name
Test status
Simulation time	45095200 ps
CPU time	13.26 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:06:54 PM PDT 24
Peak memory	284192 kb
Host	smart-18249434-f29c-4f90-b47d-34ee88089440
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871356802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.871356802
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.360922193
Short name	T1043
Test name
Test status
Simulation time	27344500 ps
CPU time	21.78 seconds
Started	Jul 25 05:06:49 PM PDT 24
Finished	Jul 25 05:07:11 PM PDT 24
Peak memory	273256 kb
Host	smart-66157cba-2324-4fab-ad39-6cb6d6b416b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360922193 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.360922193
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.4255453480
Short name	T57
Test name
Test status
Simulation time	14583390600 ps
CPU time	440.66 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:13:52 PM PDT 24
Peak memory	263108 kb
Host	smart-fb0561cb-a269-4548-aaae-f196de141c67
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4255453480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.4255453480
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.1937000861
Short name	T730
Test name
Test status
Simulation time	33256609000 ps
CPU time	2356.42 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:45:58 PM PDT 24
Peak memory	264660 kb
Host	smart-9a9b3229-f5e1-40e7-9f45-d3588ce28a97
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1937000861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.1937000861
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.1562028829
Short name	T97
Test name
Test status
Simulation time	1082907600 ps
CPU time	2163.43 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:42:47 PM PDT 24
Peak memory	264156 kb
Host	smart-8f051ebf-f742-47cf-bab1-f11740bb2269
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562028829 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1562028829
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.3940126789
Short name	T281
Test name
Test status
Simulation time	1137851900 ps
CPU time	757.1 seconds
Started	Jul 25 05:06:40 PM PDT 24
Finished	Jul 25 05:19:17 PM PDT 24
Peak memory	273776 kb
Host	smart-a40225ec-30ab-4242-92f7-30815d993d77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940126789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3940126789
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.2303464756
Short name	T48
Test name
Test status
Simulation time	603549200 ps
CPU time	26.35 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:06:59 PM PDT 24
Peak memory	263300 kb
Host	smart-fd65adba-9efb-48ee-8038-4e15daed6b48
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303464756 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2303464756
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.3816085374
Short name	T93
Test name
Test status
Simulation time	1318929800 ps
CPU time	43.06 seconds
Started	Jul 25 05:06:49 PM PDT 24
Finished	Jul 25 05:07:32 PM PDT 24
Peak memory	264560 kb
Host	smart-9e3d6ad9-5a48-4634-a01c-83804b8d4bad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816085374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.3816085374
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.2245676001
Short name	T131
Test name
Test status
Simulation time	372751164600 ps
CPU time	2702.69 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:51:45 PM PDT 24
Peak memory	265116 kb
Host	smart-edf9e0e8-fdf9-4079-94dc-bf27ad6a19cc
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245676001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.2245676001
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.1548557260
Short name	T845
Test name
Test status
Simulation time	68936600 ps
CPU time	59.68 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:07:32 PM PDT 24
Peak memory	265052 kb
Host	smart-a7ff77c5-9074-49b6-a5a9-240faa051198
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1548557260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1548557260
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.975208721
Short name	T709
Test name
Test status
Simulation time	10011816600 ps
CPU time	130.93 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:08:55 PM PDT 24
Peak memory	356676 kb
Host	smart-dedb9298-ee6f-474a-8024-a1af8ada31cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975208721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.975208721
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3078140195
Short name	T269
Test name
Test status
Simulation time	26448800 ps
CPU time	13.49 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:06:57 PM PDT 24
Peak memory	264752 kb
Host	smart-219a5edd-1748-465c-83b5-db2a575c5cfe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078140195 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3078140195
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1143739275
Short name	T623
Test name
Test status
Simulation time	80141025400 ps
CPU time	834.47 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:20:28 PM PDT 24
Peak memory	264140 kb
Host	smart-68d5eb05-f280-4ab3-b41e-0f893ea61e1c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143739275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.1143739275
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.473010303
Short name	T839
Test name
Test status
Simulation time	13785377600 ps
CPU time	110.82 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:08:23 PM PDT 24
Peak memory	260436 kb
Host	smart-5b037b97-9dcc-4ea2-b573-a680b027e1f4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473010303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw _sec_otp.473010303
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.4087427562
Short name	T931
Test name
Test status
Simulation time	3538094400 ps
CPU time	596.16 seconds
Started	Jul 25 05:06:40 PM PDT 24
Finished	Jul 25 05:16:36 PM PDT 24
Peak memory	324824 kb
Host	smart-04b90da5-fbf3-4e5f-abfc-fd2339fd1a9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087427562 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.4087427562
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2072191129
Short name	T560
Test name
Test status
Simulation time	5785687500 ps
CPU time	142.69 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:09:04 PM PDT 24
Peak memory	292708 kb
Host	smart-7bd4104d-bdf3-4329-9770-218670459820
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072191129 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2072191129
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.1135777236
Short name	T888
Test name
Test status
Simulation time	24421400100 ps
CPU time	69.65 seconds
Started	Jul 25 05:06:39 PM PDT 24
Finished	Jul 25 05:07:49 PM PDT 24
Peak memory	265056 kb
Host	smart-4937eb4d-373d-4a2f-91cb-e07635d7b428
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135777236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_wr.1135777236
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1181123417
Short name	T1016
Test name
Test status
Simulation time	18655618800 ps
CPU time	157.31 seconds
Started	Jul 25 05:06:42 PM PDT 24
Finished	Jul 25 05:09:20 PM PDT 24
Peak memory	264916 kb
Host	smart-629457ee-993f-4407-a640-0546a472d710
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118 1123417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1181123417
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.2301451274
Short name	T723
Test name
Test status
Simulation time	3362870100 ps
CPU time	66.42 seconds
Started	Jul 25 05:06:45 PM PDT 24
Finished	Jul 25 05:07:51 PM PDT 24
Peak memory	260368 kb
Host	smart-6db0d3a1-9782-48d7-9fa3-9eda6c2da41f
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301451274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2301451274
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.4076524561
Short name	T1055
Test name
Test status
Simulation time	16198500 ps
CPU time	13.5 seconds
Started	Jul 25 05:06:45 PM PDT 24
Finished	Jul 25 05:06:58 PM PDT 24
Peak memory	264868 kb
Host	smart-e7cc3d46-9a76-48b7-9a9f-15cdfae3f2aa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076524561 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.4076524561
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.1609423367
Short name	T133
Test name
Test status
Simulation time	8666843900 ps
CPU time	273.17 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:11:05 PM PDT 24
Peak memory	274568 kb
Host	smart-4cc311c7-5878-45e2-bb12-3bd6ef3d4d86
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609423367 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.1609423367
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.2996461380
Short name	T587
Test name
Test status
Simulation time	40763700 ps
CPU time	133.46 seconds
Started	Jul 25 05:06:35 PM PDT 24
Finished	Jul 25 05:08:48 PM PDT 24
Peak memory	260056 kb
Host	smart-1d007b7e-1410-4104-81ac-184c13e7cfad
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996461380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot p_reset.2996461380
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.2658541363
Short name	T649
Test name
Test status
Simulation time	2490331700 ps
CPU time	167.69 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	290224 kb
Host	smart-a61a2e8e-a833-419d-bd77-5213c38d8ddb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658541363 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2658541363
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.2451019949
Short name	T444
Test name
Test status
Simulation time	263950100 ps
CPU time	311.24 seconds
Started	Jul 25 05:06:32 PM PDT 24
Finished	Jul 25 05:11:44 PM PDT 24
Peak memory	262848 kb
Host	smart-ee8c0ade-e539-40df-8993-0a4e73dd5dd8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2451019949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2451019949
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2505288857
Short name	T192
Test name
Test status
Simulation time	15299900 ps
CPU time	13.67 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:06:57 PM PDT 24
Peak memory	262368 kb
Host	smart-4126c929-16ea-4e69-8251-1b4358e33991
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505288857 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2505288857
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.3072217924
Short name	T909
Test name
Test status
Simulation time	18116200 ps
CPU time	13.83 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:06:57 PM PDT 24
Peak memory	264820 kb
Host	smart-183710eb-44fc-499a-a44f-41422aa56867
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072217924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.flash_ctrl_prog_reset.3072217924
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.2797502519
Short name	T733
Test name
Test status
Simulation time	76737800 ps
CPU time	648.57 seconds
Started	Jul 25 05:06:33 PM PDT 24
Finished	Jul 25 05:17:22 PM PDT 24
Peak memory	285328 kb
Host	smart-5a8ef0ec-1ccb-4938-88eb-ac8b92a12c86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797502519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2797502519
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2688323082
Short name	T737
Test name
Test status
Simulation time	52225200 ps
CPU time	100.81 seconds
Started	Jul 25 05:06:35 PM PDT 24
Finished	Jul 25 05:08:16 PM PDT 24
Peak memory	262456 kb
Host	smart-cad6bb0d-c9cd-4520-8c3e-5fc5b6ccbf52
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2688323082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2688323082
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.3779762982
Short name	T1028
Test name
Test status
Simulation time	140017500 ps
CPU time	34.12 seconds
Started	Jul 25 05:06:42 PM PDT 24
Finished	Jul 25 05:07:16 PM PDT 24
Peak memory	273292 kb
Host	smart-e6ba9e7c-56b9-4a13-a87b-0556c09c2f61
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779762982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_re_evict.3779762982
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.4260507048
Short name	T204
Test name
Test status
Simulation time	64909800 ps
CPU time	22.67 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:07:04 PM PDT 24
Peak memory	265096 kb
Host	smart-cf124561-4254-436f-8c49-2fefe0850c96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260507048 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.4260507048
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.1922845819
Short name	T366
Test name
Test status
Simulation time	22950300 ps
CPU time	21.01 seconds
Started	Jul 25 05:06:46 PM PDT 24
Finished	Jul 25 05:07:07 PM PDT 24
Peak memory	265012 kb
Host	smart-56cacde6-cd2c-42c2-8497-0ed5343a5b1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922845819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_read_word_sweep_serr.1922845819
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.2136321296
Short name	T574
Test name
Test status
Simulation time	1037501600 ps
CPU time	115.02 seconds
Started	Jul 25 05:06:39 PM PDT 24
Finished	Jul 25 05:08:35 PM PDT 24
Peak memory	281528 kb
Host	smart-34166b7f-2a7e-4e83-93e7-29d66b792719
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136321296 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_ro.2136321296
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.4111134088
Short name	T1019
Test name
Test status
Simulation time	3384065500 ps
CPU time	179.23 seconds
Started	Jul 25 05:06:40 PM PDT 24
Finished	Jul 25 05:09:40 PM PDT 24
Peak memory	282620 kb
Host	smart-0fe3cf3d-dc79-4e41-8a53-165d892c32e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4111134088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.4111134088
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.1716063724
Short name	T914
Test name
Test status
Simulation time	2442430900 ps
CPU time	130.58 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:08:55 PM PDT 24
Peak memory	295016 kb
Host	smart-f171ada1-eed6-47d5-a041-2f665a4f6789
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716063724 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1716063724
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.2538014102
Short name	T765
Test name
Test status
Simulation time	7856715300 ps
CPU time	653.16 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:17:34 PM PDT 24
Peak memory	314292 kb
Host	smart-ae2d86bf-7ab4-4074-bd90-15f4019c07b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538014102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.flash_ctrl_rw.2538014102
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.227017987
Short name	T337
Test name
Test status
Simulation time	30963600 ps
CPU time	31.54 seconds
Started	Jul 25 05:06:43 PM PDT 24
Finished	Jul 25 05:07:14 PM PDT 24
Peak memory	275248 kb
Host	smart-b5813ac9-0d47-4352-bb31-62ae0bb875ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227017987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_rw_evict.227017987
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3072841704
Short name	T1035
Test name
Test status
Simulation time	51974100 ps
CPU time	30.13 seconds
Started	Jul 25 05:06:42 PM PDT 24
Finished	Jul 25 05:07:12 PM PDT 24
Peak memory	273360 kb
Host	smart-de676fe4-fb08-4efe-8817-41e7a1aae24e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072841704 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3072841704
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.3747854401
Short name	T507
Test name
Test status
Simulation time	8945404700 ps
CPU time	73.11 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:07:55 PM PDT 24
Peak memory	273732 kb
Host	smart-edb19ba5-b0ff-4f60-b55a-2cba5c92fdce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747854401 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.3747854401
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.1134292810
Short name	T474
Test name
Test status
Simulation time	58356300 ps
CPU time	122.39 seconds
Started	Jul 25 05:06:31 PM PDT 24
Finished	Jul 25 05:08:34 PM PDT 24
Peak memory	276928 kb
Host	smart-e965f64d-337b-4821-9581-efb9b7eb138c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134292810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1134292810
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.3970839740
Short name	T443
Test name
Test status
Simulation time	52168400 ps
CPU time	26.06 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:07:00 PM PDT 24
Peak memory	259600 kb
Host	smart-35ea53cc-83e5-4959-a102-a85e26ba435d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970839740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3970839740
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.2806308820
Short name	T369
Test name
Test status
Simulation time	1857277100 ps
CPU time	1615.38 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:33:39 PM PDT 24
Peak memory	290572 kb
Host	smart-9c90324a-dd41-421e-aa5f-ddbb0fd4e0e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806308820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.2806308820
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.2010110959
Short name	T885
Test name
Test status
Simulation time	25467500 ps
CPU time	26.87 seconds
Started	Jul 25 05:06:34 PM PDT 24
Finished	Jul 25 05:07:01 PM PDT 24
Peak memory	259476 kb
Host	smart-35df4fef-d106-4761-9275-c7e14a47eda8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010110959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2010110959
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.1830933931
Short name	T1061
Test name
Test status
Simulation time	5014957900 ps
CPU time	222.19 seconds
Started	Jul 25 05:06:42 PM PDT 24
Finished	Jul 25 05:10:24 PM PDT 24
Peak memory	264932 kb
Host	smart-bdad52b7-1635-49f8-abed-66f6de72105c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830933931 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.1830933931
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.2686333739
Short name	T492
Test name
Test status
Simulation time	27925700 ps
CPU time	13.42 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:10:28 PM PDT 24
Peak memory	264448 kb
Host	smart-dfbf1eeb-ecd3-480f-be43-999fc7683e50
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686333739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 2686333739
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.2564692119
Short name	T847
Test name
Test status
Simulation time	148539000 ps
CPU time	16.27 seconds
Started	Jul 25 05:10:10 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	282772 kb
Host	smart-d4a522b8-93d0-437a-8bfd-33afc9dd6683
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564692119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2564692119
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.3079946037
Short name	T358
Test name
Test status
Simulation time	32866300 ps
CPU time	20.67 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:10:21 PM PDT 24
Peak memory	273248 kb
Host	smart-e382335a-57a3-4a06-a612-aefcee8064cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079946037 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.3079946037
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.267146391
Short name	T568
Test name
Test status
Simulation time	1438623700 ps
CPU time	64.69 seconds
Started	Jul 25 05:10:00 PM PDT 24
Finished	Jul 25 05:11:04 PM PDT 24
Peak memory	260768 kb
Host	smart-112f06c5-e59e-423e-b3bf-0567a0324c87
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267146391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h w_sec_otp.267146391
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.3984385277
Short name	T983
Test name
Test status
Simulation time	79975500 ps
CPU time	133.25 seconds
Started	Jul 25 05:09:59 PM PDT 24
Finished	Jul 25 05:12:13 PM PDT 24
Peak memory	262040 kb
Host	smart-fef474a9-a1a0-4776-b640-c3b3f3934f8f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984385277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o tp_reset.3984385277
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.1636610546
Short name	T30
Test name
Test status
Simulation time	3874087200 ps
CPU time	70.46 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:11:25 PM PDT 24
Peak memory	264576 kb
Host	smart-d5eeaeaa-4d97-4ebd-9f7a-35c0cbe9c183
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636610546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1636610546
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.328364725
Short name	T110
Test name
Test status
Simulation time	38171300 ps
CPU time	74.69 seconds
Started	Jul 25 05:10:01 PM PDT 24
Finished	Jul 25 05:11:16 PM PDT 24
Peak memory	276396 kb
Host	smart-ab3a49b3-52eb-45d3-99b8-8e7dc958a75e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328364725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.328364725
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.1281424915
Short name	T910
Test name
Test status
Simulation time	99720100 ps
CPU time	13.74 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:10:29 PM PDT 24
Peak memory	257832 kb
Host	smart-46ab63e1-7fac-4186-86a7-40a234a7a9ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281424915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 1281424915
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.279561630
Short name	T2
Test name
Test status
Simulation time	15484000 ps
CPU time	13.23 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:10:28 PM PDT 24
Peak memory	284200 kb
Host	smart-06338e99-9f9f-4ba2-aba9-62729bd2d65b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279561630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.279561630
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.4011332940
Short name	T878
Test name
Test status
Simulation time	16159700 ps
CPU time	20.54 seconds
Started	Jul 25 05:10:10 PM PDT 24
Finished	Jul 25 05:10:31 PM PDT 24
Peak memory	273260 kb
Host	smart-ab6e1878-c0fd-483e-bf85-f01434112d8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011332940 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.4011332940
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3288079423
Short name	T785
Test name
Test status
Simulation time	5195836800 ps
CPU time	201.85 seconds
Started	Jul 25 05:10:12 PM PDT 24
Finished	Jul 25 05:13:34 PM PDT 24
Peak memory	260904 kb
Host	smart-f00ea94d-bd55-4f38-86d3-d9e714271a16
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288079423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.3288079423
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.3423347037
Short name	T109
Test name
Test status
Simulation time	101444800 ps
CPU time	130.78 seconds
Started	Jul 25 05:10:16 PM PDT 24
Finished	Jul 25 05:12:27 PM PDT 24
Peak memory	260616 kb
Host	smart-80fd680d-3041-488d-815b-81673c8dfce1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423347037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o tp_reset.3423347037
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.170747792
Short name	T768
Test name
Test status
Simulation time	9110569700 ps
CPU time	86.66 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:11:38 PM PDT 24
Peak memory	263496 kb
Host	smart-822b9cd9-58fd-47c2-a61d-b6ddd01ef29f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170747792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.170747792
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.2409852069
Short name	T555
Test name
Test status
Simulation time	76029700 ps
CPU time	99.38 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:11:51 PM PDT 24
Peak memory	277248 kb
Host	smart-4b18daae-d031-4a74-a8b5-569cf0e9070a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409852069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2409852069
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.2603938384
Short name	T294
Test name
Test status
Simulation time	52167100 ps
CPU time	13.83 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:10:25 PM PDT 24
Peak memory	257880 kb
Host	smart-e02f4ea6-f34d-438e-9e34-be53f8da1c53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603938384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 2603938384
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.645082685
Short name	T582
Test name
Test status
Simulation time	30230600 ps
CPU time	15.59 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	284172 kb
Host	smart-b38915c3-3218-43c4-bf5e-c30637b95cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645082685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.645082685
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.1691759440
Short name	T181
Test name
Test status
Simulation time	17618200 ps
CPU time	21.81 seconds
Started	Jul 25 05:10:10 PM PDT 24
Finished	Jul 25 05:10:32 PM PDT 24
Peak memory	273184 kb
Host	smart-d628afd9-1167-41dd-bc27-6ae9c966b512
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691759440 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.1691759440
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.787806637
Short name	T729
Test name
Test status
Simulation time	2146911900 ps
CPU time	71.38 seconds
Started	Jul 25 05:10:12 PM PDT 24
Finished	Jul 25 05:11:23 PM PDT 24
Peak memory	260820 kb
Host	smart-5b7a80d5-2383-4900-869a-da3bd838f643
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787806637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_h w_sec_otp.787806637
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.3432321870
Short name	T1036
Test name
Test status
Simulation time	79609100 ps
CPU time	130.52 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:12:25 PM PDT 24
Peak memory	264972 kb
Host	smart-affb9197-c9e4-464a-b0f3-4f716446a31c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432321870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.3432321870
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.2087046309
Short name	T412
Test name
Test status
Simulation time	1709024400 ps
CPU time	57.7 seconds
Started	Jul 25 05:10:09 PM PDT 24
Finished	Jul 25 05:11:07 PM PDT 24
Peak memory	263080 kb
Host	smart-4939d27b-e22c-46a0-8176-6c92f8673f7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087046309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2087046309
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.2321257070
Short name	T500
Test name
Test status
Simulation time	9669143200 ps
CPU time	133.16 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:12:24 PM PDT 24
Peak memory	281360 kb
Host	smart-b833db99-ec74-4223-b08d-a833b84858c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321257070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2321257070
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.2285257155
Short name	T756
Test name
Test status
Simulation time	134397700 ps
CPU time	13.78 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:10:29 PM PDT 24
Peak memory	264872 kb
Host	smart-f595fba7-9d0a-49b0-8c6e-b824c158eb7f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285257155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 2285257155
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.824578437
Short name	T879
Test name
Test status
Simulation time	16460700 ps
CPU time	13.42 seconds
Started	Jul 25 05:10:09 PM PDT 24
Finished	Jul 25 05:10:23 PM PDT 24
Peak memory	282916 kb
Host	smart-3c073bed-9dd8-49ec-9b34-6fa46cd34bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824578437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.824578437
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.140294572
Short name	T993
Test name
Test status
Simulation time	10413400 ps
CPU time	21.68 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:10:32 PM PDT 24
Peak memory	273232 kb
Host	smart-95c8182a-9701-46a9-bcc4-f34193546f1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140294572 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.140294572
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.2913962796
Short name	T949
Test name
Test status
Simulation time	14871226700 ps
CPU time	135.1 seconds
Started	Jul 25 05:10:09 PM PDT 24
Finished	Jul 25 05:12:24 PM PDT 24
Peak memory	260300 kb
Host	smart-f2c09c78-8f7d-471d-bdde-7485f24b7a73
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913962796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.2913962796
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.1849871060
Short name	T938
Test name
Test status
Simulation time	137836200 ps
CPU time	110.51 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:12:05 PM PDT 24
Peak memory	260960 kb
Host	smart-8a581fa5-e715-46a2-912d-68e22b61d5bb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849871060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.1849871060
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.1840374592
Short name	T399
Test name
Test status
Simulation time	1215684800 ps
CPU time	59.37 seconds
Started	Jul 25 05:10:12 PM PDT 24
Finished	Jul 25 05:11:12 PM PDT 24
Peak memory	263592 kb
Host	smart-ebd47912-2935-4d57-8880-849deb203012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840374592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1840374592
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.3961103765
Short name	T373
Test name
Test status
Simulation time	37732000 ps
CPU time	51.64 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:11:06 PM PDT 24
Peak memory	268400 kb
Host	smart-d19b0616-c0a2-452b-a8f5-7e07f16f8870
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961103765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3961103765
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.1322768154
Short name	T964
Test name
Test status
Simulation time	100385800 ps
CPU time	13.77 seconds
Started	Jul 25 05:10:13 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	257900 kb
Host	smart-2daa0027-26cd-4e99-b385-cb4415a772ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322768154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test. 1322768154
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.18647120
Short name	T940
Test name
Test status
Simulation time	26920100 ps
CPU time	16.16 seconds
Started	Jul 25 05:10:11 PM PDT 24
Finished	Jul 25 05:10:27 PM PDT 24
Peak memory	284132 kb
Host	smart-8339432a-9616-4c43-8cb2-ec633f3d612e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18647120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.18647120
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.1510878259
Short name	T654
Test name
Test status
Simulation time	13287200 ps
CPU time	21.63 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:10:37 PM PDT 24
Peak memory	273196 kb
Host	smart-f2861e8e-b73c-43f9-a4aa-3643d5b3173f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510878259 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.1510878259
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1701069225
Short name	T1010
Test name
Test status
Simulation time	3960939700 ps
CPU time	126.66 seconds
Started	Jul 25 05:11:05 PM PDT 24
Finished	Jul 25 05:13:12 PM PDT 24
Peak memory	263224 kb
Host	smart-01f472fc-92ed-44ce-9eb3-5a5981a5c906
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701069225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.1701069225
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.3128702546
Short name	T905
Test name
Test status
Simulation time	36154500 ps
CPU time	109.9 seconds
Started	Jul 25 05:10:12 PM PDT 24
Finished	Jul 25 05:12:02 PM PDT 24
Peak memory	265072 kb
Host	smart-59022ffd-3e8e-438d-8d93-7c19ee583647
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128702546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o tp_reset.3128702546
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.1929857565
Short name	T561
Test name
Test status
Simulation time	781486900 ps
CPU time	57.5 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:11:13 PM PDT 24
Peak memory	263592 kb
Host	smart-cf3d0500-15aa-4e0b-a7b4-d7e3b4c72de0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929857565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1929857565
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.3446506613
Short name	T755
Test name
Test status
Simulation time	80008400 ps
CPU time	96.69 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:11:52 PM PDT 24
Peak memory	277076 kb
Host	smart-c14fc657-e928-45bb-a272-301ca75536db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446506613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3446506613
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.1453875604
Short name	T100
Test name
Test status
Simulation time	30883800 ps
CPU time	13.51 seconds
Started	Jul 25 05:10:12 PM PDT 24
Finished	Jul 25 05:10:26 PM PDT 24
Peak memory	264840 kb
Host	smart-15c083f6-071d-401b-9aee-56c1b06e103b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453875604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test. 1453875604
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.3116973636
Short name	T858
Test name
Test status
Simulation time	13607000 ps
CPU time	15.91 seconds
Started	Jul 25 05:10:12 PM PDT 24
Finished	Jul 25 05:10:28 PM PDT 24
Peak memory	282764 kb
Host	smart-c1c3217c-e602-4624-8d0b-ed7824ead708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116973636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3116973636
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.782194126
Short name	T357
Test name
Test status
Simulation time	20518900 ps
CPU time	22.22 seconds
Started	Jul 25 05:10:13 PM PDT 24
Finished	Jul 25 05:10:36 PM PDT 24
Peak memory	273244 kb
Host	smart-7e734db1-9816-48e9-affc-10933225a24e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782194126 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.782194126
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1974239753
Short name	T724
Test name
Test status
Simulation time	22057669100 ps
CPU time	169.97 seconds
Started	Jul 25 05:10:09 PM PDT 24
Finished	Jul 25 05:12:59 PM PDT 24
Peak memory	262544 kb
Host	smart-eacb0f2d-8ab9-4fb7-a2e8-a24a910ec8a6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974239753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.1974239753
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.3850054945
Short name	T725
Test name
Test status
Simulation time	39215900 ps
CPU time	130.85 seconds
Started	Jul 25 05:10:15 PM PDT 24
Finished	Jul 25 05:12:26 PM PDT 24
Peak memory	264848 kb
Host	smart-a92722ed-d624-465f-9fbf-1f54c4a8aa71
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850054945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.3850054945
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.1185887848
Short name	T758
Test name
Test status
Simulation time	20497049700 ps
CPU time	72.98 seconds
Started	Jul 25 05:10:16 PM PDT 24
Finished	Jul 25 05:11:29 PM PDT 24
Peak memory	263416 kb
Host	smart-da544eb8-ca42-4e2f-a227-77ec5989d74e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185887848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1185887848
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.3756731127
Short name	T656
Test name
Test status
Simulation time	142289100 ps
CPU time	100.33 seconds
Started	Jul 25 05:10:13 PM PDT 24
Finished	Jul 25 05:11:53 PM PDT 24
Peak memory	276736 kb
Host	smart-410dd989-77a8-4b04-9b1a-baf7aa48c6b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756731127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3756731127
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.3384558277
Short name	T661
Test name
Test status
Simulation time	42580500 ps
CPU time	13.39 seconds
Started	Jul 25 05:10:20 PM PDT 24
Finished	Jul 25 05:10:33 PM PDT 24
Peak memory	257960 kb
Host	smart-53c1104b-cd95-4e2e-8407-7a96c252c8ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384558277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test. 3384558277
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.4041983796
Short name	T619
Test name
Test status
Simulation time	30815500 ps
CPU time	13.22 seconds
Started	Jul 25 05:10:25 PM PDT 24
Finished	Jul 25 05:10:38 PM PDT 24
Peak memory	284100 kb
Host	smart-3340f591-7309-42b3-86fe-c41ed8fede8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041983796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.4041983796
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.3878915190
Short name	T551
Test name
Test status
Simulation time	25467800 ps
CPU time	20.26 seconds
Started	Jul 25 05:10:20 PM PDT 24
Finished	Jul 25 05:10:41 PM PDT 24
Peak memory	273216 kb
Host	smart-cc2f844a-ac4a-4747-9e6a-c87ec7f35c23
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878915190 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.3878915190
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2953377127
Short name	T575
Test name
Test status
Simulation time	5201640300 ps
CPU time	147.32 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:12:46 PM PDT 24
Peak memory	260376 kb
Host	smart-781fc910-8d27-45be-af63-11ae61500c22
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953377127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ hw_sec_otp.2953377127
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.2108200472
Short name	T456
Test name
Test status
Simulation time	159909300 ps
CPU time	111.02 seconds
Started	Jul 25 05:10:26 PM PDT 24
Finished	Jul 25 05:12:17 PM PDT 24
Peak memory	260872 kb
Host	smart-8f7678fa-1474-4713-848e-b00b2f869ec0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108200472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o tp_reset.2108200472
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.2133276785
Short name	T484
Test name
Test status
Simulation time	1884927700 ps
CPU time	70.48 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:11:37 PM PDT 24
Peak memory	263312 kb
Host	smart-5c40a170-f23a-4b69-8901-dfb2fcebfe6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133276785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2133276785
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.1246269176
Short name	T659
Test name
Test status
Simulation time	43816000 ps
CPU time	126.41 seconds
Started	Jul 25 05:10:10 PM PDT 24
Finished	Jul 25 05:12:17 PM PDT 24
Peak memory	276056 kb
Host	smart-ada58876-bd7d-4afd-b6d0-d90d19b7234b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246269176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1246269176
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.2184742512
Short name	T581
Test name
Test status
Simulation time	49081800 ps
CPU time	13.8 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:10:33 PM PDT 24
Peak memory	258112 kb
Host	smart-c9e4ef3b-2111-4e56-ad95-ec4bc837321c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184742512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 2184742512
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.1122709557
Short name	T445
Test name
Test status
Simulation time	29250500 ps
CPU time	13.33 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:10:40 PM PDT 24
Peak memory	282808 kb
Host	smart-ab400d8d-f9fd-4ce9-94b3-ac8d5f8d7bf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122709557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.1122709557
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.3400282297
Short name	T392
Test name
Test status
Simulation time	11812400 ps
CPU time	22.02 seconds
Started	Jul 25 05:10:20 PM PDT 24
Finished	Jul 25 05:10:42 PM PDT 24
Peak memory	266072 kb
Host	smart-dc970463-e3f7-4c1c-a72f-4f95a8921607
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400282297 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.3400282297
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2530364751
Short name	T616
Test name
Test status
Simulation time	11487231400 ps
CPU time	155.46 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:12:55 PM PDT 24
Peak memory	260268 kb
Host	smart-816df674-2052-4129-b6d5-f68b925bd1b2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530364751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ hw_sec_otp.2530364751
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.2666252955
Short name	T833
Test name
Test status
Simulation time	153840900 ps
CPU time	132.53 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:12:31 PM PDT 24
Peak memory	260940 kb
Host	smart-1dac566f-bec7-417c-8e96-2ac7335fadf7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666252955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o tp_reset.2666252955
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.3315222188
Short name	T868
Test name
Test status
Simulation time	58714100 ps
CPU time	52.19 seconds
Started	Jul 25 05:10:17 PM PDT 24
Finished	Jul 25 05:11:09 PM PDT 24
Peak memory	270924 kb
Host	smart-18be2034-7ce2-4ed9-8a4c-59715ab24284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315222188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3315222188
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.3797483624
Short name	T123
Test name
Test status
Simulation time	68259700 ps
CPU time	14 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:10:34 PM PDT 24
Peak memory	264796 kb
Host	smart-dabf5fb8-ea7c-4490-8756-9d8541223f30
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797483624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test. 3797483624
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.203988259
Short name	T1054
Test name
Test status
Simulation time	14117200 ps
CPU time	15.8 seconds
Started	Jul 25 05:10:18 PM PDT 24
Finished	Jul 25 05:10:34 PM PDT 24
Peak memory	282908 kb
Host	smart-254205ec-9496-42de-a05e-501b06612943
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203988259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.203988259
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.2245693973
Short name	T391
Test name
Test status
Simulation time	15411700 ps
CPU time	21.81 seconds
Started	Jul 25 05:10:23 PM PDT 24
Finished	Jul 25 05:10:45 PM PDT 24
Peak memory	265120 kb
Host	smart-a9253e94-b53c-4231-ba46-e49e1a107db3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245693973 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.2245693973
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2355669760
Short name	T1006
Test name
Test status
Simulation time	479028900 ps
CPU time	48.21 seconds
Started	Jul 25 05:10:24 PM PDT 24
Finished	Jul 25 05:11:12 PM PDT 24
Peak memory	260904 kb
Host	smart-bae915e7-5643-432e-b191-bbed5f030817
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355669760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ hw_sec_otp.2355669760
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.404586034
Short name	T871
Test name
Test status
Simulation time	51697100 ps
CPU time	129.85 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:12:29 PM PDT 24
Peak memory	264032 kb
Host	smart-4f76825e-2c43-4c44-ab62-12aef1252e0e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404586034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot p_reset.404586034
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.135718049
Short name	T401
Test name
Test status
Simulation time	3030560500 ps
CPU time	70.2 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:11:29 PM PDT 24
Peak memory	264676 kb
Host	smart-81964b8b-c333-4153-93e1-ee58c1c7dc02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135718049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.135718049
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.2244369399
Short name	T152
Test name
Test status
Simulation time	1686653300 ps
CPU time	193.72 seconds
Started	Jul 25 05:10:20 PM PDT 24
Finished	Jul 25 05:13:34 PM PDT 24
Peak memory	281280 kb
Host	smart-da448197-460a-44a3-ab82-f1f2c8c45b00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244369399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2244369399
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.3512796065
Short name	T467
Test name
Test status
Simulation time	107496100 ps
CPU time	13.84 seconds
Started	Jul 25 05:10:26 PM PDT 24
Finished	Jul 25 05:10:40 PM PDT 24
Peak memory	257820 kb
Host	smart-22a7cc85-1b09-41b4-94f3-2d84ac8fe6a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512796065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test. 3512796065
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.2236465580
Short name	T1102
Test name
Test status
Simulation time	19648100 ps
CPU time	16.4 seconds
Started	Jul 25 05:10:20 PM PDT 24
Finished	Jul 25 05:10:36 PM PDT 24
Peak memory	284212 kb
Host	smart-feee3255-76d4-4646-9d0d-436e27aab8cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236465580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2236465580
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.2097703928
Short name	T42
Test name
Test status
Simulation time	20279900 ps
CPU time	22.19 seconds
Started	Jul 25 05:10:26 PM PDT 24
Finished	Jul 25 05:10:48 PM PDT 24
Peak memory	273180 kb
Host	smart-d0d972f1-e396-4d74-bafc-1e9ba3252bc7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097703928 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.2097703928
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1062027208
Short name	T589
Test name
Test status
Simulation time	1130849700 ps
CPU time	94.72 seconds
Started	Jul 25 05:10:17 PM PDT 24
Finished	Jul 25 05:11:52 PM PDT 24
Peak memory	260668 kb
Host	smart-22befc67-e588-421e-9217-3163c90bd518
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062027208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ hw_sec_otp.1062027208
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.1917766212
Short name	T817
Test name
Test status
Simulation time	38868200 ps
CPU time	130.38 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:12:30 PM PDT 24
Peak memory	260616 kb
Host	smart-4f61e502-38b4-4b0e-a5e7-478dfafb918e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917766212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.1917766212
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.119370767
Short name	T442
Test name
Test status
Simulation time	1401668200 ps
CPU time	66.96 seconds
Started	Jul 25 05:10:26 PM PDT 24
Finished	Jul 25 05:11:34 PM PDT 24
Peak memory	263480 kb
Host	smart-d9b55b02-d1b4-4b80-863a-02fc9ef476ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119370767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.119370767
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.235407067
Short name	T948
Test name
Test status
Simulation time	20010900 ps
CPU time	52.82 seconds
Started	Jul 25 05:10:19 PM PDT 24
Finished	Jul 25 05:11:12 PM PDT 24
Peak memory	271000 kb
Host	smart-3d714a46-6b51-4142-a92a-7d23fa838459
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235407067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.235407067
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.1649901781
Short name	T435
Test name
Test status
Simulation time	28752500 ps
CPU time	13.63 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:07:06 PM PDT 24
Peak memory	257952 kb
Host	smart-f9411b22-1afe-4834-a635-50e272660657
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649901781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1 649901781
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.622522344
Short name	T893
Test name
Test status
Simulation time	29894100 ps
CPU time	16.13 seconds
Started	Jul 25 05:06:54 PM PDT 24
Finished	Jul 25 05:07:11 PM PDT 24
Peak memory	284064 kb
Host	smart-957d8a96-64ae-48cb-ad8e-7da38be31b37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622522344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.622522344
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.1851608633
Short name	T979
Test name
Test status
Simulation time	27169100 ps
CPU time	20.68 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:07:12 PM PDT 24
Peak memory	273248 kb
Host	smart-146931b8-c5be-4f48-b20c-98b83fc20295
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851608633 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.1851608633
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.2997198605
Short name	T707
Test name
Test status
Simulation time	6454773700 ps
CPU time	2207.13 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:43:39 PM PDT 24
Peak memory	262440 kb
Host	smart-ea2e94ed-ea1f-48fd-9075-8751f839a641
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2997198605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.2997198605
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.542744137
Short name	T280
Test name
Test status
Simulation time	4821074300 ps
CPU time	1008.49 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:23:41 PM PDT 24
Peak memory	272780 kb
Host	smart-838d26c6-7f05-4f47-9f03-9efd41b8cb1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542744137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.542744137
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.1500188436
Short name	T1005
Test name
Test status
Simulation time	909275400 ps
CPU time	27.33 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:07:12 PM PDT 24
Peak memory	262276 kb
Host	smart-3876782e-6c21-4ae4-a227-0ba72e804108
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500188436 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1500188436
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1376559743
Short name	T1027
Test name
Test status
Simulation time	10026965500 ps
CPU time	65.7 seconds
Started	Jul 25 05:06:53 PM PDT 24
Finished	Jul 25 05:07:59 PM PDT 24
Peak memory	277448 kb
Host	smart-f9a14cf1-da98-4b4b-abba-1b32ac02e8df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376559743 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1376559743
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2798306366
Short name	T775
Test name
Test status
Simulation time	24676400 ps
CPU time	13.51 seconds
Started	Jul 25 05:07:04 PM PDT 24
Finished	Jul 25 05:07:18 PM PDT 24
Peak memory	264524 kb
Host	smart-936d71e6-3654-43c8-90f8-cd59c19c3c1d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798306366 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2798306366
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2655194345
Short name	T998
Test name
Test status
Simulation time	80153576800 ps
CPU time	887.88 seconds
Started	Jul 25 05:06:42 PM PDT 24
Finished	Jul 25 05:21:30 PM PDT 24
Peak memory	264240 kb
Host	smart-adf47b08-bc24-4679-81a2-3878e4e65f76
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655194345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_hw_rma_reset.2655194345
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2210984466
Short name	T894
Test name
Test status
Simulation time	1662654100 ps
CPU time	137.8 seconds
Started	Jul 25 05:06:48 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	263064 kb
Host	smart-b125b358-6d9e-499e-912f-2b111d288d35
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210984466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h w_sec_otp.2210984466
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.193111266
Short name	T866
Test name
Test status
Simulation time	1205694700 ps
CPU time	166.68 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:09:39 PM PDT 24
Peak memory	293776 kb
Host	smart-b98211d1-9810-41cc-9098-93c1b01c6546
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193111266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_intr_rd.193111266
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3787255756
Short name	T640
Test name
Test status
Simulation time	91698340700 ps
CPU time	170.08 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:09:42 PM PDT 24
Peak memory	292840 kb
Host	smart-c257a58d-05e7-4e8b-9587-e0cad6720f21
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787255756 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3787255756
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.2961070263
Short name	T1070
Test name
Test status
Simulation time	2503730100 ps
CPU time	68.94 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:08:00 PM PDT 24
Peak memory	260244 kb
Host	smart-3ac2ae2a-860e-46d0-ad97-2bdfc85ea638
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961070263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_wr.2961070263
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.458666444
Short name	T759
Test name
Test status
Simulation time	1011371700 ps
CPU time	87.41 seconds
Started	Jul 25 05:06:53 PM PDT 24
Finished	Jul 25 05:08:20 PM PDT 24
Peak memory	260352 kb
Host	smart-6125ba9e-2345-4076-8d41-5d045c0a5764
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458666444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.458666444
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.2433056284
Short name	T573
Test name
Test status
Simulation time	25100100 ps
CPU time	13.35 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:11 PM PDT 24
Peak memory	264520 kb
Host	smart-36f580eb-dade-4961-8e1b-946230fc9689
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433056284 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.2433056284
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.4084598877
Short name	T83
Test name
Test status
Simulation time	36486900 ps
CPU time	131.52 seconds
Started	Jul 25 05:06:41 PM PDT 24
Finished	Jul 25 05:08:53 PM PDT 24
Peak memory	259660 kb
Host	smart-22036d31-05d3-4ad4-bde6-005d17435a87
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084598877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot p_reset.4084598877
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.203808044
Short name	T454
Test name
Test status
Simulation time	734450900 ps
CPU time	379.26 seconds
Started	Jul 25 05:06:48 PM PDT 24
Finished	Jul 25 05:13:08 PM PDT 24
Peak memory	262888 kb
Host	smart-cf09ade4-1c2c-4652-9e4d-3325871a68b8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=203808044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.203808044
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.766871154
Short name	T387
Test name
Test status
Simulation time	272391200 ps
CPU time	13.55 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:07:06 PM PDT 24
Peak memory	264924 kb
Host	smart-e0cc154f-8634-4908-acbf-e1d8e50f7b7f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766871154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.flash_ctrl_prog_reset.766871154
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.2276459834
Short name	T153
Test name
Test status
Simulation time	4988202000 ps
CPU time	443.57 seconds
Started	Jul 25 05:06:48 PM PDT 24
Finished	Jul 25 05:14:12 PM PDT 24
Peak memory	282732 kb
Host	smart-3c990fe1-4e6f-4797-8af6-cc01dcf26dc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276459834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2276459834
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.977037354
Short name	T896
Test name
Test status
Simulation time	971971100 ps
CPU time	36.07 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:34 PM PDT 24
Peak memory	268156 kb
Host	smart-156dbf61-9898-43b5-92f4-bcca4a76f657
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977037354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_re_evict.977037354
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.1454834212
Short name	T63
Test name
Test status
Simulation time	1785689900 ps
CPU time	126.35 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:08:58 PM PDT 24
Peak memory	281452 kb
Host	smart-d81393b5-54cb-4787-9f7c-b26e24860dd8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454834212 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.1454834212
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.3114350488
Short name	T210
Test name
Test status
Simulation time	618775900 ps
CPU time	145.04 seconds
Started	Jul 25 05:06:50 PM PDT 24
Finished	Jul 25 05:09:15 PM PDT 24
Peak memory	281492 kb
Host	smart-0d7498a5-b02d-4b92-83c6-30b019c52366
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3114350488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3114350488
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.2813107137
Short name	T36
Test name
Test status
Simulation time	2360097900 ps
CPU time	131.18 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:09:03 PM PDT 24
Peak memory	281516 kb
Host	smart-1b6b4beb-aea5-47e1-886d-24c582d8f914
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813107137 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2813107137
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.1051336020
Short name	T739
Test name
Test status
Simulation time	4041685300 ps
CPU time	608.5 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:17:07 PM PDT 24
Peak memory	314368 kb
Host	smart-aa5671bd-8ad2-4990-905e-b5a9ecd99598
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051336020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.flash_ctrl_rw.1051336020
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.1605446369
Short name	T601
Test name
Test status
Simulation time	73394100 ps
CPU time	31.55 seconds
Started	Jul 25 05:06:50 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	275160 kb
Host	smart-3c46a7f5-00f7-45da-a2ea-c6ff0c854bdd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605446369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.1605446369
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.2714493484
Short name	T673
Test name
Test status
Simulation time	218383500 ps
CPU time	30.74 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:07:41 PM PDT 24
Peak memory	268152 kb
Host	smart-002750e8-face-4f7b-b834-dcf6944b931d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714493484 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.2714493484
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_serr.172299146
Short name	T956
Test name
Test status
Simulation time	26776664600 ps
CPU time	637.24 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:17:28 PM PDT 24
Peak memory	313960 kb
Host	smart-484a7d90-37ac-46fe-8eab-d476b0cb3d41
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172299146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_se rr.172299146
Directory	/workspace/5.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.2453905812
Short name	T749
Test name
Test status
Simulation time	110557700 ps
CPU time	122.56 seconds
Started	Jul 25 05:06:44 PM PDT 24
Finished	Jul 25 05:08:46 PM PDT 24
Peak memory	275980 kb
Host	smart-173ccc31-dec0-490d-b8f5-2ad6a5251494
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453905812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2453905812
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.2580440128
Short name	T917
Test name
Test status
Simulation time	1774995500 ps
CPU time	156.59 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:09:29 PM PDT 24
Peak memory	259536 kb
Host	smart-735bca0e-36ea-49f7-875b-4f58b545b56f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580440128 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.flash_ctrl_wo.2580440128
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.581317405
Short name	T1107
Test name
Test status
Simulation time	23895400 ps
CPU time	15.76 seconds
Started	Jul 25 05:10:17 PM PDT 24
Finished	Jul 25 05:10:33 PM PDT 24
Peak memory	274728 kb
Host	smart-192253a5-81c0-49cd-9b37-3a0ad0a3746c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581317405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.581317405
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.3576683218
Short name	T706
Test name
Test status
Simulation time	131111300 ps
CPU time	111.08 seconds
Started	Jul 25 05:10:21 PM PDT 24
Finished	Jul 25 05:12:12 PM PDT 24
Peak memory	260972 kb
Host	smart-03bac500-c6c5-4da6-876d-c7ebbdbd1e41
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576683218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o tp_reset.3576683218
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.3562920501
Short name	T820
Test name
Test status
Simulation time	27560300 ps
CPU time	16.3 seconds
Started	Jul 25 05:10:26 PM PDT 24
Finished	Jul 25 05:10:43 PM PDT 24
Peak memory	284104 kb
Host	smart-4ebfab90-83c8-405a-8f36-1f8824178af8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562920501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3562920501
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.2286507242
Short name	T84
Test name
Test status
Simulation time	78225100 ps
CPU time	132.28 seconds
Started	Jul 25 05:10:20 PM PDT 24
Finished	Jul 25 05:12:32 PM PDT 24
Peak memory	260280 kb
Host	smart-a069190c-46e4-41be-abde-3122d4787415
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286507242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.2286507242
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.1301979755
Short name	T985
Test name
Test status
Simulation time	21455500 ps
CPU time	16.05 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:10:43 PM PDT 24
Peak memory	284132 kb
Host	smart-031ce9bd-55af-4e3e-bb25-92b8c5ba2e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301979755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1301979755
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.1477440734
Short name	T1059
Test name
Test status
Simulation time	23885700 ps
CPU time	15.63 seconds
Started	Jul 25 05:10:26 PM PDT 24
Finished	Jul 25 05:10:42 PM PDT 24
Peak memory	282884 kb
Host	smart-4db3b944-6a32-4fbf-a230-35616124dda4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477440734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1477440734
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.886159360
Short name	T460
Test name
Test status
Simulation time	40973000 ps
CPU time	130.97 seconds
Started	Jul 25 05:10:28 PM PDT 24
Finished	Jul 25 05:12:39 PM PDT 24
Peak memory	259876 kb
Host	smart-5759d494-6bcf-475d-b1fa-c2e25722f9ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886159360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot p_reset.886159360
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.2115301671
Short name	T799
Test name
Test status
Simulation time	38215900 ps
CPU time	15.99 seconds
Started	Jul 25 05:10:28 PM PDT 24
Finished	Jul 25 05:10:44 PM PDT 24
Peak memory	274728 kb
Host	smart-4effc88a-0bf6-4afb-a4d3-f09acc76b6a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115301671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2115301671
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.1786889234
Short name	T919
Test name
Test status
Simulation time	50991100 ps
CPU time	132.95 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:12:40 PM PDT 24
Peak memory	264040 kb
Host	smart-b95fcb63-06f2-4c96-b639-6af68e341dd4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786889234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.1786889234
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.2702312217
Short name	T613
Test name
Test status
Simulation time	18375000 ps
CPU time	13.41 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:10:41 PM PDT 24
Peak memory	284036 kb
Host	smart-83b86238-55ed-4208-a119-fd7b1d5bace7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702312217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2702312217
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.1004809638
Short name	T902
Test name
Test status
Simulation time	171683900 ps
CPU time	15.84 seconds
Started	Jul 25 05:10:28 PM PDT 24
Finished	Jul 25 05:10:44 PM PDT 24
Peak memory	284176 kb
Host	smart-d69f3f83-2cfc-4820-9647-33ec86fa4037
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004809638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1004809638
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.2615587999
Short name	T988
Test name
Test status
Simulation time	109754500 ps
CPU time	108.12 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:12:15 PM PDT 24
Peak memory	260912 kb
Host	smart-e917a818-3abf-4dd3-b651-32ffc843569c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615587999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o tp_reset.2615587999
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.3694091271
Short name	T469
Test name
Test status
Simulation time	40482800 ps
CPU time	16.08 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:10:43 PM PDT 24
Peak memory	282828 kb
Host	smart-2f49cedb-4082-4540-8fbf-93d82292619b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694091271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3694091271
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.469462414
Short name	T777
Test name
Test status
Simulation time	297076200 ps
CPU time	133.11 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:12:40 PM PDT 24
Peak memory	264848 kb
Host	smart-e6d3fdcb-7f88-4214-8713-3c82b5bee40d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469462414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot p_reset.469462414
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.1505482250
Short name	T481
Test name
Test status
Simulation time	15846100 ps
CPU time	15.72 seconds
Started	Jul 25 05:10:27 PM PDT 24
Finished	Jul 25 05:10:43 PM PDT 24
Peak memory	284060 kb
Host	smart-708b6a9b-42a6-41a7-8a14-85c9089c113e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505482250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1505482250
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.2501954101
Short name	T543
Test name
Test status
Simulation time	155371100 ps
CPU time	132.7 seconds
Started	Jul 25 05:10:25 PM PDT 24
Finished	Jul 25 05:12:38 PM PDT 24
Peak memory	264016 kb
Host	smart-a7ab0aa4-0359-4134-8c88-521a2992cba8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501954101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.2501954101
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.615929440
Short name	T1013
Test name
Test status
Simulation time	16561200 ps
CPU time	13.57 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:10:51 PM PDT 24
Peak memory	284092 kb
Host	smart-3f1d0b93-b098-447a-a5ce-d9fb6ce5872b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615929440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.615929440
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.3981172647
Short name	T150
Test name
Test status
Simulation time	77354900 ps
CPU time	130.98 seconds
Started	Jul 25 05:10:34 PM PDT 24
Finished	Jul 25 05:12:46 PM PDT 24
Peak memory	265224 kb
Host	smart-ebebf720-0a41-44c1-8ed8-18b017b72c98
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981172647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.3981172647
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.1846295700
Short name	T372
Test name
Test status
Simulation time	64062900 ps
CPU time	13.97 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:07:16 PM PDT 24
Peak memory	257908 kb
Host	smart-6a5eb3ba-f1f0-46b3-913d-1c4ab1182485
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846295700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1 846295700
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.1820553784
Short name	T974
Test name
Test status
Simulation time	41998500 ps
CPU time	15.99 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:07:15 PM PDT 24
Peak memory	284172 kb
Host	smart-bb65c919-2bf3-42e8-a454-0075fdf3f844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820553784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1820553784
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.1194308645
Short name	T184
Test name
Test status
Simulation time	113067300 ps
CPU time	22.27 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	265120 kb
Host	smart-ec06e858-7afd-47bd-9057-f1d302d0bcdc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194308645 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.1194308645
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.3955504574
Short name	T279
Test name
Test status
Simulation time	7783692600 ps
CPU time	2319.66 seconds
Started	Jul 25 05:06:50 PM PDT 24
Finished	Jul 25 05:45:30 PM PDT 24
Peak memory	262636 kb
Host	smart-b3ca219e-1b7d-4c5d-a96d-aaa00f1e0e55
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3955504574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3955504574
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.3513970074
Short name	T647
Test name
Test status
Simulation time	384933000 ps
CPU time	701.7 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:18:34 PM PDT 24
Peak memory	273104 kb
Host	smart-5ffb82c7-2511-4928-8d09-97a4a167030d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513970074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3513970074
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.1114276944
Short name	T47
Test name
Test status
Simulation time	1211853100 ps
CPU time	27.26 seconds
Started	Jul 25 05:06:50 PM PDT 24
Finished	Jul 25 05:07:18 PM PDT 24
Peak memory	262176 kb
Host	smart-f89cb982-3a2e-4fea-8ee6-7c04ae117e05
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114276944 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1114276944
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3012268485
Short name	T1023
Test name
Test status
Simulation time	10016332500 ps
CPU time	105.42 seconds
Started	Jul 25 05:07:02 PM PDT 24
Finished	Jul 25 05:08:48 PM PDT 24
Peak memory	340176 kb
Host	smart-e5223665-72da-4ca4-a9e7-f572156f46d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012268485 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3012268485
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.124095539
Short name	T752
Test name
Test status
Simulation time	15565700 ps
CPU time	13.49 seconds
Started	Jul 25 05:07:00 PM PDT 24
Finished	Jul 25 05:07:13 PM PDT 24
Peak memory	259756 kb
Host	smart-5af73437-2443-47a4-87b7-ded0dbc249b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124095539 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.124095539
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3745081653
Short name	T158
Test name
Test status
Simulation time	760521633600 ps
CPU time	1578.73 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:33:26 PM PDT 24
Peak memory	264308 kb
Host	smart-031ae0ef-8f77-4ac1-bf0c-cde61fc25fe5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745081653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_hw_rma_reset.3745081653
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3753103880
Short name	T811
Test name
Test status
Simulation time	6029281400 ps
CPU time	239.49 seconds
Started	Jul 25 05:07:04 PM PDT 24
Finished	Jul 25 05:11:04 PM PDT 24
Peak memory	262620 kb
Host	smart-1173a9aa-4d3a-4b0c-8a7c-d431ca800ab9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753103880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.3753103880
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.297329412
Short name	T538
Test name
Test status
Simulation time	6915302900 ps
CPU time	143.66 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:09:16 PM PDT 24
Peak memory	293740 kb
Host	smart-0e9282f6-c6e6-47f4-be56-14f48630e9f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297329412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_intr_rd.297329412
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3251249117
Short name	T308
Test name
Test status
Simulation time	116815766400 ps
CPU time	162.49 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:09:41 PM PDT 24
Peak memory	293828 kb
Host	smart-1c760849-7843-431c-badb-5e6366e09808
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251249117 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3251249117
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.3022906968
Short name	T890
Test name
Test status
Simulation time	2769192600 ps
CPU time	78.12 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:08:16 PM PDT 24
Peak memory	264856 kb
Host	smart-03f30457-dc36-4387-a1b0-9d3b8fb6d94f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022906968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_wr.3022906968
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1064890501
Short name	T1009
Test name
Test status
Simulation time	323167169900 ps
CPU time	254.37 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:11:12 PM PDT 24
Peak memory	260168 kb
Host	smart-6eedc215-95e5-43e5-baa6-4adb05f8ecc9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106 4890501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1064890501
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.3053575212
Short name	T854
Test name
Test status
Simulation time	3348124200 ps
CPU time	62.14 seconds
Started	Jul 25 05:06:50 PM PDT 24
Finished	Jul 25 05:07:52 PM PDT 24
Peak memory	263304 kb
Host	smart-30418bf7-feaa-4dc5-98bf-1cfd976642fe
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053575212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3053575212
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.1829092331
Short name	T163
Test name
Test status
Simulation time	46154300 ps
CPU time	13.48 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:12 PM PDT 24
Peak memory	264460 kb
Host	smart-8e299f26-394f-4da8-aebf-6640693ad03e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829092331 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.1829092331
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.2536383125
Short name	T1057
Test name
Test status
Simulation time	64795700 ps
CPU time	110.61 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:08:43 PM PDT 24
Peak memory	259776 kb
Host	smart-9b2a9f99-f25b-487f-b778-58e6e56929d3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536383125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.2536383125
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.2543172432
Short name	T792
Test name
Test status
Simulation time	136206800 ps
CPU time	280.62 seconds
Started	Jul 25 05:06:49 PM PDT 24
Finished	Jul 25 05:11:30 PM PDT 24
Peak memory	262832 kb
Host	smart-77ceb31e-d6e3-4555-9dc6-3b7b0b0be884
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2543172432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2543172432
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.625482851
Short name	T844
Test name
Test status
Simulation time	21078700 ps
CPU time	13.53 seconds
Started	Jul 25 05:06:49 PM PDT 24
Finished	Jul 25 05:07:03 PM PDT 24
Peak memory	258808 kb
Host	smart-68273e83-a34d-4cd7-9322-fe7819fbf4b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625482851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.flash_ctrl_prog_reset.625482851
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.355564549
Short name	T933
Test name
Test status
Simulation time	3137495200 ps
CPU time	1002.13 seconds
Started	Jul 25 05:06:55 PM PDT 24
Finished	Jul 25 05:23:37 PM PDT 24
Peak memory	286284 kb
Host	smart-d45f94c5-a2ee-4828-a5c6-114961b172e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355564549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.355564549
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.768796311
Short name	T330
Test name
Test status
Simulation time	61032100 ps
CPU time	31.51 seconds
Started	Jul 25 05:06:52 PM PDT 24
Finished	Jul 25 05:07:24 PM PDT 24
Peak memory	275316 kb
Host	smart-8f14d8e2-8580-40f1-abae-312afd2dc7f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768796311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_re_evict.768796311
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.1458304482
Short name	T698
Test name
Test status
Simulation time	602525500 ps
CPU time	124.18 seconds
Started	Jul 25 05:06:49 PM PDT 24
Finished	Jul 25 05:08:53 PM PDT 24
Peak memory	289700 kb
Host	smart-231a8049-600d-4282-912c-8c07e04658ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458304482 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_ro.1458304482
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.199379408
Short name	T201
Test name
Test status
Simulation time	4302649200 ps
CPU time	156.73 seconds
Started	Jul 25 05:06:54 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	282656 kb
Host	smart-c44abbf0-f390-4ae4-bb39-eac38bfc52f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 199379408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.199379408
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.88967016
Short name	T629
Test name
Test status
Simulation time	1279165100 ps
CPU time	132.95 seconds
Started	Jul 25 05:06:53 PM PDT 24
Finished	Jul 25 05:09:06 PM PDT 24
Peak memory	294500 kb
Host	smart-1dfd7613-d0d0-4a47-8a95-c6f75d217cbd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88967016 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.88967016
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.894015848
Short name	T214
Test name
Test status
Simulation time	6505934400 ps
CPU time	448.63 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:14:39 PM PDT 24
Peak memory	314316 kb
Host	smart-bc886a62-cc0f-4e66-9a9e-c671b18c4fcc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894015848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.894015848
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_derr.2175834847
Short name	T238
Test name
Test status
Simulation time	16732235700 ps
CPU time	615.66 seconds
Started	Jul 25 05:06:51 PM PDT 24
Finished	Jul 25 05:17:07 PM PDT 24
Peak memory	337984 kb
Host	smart-4a15814e-602b-427f-b71a-9d031873b948
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175834847 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_rw_derr.2175834847
Directory	/workspace/6.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.3602338080
Short name	T268
Test name
Test status
Simulation time	27204100 ps
CPU time	29.16 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:27 PM PDT 24
Peak memory	273284 kb
Host	smart-3ad8b974-5745-455e-a0be-ce30661df71e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602338080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.3602338080
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3564366730
Short name	T338
Test name
Test status
Simulation time	127283500 ps
CPU time	31.24 seconds
Started	Jul 25 05:07:53 PM PDT 24
Finished	Jul 25 05:08:24 PM PDT 24
Peak memory	275376 kb
Host	smart-ed7b2141-f83a-4613-94dd-265d5edccefc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564366730 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3564366730
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.4013277165
Short name	T796
Test name
Test status
Simulation time	9148072300 ps
CPU time	82.33 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:08:21 PM PDT 24
Peak memory	262824 kb
Host	smart-6a4d09f4-1afc-4881-a143-0a39157d7152
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013277165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.4013277165
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.1056788565
Short name	T685
Test name
Test status
Simulation time	107182100 ps
CPU time	125.73 seconds
Started	Jul 25 05:06:53 PM PDT 24
Finished	Jul 25 05:08:59 PM PDT 24
Peak memory	268508 kb
Host	smart-66d7dd8d-8dbc-401f-b3f3-919a5bf37001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056788565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1056788565
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.336688595
Short name	T379
Test name
Test status
Simulation time	7779580200 ps
CPU time	178.51 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:09:57 PM PDT 24
Peak memory	264976 kb
Host	smart-e2355aa8-1da1-4667-9bef-987d3a6e8b51
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336688595 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_wo.336688595
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.858686560
Short name	T934
Test name
Test status
Simulation time	26610100 ps
CPU time	15.78 seconds
Started	Jul 25 05:10:34 PM PDT 24
Finished	Jul 25 05:10:49 PM PDT 24
Peak memory	284192 kb
Host	smart-39ac1c45-7375-4b67-9b53-aa1058d9cc9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858686560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.858686560
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.3367852858
Short name	T174
Test name
Test status
Simulation time	526795400 ps
CPU time	133.18 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:12:50 PM PDT 24
Peak memory	264488 kb
Host	smart-e39f954c-2b0f-4bf8-890d-6ada85669757
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367852858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o tp_reset.3367852858
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.2781170026
Short name	T842
Test name
Test status
Simulation time	42182100 ps
CPU time	13.34 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:10:50 PM PDT 24
Peak memory	283980 kb
Host	smart-219bae28-25c6-49dc-b2e8-f11333e2179c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781170026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2781170026
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.949761325
Short name	T72
Test name
Test status
Simulation time	35166700 ps
CPU time	134.29 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:12:51 PM PDT 24
Peak memory	259744 kb
Host	smart-e8740048-5426-4e09-a0ca-26915b6904b0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949761325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_ot p_reset.949761325
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.4183057494
Short name	T480
Test name
Test status
Simulation time	27747200 ps
CPU time	15.71 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	284176 kb
Host	smart-ac87fe67-fe61-4bbe-9d97-aec85844326f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183057494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.4183057494
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.4144887653
Short name	T671
Test name
Test status
Simulation time	40588200 ps
CPU time	133.2 seconds
Started	Jul 25 05:11:27 PM PDT 24
Finished	Jul 25 05:13:40 PM PDT 24
Peak memory	261792 kb
Host	smart-e925e19d-c3a9-4d67-b698-0295765b77b8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144887653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o tp_reset.4144887653
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.2160031793
Short name	T677
Test name
Test status
Simulation time	23935000 ps
CPU time	16.13 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	284236 kb
Host	smart-a27ab79e-8ad9-4cce-a319-40c5987ab20e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160031793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2160031793
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.3460605918
Short name	T1022
Test name
Test status
Simulation time	321827100 ps
CPU time	132.73 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:12:49 PM PDT 24
Peak memory	264812 kb
Host	smart-6a352d04-d788-46f5-aba5-28843930714f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460605918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o tp_reset.3460605918
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.124801584
Short name	T537
Test name
Test status
Simulation time	15695600 ps
CPU time	16.13 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	282892 kb
Host	smart-c0672243-63a2-4569-ae62-5406f41e5d5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124801584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.124801584
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.2667519797
Short name	T1079
Test name
Test status
Simulation time	143171300 ps
CPU time	133.99 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:12:51 PM PDT 24
Peak memory	260648 kb
Host	smart-8df2103b-9afd-4e0f-bfee-c61f7098cd12
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667519797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o tp_reset.2667519797
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.2589024486
Short name	T684
Test name
Test status
Simulation time	19149700 ps
CPU time	15.83 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:10:53 PM PDT 24
Peak memory	274740 kb
Host	smart-6a03d3ac-b8db-4f7c-9956-7c396d6c04a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589024486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2589024486
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.3948473664
Short name	T843
Test name
Test status
Simulation time	132550100 ps
CPU time	133.26 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:12:51 PM PDT 24
Peak memory	260680 kb
Host	smart-2590cd4b-f534-412d-9c0f-5086ce1397f8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948473664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o tp_reset.3948473664
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.1474892010
Short name	T129
Test name
Test status
Simulation time	30257000 ps
CPU time	15.84 seconds
Started	Jul 25 05:10:38 PM PDT 24
Finished	Jul 25 05:10:54 PM PDT 24
Peak memory	274704 kb
Host	smart-d9ed45a7-d55b-4f18-a957-0379d5b8c026
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474892010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1474892010
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.453583419
Short name	T477
Test name
Test status
Simulation time	36132500 ps
CPU time	132.8 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:12:49 PM PDT 24
Peak memory	260744 kb
Host	smart-cc79b161-f08b-47b9-ae42-c9811aa58963
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453583419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot p_reset.453583419
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.1926010983
Short name	T119
Test name
Test status
Simulation time	47541600 ps
CPU time	16.07 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:10:54 PM PDT 24
Peak memory	282804 kb
Host	smart-ea03b940-656c-46cf-af80-e24845dd23d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926010983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1926010983
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.1055593016
Short name	T159
Test name
Test status
Simulation time	49206500 ps
CPU time	133.09 seconds
Started	Jul 25 05:10:34 PM PDT 24
Finished	Jul 25 05:12:48 PM PDT 24
Peak memory	263936 kb
Host	smart-ec08f286-3e7c-46ca-b08b-e85404078389
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055593016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.1055593016
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.1579165150
Short name	T947
Test name
Test status
Simulation time	52964000 ps
CPU time	13.44 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:10:50 PM PDT 24
Peak memory	282724 kb
Host	smart-82cfea2e-d3a0-4277-9bc7-93fbd0dc1195
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579165150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1579165150
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.1565978686
Short name	T906
Test name
Test status
Simulation time	39102900 ps
CPU time	132.58 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:12:49 PM PDT 24
Peak memory	259984 kb
Host	smart-f60c1c2d-716a-480e-b821-74c1e238645b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565978686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.1565978686
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.54704735
Short name	T625
Test name
Test status
Simulation time	14846100 ps
CPU time	16 seconds
Started	Jul 25 05:10:36 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	284136 kb
Host	smart-51fbe576-7807-46b3-a909-6d2c813a6671
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54704735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.54704735
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.1491656299
Short name	T177
Test name
Test status
Simulation time	110791200 ps
CPU time	134.26 seconds
Started	Jul 25 05:10:42 PM PDT 24
Finished	Jul 25 05:12:56 PM PDT 24
Peak memory	260664 kb
Host	smart-9c31d7b8-7484-4bff-8bc3-d8983b70175b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491656299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.1491656299
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.2530061659
Short name	T945
Test name
Test status
Simulation time	71769200 ps
CPU time	13.51 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:07:14 PM PDT 24
Peak memory	257908 kb
Host	smart-f6730f0a-ddfc-40c8-ac6a-d957468a8d87
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530061659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2 530061659
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.3409144386
Short name	T965
Test name
Test status
Simulation time	15819200 ps
CPU time	13.86 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:07:14 PM PDT 24
Peak memory	282780 kb
Host	smart-47526054-15e6-4114-b0fa-6dbcb7d59a39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409144386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.3409144386
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.1616878793
Short name	T12
Test name
Test status
Simulation time	16080200 ps
CPU time	22.06 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	273560 kb
Host	smart-c810a96a-cf26-4eb1-a773-0b387a7fe2b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616878793 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.1616878793
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.1682376270
Short name	T25
Test name
Test status
Simulation time	10883133400 ps
CPU time	2239.15 seconds
Started	Jul 25 05:07:00 PM PDT 24
Finished	Jul 25 05:44:20 PM PDT 24
Peak memory	262508 kb
Host	smart-31ea4c94-9670-4ed0-81af-ffdf6eb36caa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1682376270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.1682376270
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.3708112038
Short name	T789
Test name
Test status
Simulation time	5252845100 ps
CPU time	792.66 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:20:13 PM PDT 24
Peak memory	272516 kb
Host	smart-d1dccab8-c353-4d65-926d-197e9f78f88e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708112038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3708112038
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.320995064
Short name	T52
Test name
Test status
Simulation time	1065874800 ps
CPU time	20.29 seconds
Started	Jul 25 05:07:00 PM PDT 24
Finished	Jul 25 05:07:20 PM PDT 24
Peak memory	262292 kb
Host	smart-ba49e3dc-2bc5-434f-98f4-22a8026e97f2
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320995064 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.320995064
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2585059343
Short name	T679
Test name
Test status
Simulation time	10081400000 ps
CPU time	44.02 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:07:44 PM PDT 24
Peak memory	266464 kb
Host	smart-99ca4e50-6794-4e21-8d6f-c10b0525c0f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585059343 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2585059343
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2465449670
Short name	T667
Test name
Test status
Simulation time	18823400 ps
CPU time	13.5 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	259820 kb
Host	smart-785a1c4c-c160-4e3d-a0e1-6b11c8f08239
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465449670 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2465449670
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.2544424967
Short name	T797
Test name
Test status
Simulation time	80132371400 ps
CPU time	858.76 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:21:20 PM PDT 24
Peak memory	263684 kb
Host	smart-f2f64383-1556-4188-8b1e-39fc363a7ede
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544424967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.flash_ctrl_hw_rma_reset.2544424967
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1666093522
Short name	T295
Test name
Test status
Simulation time	2580060700 ps
CPU time	106.25 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:08:44 PM PDT 24
Peak memory	260772 kb
Host	smart-d8f9f751-c701-430d-93e5-5e8c94745c62
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666093522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.1666093522
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.1743363299
Short name	T710
Test name
Test status
Simulation time	10328015800 ps
CPU time	222.83 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:10:41 PM PDT 24
Peak memory	290628 kb
Host	smart-4badcaa7-7b59-4466-bbef-565003bece2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743363299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_intr_rd.1743363299
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.4180772566
Short name	T326
Test name
Test status
Simulation time	8627867200 ps
CPU time	193.99 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:10:12 PM PDT 24
Peak memory	289676 kb
Host	smart-b3c57ae0-ac4c-4332-95c0-024398d73fa5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180772566 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.4180772566
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.3529043438
Short name	T28
Test name
Test status
Simulation time	3941797900 ps
CPU time	60.7 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:59 PM PDT 24
Peak memory	264868 kb
Host	smart-2d71de3c-772e-464e-82fb-86d92d2a75dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529043438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.3529043438
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.948292366
Short name	T1039
Test name
Test status
Simulation time	25007907500 ps
CPU time	216.99 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:10:38 PM PDT 24
Peak memory	264940 kb
Host	smart-2b0c9818-734b-4d35-8cf7-80674ea5f485
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948 292366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.948292366
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.827060843
Short name	T421
Test name
Test status
Simulation time	992983700 ps
CPU time	87.53 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:08:26 PM PDT 24
Peak memory	260324 kb
Host	smart-2c5d201b-a9e2-44d5-ae02-7b344add1eca
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827060843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.827060843
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1713748042
Short name	T1106
Test name
Test status
Simulation time	45918800 ps
CPU time	13.4 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:07:23 PM PDT 24
Peak memory	264520 kb
Host	smart-3800bca0-b401-4dae-b3e2-aed66f111e2d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713748042 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1713748042
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.926917286
Short name	T78
Test name
Test status
Simulation time	70279534900 ps
CPU time	518.48 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:15:38 PM PDT 24
Peak memory	274380 kb
Host	smart-5452a327-b152-4bd2-91af-af78e453af45
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926917286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.926917286
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.3540714711
Short name	T180
Test name
Test status
Simulation time	41983800 ps
CPU time	111.08 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:08:52 PM PDT 24
Peak memory	259952 kb
Host	smart-048cef3b-b84e-4551-9e45-2d8539b50dc4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540714711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.3540714711
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.1750982875
Short name	T505
Test name
Test status
Simulation time	50542200 ps
CPU time	69.11 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:08:09 PM PDT 24
Peak memory	262976 kb
Host	smart-51aeb3b7-e487-495c-904b-02b35ca2e032
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1750982875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1750982875
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.1631202782
Short name	T609
Test name
Test status
Simulation time	44364246500 ps
CPU time	192.59 seconds
Started	Jul 25 05:07:02 PM PDT 24
Finished	Jul 25 05:10:14 PM PDT 24
Peak memory	260256 kb
Host	smart-312982f2-27ab-4224-a8b8-170aa9388e95
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631202782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_prog_reset.1631202782
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.4145282880
Short name	T154
Test name
Test status
Simulation time	1888319600 ps
CPU time	1442.11 seconds
Started	Jul 25 05:07:03 PM PDT 24
Finished	Jul 25 05:31:05 PM PDT 24
Peak memory	286440 kb
Host	smart-5172ce2a-cc1c-426c-a9ec-5275b76a874b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145282880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.4145282880
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.1332761823
Short name	T675
Test name
Test status
Simulation time	69172100 ps
CPU time	33.6 seconds
Started	Jul 25 05:07:00 PM PDT 24
Finished	Jul 25 05:07:34 PM PDT 24
Peak memory	275372 kb
Host	smart-bcc6cd13-9937-4e8d-b3be-13bc9635dbd6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332761823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_re_evict.1332761823
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.2722223410
Short name	T388
Test name
Test status
Simulation time	4171746000 ps
CPU time	140.79 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:09:21 PM PDT 24
Peak memory	281496 kb
Host	smart-2083287b-b301-4a27-9c4f-72ff16c8c70f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722223410 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.2722223410
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.1476944604
Short name	T102
Test name
Test status
Simulation time	2866894400 ps
CPU time	150.06 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:09:31 PM PDT 24
Peak memory	281468 kb
Host	smart-33dcae65-d9a4-4078-8666-645d05b55164
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476944604 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.1476944604
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.1202251073
Short name	T970
Test name
Test status
Simulation time	4248356800 ps
CPU time	595.02 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:16:54 PM PDT 24
Peak memory	313908 kb
Host	smart-2befc224-034b-4b55-9312-6988fe4915f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202251073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.flash_ctrl_rw.1202251073
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1721499522
Short name	T533
Test name
Test status
Simulation time	29630000 ps
CPU time	30.63 seconds
Started	Jul 25 05:06:58 PM PDT 24
Finished	Jul 25 05:07:28 PM PDT 24
Peak memory	273292 kb
Host	smart-d08ba90d-6250-4055-8671-491c32337e80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721499522 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1721499522
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.3638258122
Short name	T266
Test name
Test status
Simulation time	9814517700 ps
CPU time	621.39 seconds
Started	Jul 25 05:07:02 PM PDT 24
Finished	Jul 25 05:17:24 PM PDT 24
Peak memory	312268 kb
Host	smart-3c2c6b87-bceb-438c-b264-78c525b00096
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638258122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s err.3638258122
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.419864271
Short name	T410
Test name
Test status
Simulation time	22266637700 ps
CPU time	69.95 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:08:18 PM PDT 24
Peak memory	264504 kb
Host	smart-3993f453-9d3c-4673-9805-c1f0a61594ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419864271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.419864271
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.3269874414
Short name	T1007
Test name
Test status
Simulation time	52974200 ps
CPU time	191.77 seconds
Started	Jul 25 05:06:59 PM PDT 24
Finished	Jul 25 05:10:11 PM PDT 24
Peak memory	279888 kb
Host	smart-13a85776-881b-4ab9-9b94-057953016159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269874414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3269874414
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.995129314
Short name	T529
Test name
Test status
Simulation time	7685405100 ps
CPU time	180.58 seconds
Started	Jul 25 05:07:02 PM PDT 24
Finished	Jul 25 05:10:03 PM PDT 24
Peak memory	258996 kb
Host	smart-cffcba83-cdb0-40f3-96f6-bca1255f0588
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995129314 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 7.flash_ctrl_wo.995129314
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.4249559694
Short name	T925
Test name
Test status
Simulation time	35731400 ps
CPU time	15.78 seconds
Started	Jul 25 05:10:37 PM PDT 24
Finished	Jul 25 05:10:53 PM PDT 24
Peak memory	282984 kb
Host	smart-6d50bf82-12a2-424b-8e00-2a213747257e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249559694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4249559694
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.3142192436
Short name	T468
Test name
Test status
Simulation time	43250500 ps
CPU time	134.06 seconds
Started	Jul 25 05:10:38 PM PDT 24
Finished	Jul 25 05:12:52 PM PDT 24
Peak memory	265300 kb
Host	smart-2e804974-9384-495b-a0de-3679c742016e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142192436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o tp_reset.3142192436
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.3940903540
Short name	T118
Test name
Test status
Simulation time	41064800 ps
CPU time	13.56 seconds
Started	Jul 25 05:10:50 PM PDT 24
Finished	Jul 25 05:11:04 PM PDT 24
Peak memory	282896 kb
Host	smart-02dbdbee-70fa-415f-8cf6-9f27323621ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940903540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3940903540
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.1702408587
Short name	T175
Test name
Test status
Simulation time	71579200 ps
CPU time	132.61 seconds
Started	Jul 25 05:10:56 PM PDT 24
Finished	Jul 25 05:13:09 PM PDT 24
Peak memory	259996 kb
Host	smart-de92940b-32fb-4913-b9b3-baed09f79a6f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702408587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o tp_reset.1702408587
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.2372362345
Short name	T508
Test name
Test status
Simulation time	17142400 ps
CPU time	16.17 seconds
Started	Jul 25 05:10:46 PM PDT 24
Finished	Jul 25 05:11:02 PM PDT 24
Peak memory	284104 kb
Host	smart-8518e38e-9a08-40f8-82dd-9deb6c48b774
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372362345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2372362345
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.1100673580
Short name	T389
Test name
Test status
Simulation time	50096100 ps
CPU time	136.73 seconds
Started	Jul 25 05:10:45 PM PDT 24
Finished	Jul 25 05:13:02 PM PDT 24
Peak memory	264248 kb
Host	smart-87c505f5-1b3f-4cac-a31f-d19ddc3c9170
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100673580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.1100673580
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.3995085472
Short name	T128
Test name
Test status
Simulation time	228761800 ps
CPU time	15.59 seconds
Started	Jul 25 05:10:46 PM PDT 24
Finished	Jul 25 05:11:02 PM PDT 24
Peak memory	282712 kb
Host	smart-8d72964e-5923-4bcf-9322-fba1fad65d3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995085472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3995085472
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.1517359628
Short name	T85
Test name
Test status
Simulation time	38453200 ps
CPU time	135.23 seconds
Started	Jul 25 05:10:47 PM PDT 24
Finished	Jul 25 05:13:02 PM PDT 24
Peak memory	260740 kb
Host	smart-9582312e-0cb2-4e6a-945e-99773a326660
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517359628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.1517359628
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.1987083206
Short name	T916
Test name
Test status
Simulation time	22417000 ps
CPU time	13.21 seconds
Started	Jul 25 05:10:56 PM PDT 24
Finished	Jul 25 05:11:09 PM PDT 24
Peak memory	282888 kb
Host	smart-79f39ee9-bd7c-47e8-8dbb-14cb7459e4c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987083206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1987083206
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.2955895816
Short name	T975
Test name
Test status
Simulation time	258151300 ps
CPU time	131.21 seconds
Started	Jul 25 05:10:47 PM PDT 24
Finished	Jul 25 05:12:59 PM PDT 24
Peak memory	260016 kb
Host	smart-631eb34d-a4b2-410d-b9ab-3396e3e53ccf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955895816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o tp_reset.2955895816
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.3366050962
Short name	T430
Test name
Test status
Simulation time	15935900 ps
CPU time	15.99 seconds
Started	Jul 25 05:10:47 PM PDT 24
Finished	Jul 25 05:11:03 PM PDT 24
Peak memory	282856 kb
Host	smart-08d8936d-ba55-49e5-adad-6cc9b2dadb12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366050962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3366050962
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.3240324298
Short name	T1008
Test name
Test status
Simulation time	42253400 ps
CPU time	109.95 seconds
Started	Jul 25 05:10:46 PM PDT 24
Finished	Jul 25 05:12:36 PM PDT 24
Peak memory	264888 kb
Host	smart-80e466fc-1b6b-4acf-ab35-9e63fd5445c8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240324298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o tp_reset.3240324298
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.3257286434
Short name	T569
Test name
Test status
Simulation time	28353200 ps
CPU time	15.84 seconds
Started	Jul 25 05:10:47 PM PDT 24
Finished	Jul 25 05:11:03 PM PDT 24
Peak memory	274752 kb
Host	smart-c7e3eb7e-b4f4-4334-aa1f-1b73919e1255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257286434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3257286434
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.3573314881
Short name	T806
Test name
Test status
Simulation time	196353600 ps
CPU time	132.21 seconds
Started	Jul 25 05:10:53 PM PDT 24
Finished	Jul 25 05:13:05 PM PDT 24
Peak memory	265124 kb
Host	smart-4b98bb62-63c2-4fdb-9388-cb3c40cf1814
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573314881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o tp_reset.3573314881
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.3055430572
Short name	T722
Test name
Test status
Simulation time	14294600 ps
CPU time	16.3 seconds
Started	Jul 25 05:10:47 PM PDT 24
Finished	Jul 25 05:11:03 PM PDT 24
Peak memory	284168 kb
Host	smart-2527fbbe-229f-4977-9b64-42fb16417d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055430572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3055430572
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.1086344928
Short name	T859
Test name
Test status
Simulation time	195695600 ps
CPU time	132.67 seconds
Started	Jul 25 05:10:48 PM PDT 24
Finished	Jul 25 05:13:01 PM PDT 24
Peak memory	264036 kb
Host	smart-741db1cf-08b0-45c8-9302-6bcce12d5dda
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086344928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.1086344928
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.3120123628
Short name	T851
Test name
Test status
Simulation time	48036900 ps
CPU time	15.9 seconds
Started	Jul 25 05:10:46 PM PDT 24
Finished	Jul 25 05:11:02 PM PDT 24
Peak memory	274732 kb
Host	smart-c6bf852b-34a6-4099-af5f-31631cf3946d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120123628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3120123628
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.329681563
Short name	T544
Test name
Test status
Simulation time	303099100 ps
CPU time	132.02 seconds
Started	Jul 25 05:10:48 PM PDT 24
Finished	Jul 25 05:13:00 PM PDT 24
Peak memory	260276 kb
Host	smart-93b7bc86-7b20-4289-a825-662f730edd82
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329681563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot p_reset.329681563
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.3961822296
Short name	T769
Test name
Test status
Simulation time	17983700 ps
CPU time	15.81 seconds
Started	Jul 25 05:10:46 PM PDT 24
Finished	Jul 25 05:11:02 PM PDT 24
Peak memory	284072 kb
Host	smart-f49f43b9-74ce-42b6-8b12-fd96d6bf1f3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961822296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3961822296
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.3672571384
Short name	T178
Test name
Test status
Simulation time	42124100 ps
CPU time	130.82 seconds
Started	Jul 25 05:10:47 PM PDT 24
Finished	Jul 25 05:12:58 PM PDT 24
Peak memory	260928 kb
Host	smart-caa463d2-5ea3-498e-a06d-669b10ae94d0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672571384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.3672571384
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.2903152269
Short name	T464
Test name
Test status
Simulation time	300588800 ps
CPU time	13.35 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	257896 kb
Host	smart-72ae9d36-59cd-4016-bcaa-6f2aae7bc59b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903152269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.2 903152269
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.3768187126
Short name	T821
Test name
Test status
Simulation time	13812400 ps
CPU time	13.16 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:07:24 PM PDT 24
Peak memory	274656 kb
Host	smart-10c3fded-9cc2-4364-b190-f4a2535cd3bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768187126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3768187126
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.609747644
Short name	T1012
Test name
Test status
Simulation time	13663300 ps
CPU time	22.53 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:07:31 PM PDT 24
Peak memory	266232 kb
Host	smart-f0f930dc-c2b6-4f1f-b3bb-63a1ae1f9dc2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609747644 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.609747644
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.2743494680
Short name	T482
Test name
Test status
Simulation time	3932999500 ps
CPU time	2162.68 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:43:10 PM PDT 24
Peak memory	264896 kb
Host	smart-7d7ac539-a1e0-40be-8e68-ae7695e62585
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2743494680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2743494680
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.2989864075
Short name	T539
Test name
Test status
Simulation time	619780900 ps
CPU time	814.81 seconds
Started	Jul 25 05:10:24 PM PDT 24
Finished	Jul 25 05:23:59 PM PDT 24
Peak memory	270180 kb
Host	smart-166a8293-6c44-4941-b595-45caeb6e24ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989864075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2989864075
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2755116899
Short name	T815
Test name
Test status
Simulation time	10039615400 ps
CPU time	52.57 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:08:01 PM PDT 24
Peak memory	282072 kb
Host	smart-9a2dd970-25ed-4e36-8d6b-8843874d4ba8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755116899 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2755116899
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.943897072
Short name	T958
Test name
Test status
Simulation time	15346200 ps
CPU time	13.85 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	264436 kb
Host	smart-5d814e04-2968-422a-971e-331e75dd5e14
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943897072 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.943897072
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2660300423
Short name	T908
Test name
Test status
Simulation time	80136461800 ps
CPU time	782.35 seconds
Started	Jul 25 05:07:02 PM PDT 24
Finished	Jul 25 05:20:05 PM PDT 24
Peak memory	260628 kb
Host	smart-575e5ef8-65aa-4469-b544-3fcabfb45554
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660300423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.2660300423
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.418048049
Short name	T782
Test name
Test status
Simulation time	15333638500 ps
CPU time	125.8 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:09:16 PM PDT 24
Peak memory	260780 kb
Host	smart-f316a160-872f-453b-9899-89d51f475fb8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418048049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw _sec_otp.418048049
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.820017153
Short name	T127
Test name
Test status
Simulation time	5721122400 ps
CPU time	138.04 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:09:29 PM PDT 24
Peak memory	289792 kb
Host	smart-713ec642-a6f3-446f-ac34-2eee831965a1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820017153 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.820017153
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.925121411
Short name	T732
Test name
Test status
Simulation time	3086261900 ps
CPU time	62.08 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:08:12 PM PDT 24
Peak memory	260784 kb
Host	smart-afa5936f-ebe9-42c4-ba1e-35d285e08a10
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925121411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.flash_ctrl_intr_wr.925121411
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.398685777
Short name	T16
Test name
Test status
Simulation time	28044135900 ps
CPU time	186.42 seconds
Started	Jul 25 05:07:11 PM PDT 24
Finished	Jul 25 05:10:17 PM PDT 24
Peak memory	264936 kb
Host	smart-e00a4d49-4b44-4692-a2e0-342b2a089207
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398 685777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.398685777
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.3139227535
Short name	T967
Test name
Test status
Simulation time	1015264500 ps
CPU time	81.89 seconds
Started	Jul 25 05:07:11 PM PDT 24
Finished	Jul 25 05:08:33 PM PDT 24
Peak memory	260552 kb
Host	smart-26268391-6994-4a9b-b203-a8d06d3625a3
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139227535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3139227535
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.255159347
Short name	T162
Test name
Test status
Simulation time	121011900 ps
CPU time	13.68 seconds
Started	Jul 25 05:07:11 PM PDT 24
Finished	Jul 25 05:07:25 PM PDT 24
Peak memory	264576 kb
Host	smart-2e9c2111-ba84-455d-b8d8-74f4c720c62b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255159347 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.255159347
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.1316367477
Short name	T1024
Test name
Test status
Simulation time	49564593400 ps
CPU time	290.29 seconds
Started	Jul 25 05:07:12 PM PDT 24
Finished	Jul 25 05:12:02 PM PDT 24
Peak memory	274628 kb
Host	smart-05f54777-6fd9-452c-9195-dd1156a6aec4
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316367477 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.1316367477
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.1535700840
Short name	T305
Test name
Test status
Simulation time	261857500 ps
CPU time	130.3 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:09:18 PM PDT 24
Peak memory	259948 kb
Host	smart-ca2fe91d-b4bc-4f09-8860-f2a0c3464151
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535700840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.1535700840
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.2128127753
Short name	T196
Test name
Test status
Simulation time	23075897400 ps
CPU time	533.5 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:16:01 PM PDT 24
Peak memory	262860 kb
Host	smart-b089d089-54a5-40e6-a842-a5e0ae92d2d6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2128127753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2128127753
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.3163173841
Short name	T1050
Test name
Test status
Simulation time	37030300 ps
CPU time	13.54 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:07:21 PM PDT 24
Peak memory	258992 kb
Host	smart-fe64a679-7e8d-4dd0-ac97-86193cce760c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163173841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.3163173841
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.1732554670
Short name	T82
Test name
Test status
Simulation time	429400600 ps
CPU time	699.42 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:18:49 PM PDT 24
Peak memory	285708 kb
Host	smart-57f6f2b1-400d-4118-a136-9b05c0b2c39a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732554670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1732554670
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.3532427824
Short name	T787
Test name
Test status
Simulation time	88525200 ps
CPU time	34.79 seconds
Started	Jul 25 05:07:12 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	275328 kb
Host	smart-9b2eac7f-da1d-4f1c-bd0e-5713b4c82881
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532427824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.3532427824
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.1699744724
Short name	T612
Test name
Test status
Simulation time	2120671200 ps
CPU time	127.9 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:09:15 PM PDT 24
Peak memory	291312 kb
Host	smart-c28f8f18-9a29-459f-ae47-5d3e202ea64f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699744724 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.1699744724
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.1459955127
Short name	T198
Test name
Test status
Simulation time	594190300 ps
CPU time	129.42 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:09:18 PM PDT 24
Peak memory	281548 kb
Host	smart-44de5e28-22e9-4fed-acd3-4efafb2cf3ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1459955127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1459955127
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.250262729
Short name	T37
Test name
Test status
Simulation time	11146831700 ps
CPU time	169.56 seconds
Started	Jul 25 05:07:07 PM PDT 24
Finished	Jul 25 05:09:57 PM PDT 24
Peak memory	281564 kb
Host	smart-7f073ef7-880c-43a4-8688-e5c8f8064889
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250262729 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.250262729
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.2968058787
Short name	T550
Test name
Test status
Simulation time	25278685900 ps
CPU time	543.16 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:16:13 PM PDT 24
Peak memory	309732 kb
Host	smart-2e1a61c8-64f6-4b47-a35a-f2e5254f25ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968058787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.flash_ctrl_rw.2968058787
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.2420106710
Short name	T199
Test name
Test status
Simulation time	3097352600 ps
CPU time	547.18 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:16:15 PM PDT 24
Peak memory	314252 kb
Host	smart-72dd5c65-6110-463a-9a94-2948883da0e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420106710 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_rw_derr.2420106710
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.2532660000
Short name	T384
Test name
Test status
Simulation time	27911700 ps
CPU time	31.42 seconds
Started	Jul 25 05:07:09 PM PDT 24
Finished	Jul 25 05:07:40 PM PDT 24
Peak memory	268140 kb
Host	smart-8207368a-05f6-49bb-96d6-378d93e6378a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532660000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_rw_evict.2532660000
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2217509130
Short name	T772
Test name
Test status
Simulation time	26734600 ps
CPU time	30.86 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:07:48 PM PDT 24
Peak memory	275320 kb
Host	smart-df23f2cd-07b6-4b07-a32c-d4dd49178434
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217509130 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.2217509130
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.2579647647
Short name	T1080
Test name
Test status
Simulation time	3609268000 ps
CPU time	615.03 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:17:24 PM PDT 24
Peak memory	313668 kb
Host	smart-367d95e6-a7c4-4af1-9430-479101edac66
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579647647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s err.2579647647
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.98250646
Short name	T256
Test name
Test status
Simulation time	1885731500 ps
CPU time	69.45 seconds
Started	Jul 25 05:07:09 PM PDT 24
Finished	Jul 25 05:08:19 PM PDT 24
Peak memory	262832 kb
Host	smart-7a9c9425-6c2b-4be1-a05f-4fc06bd3ef45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98250646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.98250646
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.1152880508
Short name	T554
Test name
Test status
Simulation time	24748300 ps
CPU time	75.93 seconds
Started	Jul 25 05:07:01 PM PDT 24
Finished	Jul 25 05:08:17 PM PDT 24
Peak memory	276268 kb
Host	smart-fd30d5c3-1e8c-49ab-b499-6e3927424cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152880508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1152880508
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.2160764292
Short name	T578
Test name
Test status
Simulation time	4259721200 ps
CPU time	221.29 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:10:52 PM PDT 24
Peak memory	259748 kb
Host	smart-69def10c-97aa-4098-9f0d-4713b958b7fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160764292 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_wo.2160764292
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.2233073372
Short name	T434
Test name
Test status
Simulation time	143091900 ps
CPU time	13.72 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:07:30 PM PDT 24
Peak memory	264868 kb
Host	smart-5561a9e4-fee8-48a2-b7af-0a1929548c1a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233073372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2 233073372
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.3396847316
Short name	T790
Test name
Test status
Simulation time	51640900 ps
CPU time	15.98 seconds
Started	Jul 25 05:07:21 PM PDT 24
Finished	Jul 25 05:07:37 PM PDT 24
Peak memory	284184 kb
Host	smart-6094cd0d-0435-43c2-b660-6daa4f250709
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396847316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3396847316
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.632219115
Short name	T746
Test name
Test status
Simulation time	15728600 ps
CPU time	22.11 seconds
Started	Jul 25 05:07:18 PM PDT 24
Finished	Jul 25 05:07:40 PM PDT 24
Peak memory	273288 kb
Host	smart-bf030c04-cb46-4e6e-a3a4-cb29abaad5d4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632219115 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.632219115
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.2136863960
Short name	T570
Test name
Test status
Simulation time	17468639900 ps
CPU time	2464.6 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:48:15 PM PDT 24
Peak memory	265016 kb
Host	smart-99ad8749-67d5-4db3-b6bc-120581d26676
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2136863960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.2136863960
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.2345703958
Short name	T200
Test name
Test status
Simulation time	702491000 ps
CPU time	889.45 seconds
Started	Jul 25 05:07:13 PM PDT 24
Finished	Jul 25 05:22:02 PM PDT 24
Peak memory	273088 kb
Host	smart-fc99684b-fd2a-4918-ade6-261330842171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345703958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2345703958
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.3502715997
Short name	T53
Test name
Test status
Simulation time	1187772100 ps
CPU time	28.54 seconds
Started	Jul 25 05:07:13 PM PDT 24
Finished	Jul 25 05:07:42 PM PDT 24
Peak memory	262176 kb
Host	smart-228192a1-c673-41f8-b92c-2dc4096e132d
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502715997 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3502715997
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.912706672
Short name	T1044
Test name
Test status
Simulation time	10019793400 ps
CPU time	84 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:08:40 PM PDT 24
Peak memory	311096 kb
Host	smart-f214680c-a3bd-481a-a6ae-48e235d33c5c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912706672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.912706672
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3243662714
Short name	T270
Test name
Test status
Simulation time	81541200 ps
CPU time	13.49 seconds
Started	Jul 25 05:07:18 PM PDT 24
Finished	Jul 25 05:07:32 PM PDT 24
Peak memory	258340 kb
Host	smart-f200d630-6545-4c62-9396-0fed22e2f1c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243662714 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3243662714
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.2689880441
Short name	T932
Test name
Test status
Simulation time	7273322000 ps
CPU time	159.89 seconds
Started	Jul 25 05:07:09 PM PDT 24
Finished	Jul 25 05:09:49 PM PDT 24
Peak memory	263032 kb
Host	smart-57eb0220-d747-4268-956e-63e4f3ed71b9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689880441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h w_sec_otp.2689880441
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.1456828138
Short name	T594
Test name
Test status
Simulation time	1197231300 ps
CPU time	128.4 seconds
Started	Jul 25 05:07:15 PM PDT 24
Finished	Jul 25 05:09:24 PM PDT 24
Peak memory	293788 kb
Host	smart-d3ea8cc2-eb33-4849-a8df-57d65d79e6a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456828138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_intr_rd.1456828138
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2335897556
Short name	T750
Test name
Test status
Simulation time	32267903600 ps
CPU time	403.86 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:14:00 PM PDT 24
Peak memory	291704 kb
Host	smart-0820c22f-fa83-4791-92c2-f36920802371
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335897556 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.2335897556
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.1720722983
Short name	T1031
Test name
Test status
Simulation time	1874014000 ps
CPU time	62.15 seconds
Started	Jul 25 05:07:20 PM PDT 24
Finished	Jul 25 05:08:23 PM PDT 24
Peak memory	260236 kb
Host	smart-d4b84f41-f996-457d-8ad8-2c6617f142a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720722983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.1720722983
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.400188866
Short name	T822
Test name
Test status
Simulation time	18782994700 ps
CPU time	171.22 seconds
Started	Jul 25 05:07:16 PM PDT 24
Finished	Jul 25 05:10:07 PM PDT 24
Peak memory	260052 kb
Host	smart-600b00d0-af13-4c62-88ec-6725a44fadd2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400 188866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.400188866
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.3461109750
Short name	T972
Test name
Test status
Simulation time	4343299500 ps
CPU time	70.24 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:08:19 PM PDT 24
Peak memory	260356 kb
Host	smart-1bacd78d-014c-48cb-9ced-50825c845826
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461109750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3461109750
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.2416575560
Short name	T277
Test name
Test status
Simulation time	38000900 ps
CPU time	13.56 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:07:30 PM PDT 24
Peak memory	260336 kb
Host	smart-074348f9-7dfc-4e39-8dff-7d78586237dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416575560 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.2416575560
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.4127610085
Short name	T145
Test name
Test status
Simulation time	33857279100 ps
CPU time	242 seconds
Started	Jul 25 05:07:11 PM PDT 24
Finished	Jul 25 05:11:13 PM PDT 24
Peak memory	274220 kb
Host	smart-2199f175-6eff-467b-bcb8-29976c5e7126
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127610085 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.4127610085
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.27225556
Short name	T1064
Test name
Test status
Simulation time	156036700 ps
CPU time	131.2 seconds
Started	Jul 25 05:07:11 PM PDT 24
Finished	Jul 25 05:09:22 PM PDT 24
Peak memory	259712 kb
Host	smart-2db0739f-0be5-4dfd-87fa-14813461e0e2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27225556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_ reset.27225556
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.2419479891
Short name	T479
Test name
Test status
Simulation time	7122339100 ps
CPU time	290.43 seconds
Started	Jul 25 05:07:09 PM PDT 24
Finished	Jul 25 05:12:00 PM PDT 24
Peak memory	262904 kb
Host	smart-77d8e6fe-2dbb-45a5-80c0-366da2476eb6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2419479891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2419479891
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.3102040657
Short name	T583
Test name
Test status
Simulation time	4290467100 ps
CPU time	185.28 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:10:22 PM PDT 24
Peak memory	264860 kb
Host	smart-c5fcaa93-bae1-40ec-bbc9-6000f7f1c783
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102040657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.flash_ctrl_prog_reset.3102040657
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.588655988
Short name	T955
Test name
Test status
Simulation time	1469288500 ps
CPU time	747.19 seconds
Started	Jul 25 05:07:13 PM PDT 24
Finished	Jul 25 05:19:40 PM PDT 24
Peak memory	284672 kb
Host	smart-221bbc37-1e6d-478b-9283-84e7dda8e053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588655988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.588655988
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.1028873933
Short name	T501
Test name
Test status
Simulation time	61729400 ps
CPU time	34.86 seconds
Started	Jul 25 05:07:18 PM PDT 24
Finished	Jul 25 05:07:53 PM PDT 24
Peak memory	275268 kb
Host	smart-ed275989-1489-4156-b9c1-a480819708d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028873933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.1028873933
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.3584650375
Short name	T536
Test name
Test status
Simulation time	493649900 ps
CPU time	110.81 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:08:59 PM PDT 24
Peak memory	280768 kb
Host	smart-2639e694-ed14-49f8-a12e-adae88cb3a76
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584650375 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.3584650375
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.3966970066
Short name	T721
Test name
Test status
Simulation time	2128549100 ps
CPU time	109.03 seconds
Started	Jul 25 05:07:10 PM PDT 24
Finished	Jul 25 05:08:59 PM PDT 24
Peak memory	281564 kb
Host	smart-486d4c25-cbaf-4487-9567-7fa4b45c98be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966970066 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3966970066
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.3870061499
Short name	T310
Test name
Test status
Simulation time	11807747600 ps
CPU time	524.76 seconds
Started	Jul 25 05:07:09 PM PDT 24
Finished	Jul 25 05:15:54 PM PDT 24
Peak memory	314180 kb
Host	smart-ed88d8ec-1c85-49ad-9751-2f4b95fa95fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870061499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.3870061499
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict.3508146239
Short name	T692
Test name
Test status
Simulation time	27328300 ps
CPU time	27.97 seconds
Started	Jul 25 05:07:17 PM PDT 24
Finished	Jul 25 05:07:45 PM PDT 24
Peak memory	275372 kb
Host	smart-cec68dbc-6446-4ddb-a4e7-420c1c4901bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508146239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_rw_evict.3508146239
Directory	/workspace/9.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3637865475
Short name	T712
Test name
Test status
Simulation time	68890500 ps
CPU time	31.09 seconds
Started	Jul 25 05:07:15 PM PDT 24
Finished	Jul 25 05:07:47 PM PDT 24
Peak memory	268164 kb
Host	smart-4912e573-e43a-45c9-9e6e-ff352093222b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637865475 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3637865475
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.2229383364
Short name	T472
Test name
Test status
Simulation time	3659010600 ps
CPU time	63.7 seconds
Started	Jul 25 05:07:22 PM PDT 24
Finished	Jul 25 05:08:25 PM PDT 24
Peak memory	263496 kb
Host	smart-c9869df1-fa7a-499b-94d4-4d8cc2c5ad9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229383364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2229383364
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.2625159448
Short name	T984
Test name
Test status
Simulation time	23518100 ps
CPU time	118.7 seconds
Started	Jul 25 05:07:09 PM PDT 24
Finished	Jul 25 05:09:08 PM PDT 24
Peak memory	277052 kb
Host	smart-4958709a-c513-43d4-86d7-ded6bf707858
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625159448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2625159448
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.3350510019
Short name	T296
Test name
Test status
Simulation time	6245462800 ps
CPU time	194.22 seconds
Started	Jul 25 05:07:08 PM PDT 24
Finished	Jul 25 05:10:23 PM PDT 24
Peak memory	259620 kb
Host	smart-0de2906e-240d-4dd5-aed1-973f057a9448
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350510019 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.3350510019
Directory	/workspace/9.flash_ctrl_wo/latest

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