Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25509311	1		T1	19		T2	10172		T3	73
full_word	7566869	1		T2	9391		T3	119		T4	54498

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33075890	1		T1	19		T2	19563		T3	192
auto[TlIntgErrCmd]	99	1		T233	8		T234	4		T250	9
auto[TlIntgErrData]	94	1		T233	6		T234	4		T250	7
auto[TlIntgErrBoth]	97	1		T233	6		T234	2		T250	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28619062	1		T1	18		T2	11781		T3	91
auto[1]	4457118	1		T1	1		T2	7782		T3	101

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24805431	1		T1	18		T2	9167		T3	60
auto[TlIntgErrNone]	partial	auto[1]	703617	1		T1	1		T2	1005		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	3813493	1		T2	2614		T3	31		T4	42599
auto[TlIntgErrNone]	full_word	auto[1]	3753349	1		T2	6777		T3	88		T4	11899
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T233	5		T234	1		T250	6
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T233	2		T234	2		T250	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1		T234	1		T283	1		T287	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T233	1		T323	1		T360	2
auto[TlIntgErrData]	partial	auto[0]	37	1		T233	2		T234	1		T250	3
auto[TlIntgErrData]	partial	auto[1]	50	1		T233	4		T234	2		T250	4
auto[TlIntgErrData]	full_word	auto[0]	2	1		T234	1		T361	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T323	1		T359	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T233	4		T250	2		T252	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T233	1		T234	2		T250	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T250	1		T299	1		T298	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T233	1		T283	1		T359	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19512	1		T69	13		T70	94		T100	98
full_word	3828836	1		T4	16641		T5	16748		T6	41353

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3848081	1		T4	16641		T5	16748		T6	41353
auto[TlIntgErrCmd]	83	1		T233	7		T234	3		T250	7
auto[TlIntgErrData]	94	1		T233	7		T234	4		T250	6
auto[TlIntgErrBoth]	90	1		T233	5		T234	3		T250	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3822920	1		T4	16641		T5	16748		T6	41353
auto[1]	25428	1		T69	22		T70	104		T100	113

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1196	1		T70	5		T100	7		T235	1
auto[TlIntgErrNone]	partial	auto[1]	18084	1		T69	13		T70	89		T100	91
auto[TlIntgErrNone]	full_word	auto[0]	3821607	1		T4	16641		T5	16748		T6	41353
auto[TlIntgErrNone]	full_word	auto[1]	7194	1		T69	9		T70	15		T100	22
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T233	1		T234	1		T250	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T233	5		T234	1		T250	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T234	1		T250	1		T357	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T233	1		T250	2		T283	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T233	3		T234	1		T250	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T233	2		T234	3		T250	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T233	1		T252	1		T363	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T233	1		T287	3		T364	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T233	2		T250	4		T299	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T233	2		T234	2		T250	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T233	1		T252	1		T287	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T234	1		T283	1		T358	1