Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1568610248	1565380064	0	0
CheckNGreaterZero_A	4252	4252	0	0
GntImpliesReady_A	1568610248	405318321	0	0
GntImpliesValid_A	1568610248	405318321	0	0
GrantKnown_A	1568610248	1565380064	0	0
IdxKnown_A	1568610248	1565380064	0	0
IndexIsCorrect_A	1568610248	405318321	0	0
NoReadyValidNoGrant_A	1568610248	170944421	0	0
Priority_A	1568610248	429438086	0	0
ReadyAndValidImplyGrant_A	1568610248	405318321	0	0
ReqAndReadyImplyGrant_A	1568610248	405318321	0	0
ReqImpliesValid_A	1568610248	429438086	0	0
ValidKnown_A	1568610248	1565380064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	1565380064	0	0
T1	6100	5728	0	0
T2	759248	758852	0	0
T3	5440	5104	0	0
T4	455004	454956	0	0
T5	308760	308252	0	0
T6	1593940	1593736	0	0
T10	4280	3932	0	0
T18	10280	9940	0	0
T19	14904	11988	0	0
T20	4876	4624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4252	4252	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	405318321	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	81798	0	0
T5	308760	49814	0	0
T6	1593940	519268	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	42536	0	0
T53	968	12	0	0
T63	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	405318321	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	81798	0	0
T5	308760	49814	0	0
T6	1593940	519268	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	42536	0	0
T53	968	12	0	0
T63	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	1565380064	0	0
T1	6100	5728	0	0
T2	759248	758852	0	0
T3	5440	5104	0	0
T4	455004	454956	0	0
T5	308760	308252	0	0
T6	1593940	1593736	0	0
T10	4280	3932	0	0
T18	10280	9940	0	0
T19	14904	11988	0	0
T20	4876	4624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	1565380064	0	0
T1	6100	5728	0	0
T2	759248	758852	0	0
T3	5440	5104	0	0
T4	455004	454956	0	0
T5	308760	308252	0	0
T6	1593940	1593736	0	0
T10	4280	3932	0	0
T18	10280	9940	0	0
T19	14904	11988	0	0
T20	4876	4624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	405318321	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	81798	0	0
T5	308760	49814	0	0
T6	1593940	519268	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	42536	0	0
T53	968	12	0	0
T63	0	10	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	170944421	0	0
T1	3050	256	0	0
T2	759248	7384	0	0
T3	5440	340	0	0
T4	455004	2570014	0	0
T5	308760	142970	0	0
T6	1593940	208942	0	0
T10	4280	256	0	0
T18	10280	986	0	0
T19	14904	1536	0	0
T20	4876	256	0	0
T21	0	1652	0	0
T25	0	32	0	0
T36	0	115576	0	0
T43	0	64786	0	0
T53	968	10	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	429438086	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	522040	0	0
T5	308760	53580	0	0
T6	1593940	626502	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	44174	0	0
T53	968	16	0	0
T63	0	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	405318321	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	81798	0	0
T5	308760	49814	0	0
T6	1593940	519268	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	42536	0	0
T53	968	12	0	0
T63	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	405318321	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	81798	0	0
T5	308760	49814	0	0
T6	1593940	519268	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	42536	0	0
T53	968	12	0	0
T63	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	429438086	0	0
T1	3050	64	0	0
T2	759248	97722	0	0
T3	5440	118	0	0
T4	455004	522040	0	0
T5	308760	53580	0	0
T6	1593940	626502	0	0
T10	4280	652	0	0
T18	10280	356	0	0
T19	14904	432	0	0
T20	4876	64	0	0
T25	0	140	0	0
T26	0	186876	0	0
T36	0	44174	0	0
T53	968	16	0	0
T63	0	10	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568610248	1565380064	0	0
T1	6100	5728	0	0
T2	759248	758852	0	0
T3	5440	5104	0	0
T4	455004	454956	0	0
T5	308760	308252	0	0
T6	1593940	1593736	0	0
T10	4280	3932	0	0
T18	10280	9940	0	0
T19	14904	11988	0	0
T20	4876	4624	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392152562	391345016	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392152562	107372971	0	0
GntImpliesValid_A	392152562	107372971	0	0
GrantKnown_A	392152562	391345016	0	0
IdxKnown_A	392152562	391345016	0	0
IndexIsCorrect_A	392152562	107372971	0	0
NoReadyValidNoGrant_A	392152562	44113649	0	0
Priority_A	392152562	113287206	0	0
ReadyAndValidImplyGrant_A	392152562	107372971	0	0
ReqAndReadyImplyGrant_A	392152562	107372971	0	0
ReqImpliesValid_A	392152562	113287206	0	0
ValidKnown_A	392152562	391345016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372971	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372971	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372971	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	44113649	0	0
T1	1525	128	0	0
T2	189812	2030	0	0
T3	1360	128	0	0
T4	113751	602714	0	0
T5	77190	46084	0	0
T6	398485	61041	0	0
T10	1070	128	0	0
T18	2570	493	0	0
T19	3726	768	0	0
T20	1219	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	113287206	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	127815	0	0
T5	77190	17326	0	0
T6	398485	173001	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372971	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372971	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	113287206	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	127815	0	0
T5	77190	17326	0	0
T6	398485	173001	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392152562	391345016	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392152562	107372895	0	0
GntImpliesValid_A	392152562	107372895	0	0
GrantKnown_A	392152562	391345016	0	0
IdxKnown_A	392152562	391345016	0	0
IndexIsCorrect_A	392152562	107372895	0	0
NoReadyValidNoGrant_A	392152562	44113601	0	0
Priority_A	392152562	113287178	0	0
ReadyAndValidImplyGrant_A	392152562	107372895	0	0
ReqAndReadyImplyGrant_A	392152562	107372895	0	0
ReqImpliesValid_A	392152562	113287178	0	0
ValidKnown_A	392152562	391345016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372895	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372895	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372895	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	44113601	0	0
T1	1525	128	0	0
T2	189812	2030	0	0
T3	1360	128	0	0
T4	113751	602714	0	0
T5	77190	46084	0	0
T6	398485	61041	0	0
T10	1070	128	0	0
T18	2570	493	0	0
T19	3726	768	0	0
T20	1219	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	113287178	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	127815	0	0
T5	77190	17326	0	0
T6	398485	173001	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372895	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	107372895	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	18852	0	0
T5	77190	16695	0	0
T6	398485	140415	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	113287178	0	0
T1	1525	32	0	0
T2	189812	25568	0	0
T3	1360	32	0	0
T4	113751	127815	0	0
T5	77190	17326	0	0
T6	398485	173001	0	0
T10	1070	326	0	0
T18	2570	178	0	0
T19	3726	216	0	0
T20	1219	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392152562	391345016	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392152562	95286187	0	0
GntImpliesValid_A	392152562	95286187	0	0
GrantKnown_A	392152562	391345016	0	0
IdxKnown_A	392152562	391345016	0	0
IndexIsCorrect_A	392152562	95286187	0	0
NoReadyValidNoGrant_A	392152562	41358609	0	0
Priority_A	392152562	101431787	0	0
ReadyAndValidImplyGrant_A	392152562	95286187	0	0
ReqAndReadyImplyGrant_A	392152562	95286187	0	0
ReqImpliesValid_A	392152562	101431787	0	0
ValidKnown_A	392152562	391345016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286187	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286187	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286187	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	41358609	0	0
T2	189812	1662	0	0
T3	1360	42	0	0
T4	113751	682293	0	0
T5	77190	25401	0	0
T6	398485	43430	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T21	0	826	0	0
T25	0	16	0	0
T36	0	57788	0	0
T43	0	32393	0	0
T53	484	5	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	101431787	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	133205	0	0
T5	77190	9464	0	0
T6	398485	140250	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	22087	0	0
T53	484	8	0	0
T63	0	5	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286187	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286187	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	101431787	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	133205	0	0
T5	77190	9464	0	0
T6	398485	140250	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	22087	0	0
T53	484	8	0	0
T63	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392152562	391345016	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392152562	95286268	0	0
GntImpliesValid_A	392152562	95286268	0	0
GrantKnown_A	392152562	391345016	0	0
IdxKnown_A	392152562	391345016	0	0
IndexIsCorrect_A	392152562	95286268	0	0
NoReadyValidNoGrant_A	392152562	41358562	0	0
Priority_A	392152562	101431915	0	0
ReadyAndValidImplyGrant_A	392152562	95286268	0	0
ReqAndReadyImplyGrant_A	392152562	95286268	0	0
ReqImpliesValid_A	392152562	101431915	0	0
ValidKnown_A	392152562	391345016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286268	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286268	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286268	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	41358562	0	0
T2	189812	1662	0	0
T3	1360	42	0	0
T4	113751	682293	0	0
T5	77190	25401	0	0
T6	398485	43430	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T21	0	826	0	0
T25	0	16	0	0
T36	0	57788	0	0
T43	0	32393	0	0
T53	484	5	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	101431915	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	133205	0	0
T5	77190	9464	0	0
T6	398485	140250	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	22087	0	0
T53	484	8	0	0
T63	0	5	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286268	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	95286268	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	22047	0	0
T5	77190	8212	0	0
T6	398485	119219	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	21268	0	0
T53	484	6	0	0
T63	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	101431915	0	0
T2	189812	23293	0	0
T3	1360	27	0	0
T4	113751	133205	0	0
T5	77190	9464	0	0
T6	398485	140250	0	0
T10	1070	0	0	0
T18	2570	0	0	0
T19	3726	0	0	0
T20	1219	0	0	0
T25	0	70	0	0
T26	0	93438	0	0
T36	0	22087	0	0
T53	484	8	0	0
T63	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392152562	391345016	0	0
T1	1525	1432	0	0
T2	189812	189713	0	0
T3	1360	1276	0	0
T4	113751	113739	0	0
T5	77190	77063	0	0
T6	398485	398434	0	0
T10	1070	983	0	0
T18	2570	2485	0	0
T19	3726	2997	0	0
T20	1219	1156	0	0