Module Definition
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Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.84 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.84 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_region_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_sw_sel

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_region_sel

Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_hw_sel

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Module : flash_mp_data_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T25,T63
11CoveredT2,T36,T21

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T27,T63
11CoveredT2,T30,T72

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T72,T25
11CoveredT2,T20,T31

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T25,T45
11CoveredT2,T21,T40

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T25,T135
11CoveredT2,T20,T31

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T25,T57
11CoveredT61,T48,T20

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T45,T42
11CoveredT2,T12,T30

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T12,T30
11CoveredT2,T3,T4

Branch Coverage for Module : flash_mp_data_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T25,T63
11CoveredT36,T21,T40

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T27,T63
11CoveredT30,T40,T8

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T268,T225
11CoveredT20,T31,T40

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T25,T45
11CoveredT2,T21,T40

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T25,T135
11CoveredT2,T20,T31

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T25,T57
11CoveredT61,T20,T31

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T45,T42
11CoveredT2,T12,T20

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T12,T30
11CoveredT2,T3,T17

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T17
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T11,T81,T82
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T269,T270
11CoveredT2,T36,T72

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT271,T272,T273
11CoveredT2,T72,T34

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T72,T57
11CoveredT2,T57,T192

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T45,T83
11CoveredT243,T120,T274

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT275,T276,T277
11CoveredT35,T44,T243

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT83,T268,T225
11CoveredT48,T21,T42

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT243,T83,T207
11CoveredT30,T20,T36

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T30,T48
11CoveredT2,T4,T7

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%