Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.60 100.00 90.39 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.00 97.64 93.15 100.00 99.37 94.83


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.76 96.63 85.85 100.00 91.30 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg 100.00 100.00
u_addr_xor_storage 96.53 100.00 86.11 100.00 100.00
u_bus_inv_data_intg 0.00 0.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 93.75 100.00 80.56 94.44 100.00
u_plain_enc 100.00 100.00
u_prim_buf_data_xor_out 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 97.44 100.00 87.18 100.00 100.00 100.00
u_rsp_order_fifo 97.44 100.00 87.18 100.00 100.00 100.00
u_valid_random 92.50 92.31 97.69 100.00 80.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.65 100.00 90.61 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.02 97.64 93.24 100.00 99.37 94.83


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.55 97.75 91.51 100.00 93.48 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg 100.00 100.00
u_addr_xor_storage 96.53 100.00 86.11 100.00 100.00
u_bus_inv_data_intg 0.00 0.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 93.75 100.00 80.56 94.44 100.00
u_plain_enc 100.00 100.00
u_prim_buf_data_xor_out 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 97.44 100.00 87.18 100.00 100.00 100.00
u_rsp_order_fifo 97.44 100.00 87.18 100.00 100.00 100.00
u_valid_random 92.50 92.31 97.69 100.00 80.00

Line Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23211100.00
ALWAYS25744100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
ALWAYS3601212100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
ALWAYS60066100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61411100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
ALWAYS67088100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN78711100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN80011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
137 1 1
140 4 4
141 4 4
146 4 4
152 1 1
154 3 3
186 1 1
193 4 4
194 4 4
196 4 4
212 4 4
218 4 4
222 4 4
229 1 1
232 1 1
257 1 1
258 1 1
259 1 1
260 1 1
MISSING_ELSE
291 1 1
292 1 1
302 1 1
305 1 1
308 1 1
326 1 1
331 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
MISSING_ELSE
377 1 1
382 1 1
393 1 1
399 1 1
407 1 1
428 1 1
432 1 1
442 1 1
445 1 1
451 1 1
456 1 1
459 1 1
491 1 1
494 1 1
497 1 1
501 1 1
503 1 1
504 1 1
505 1 1
513 1 1
521 1 1
523 1 1
597 1 1
598 1 1
600 1 1
601 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
614 1 1
617 1 1
624 1 1
628 1 1
636 1 1
654 1 1
659 1 1
664 4 4
670 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
MISSING_ELSE
683 1 1
704 1 1
724 1 1
736 1 1
738 1 1
744 1 1
745 1 1
747 1 1
751 1 1
762 1 1
775 1 1
787 1 1
790 1 1
794 1 1
797 1 1
800 1 1


Cond Coverage for Module : flash_phy_rd
TotalCoveredPercent
Conditions45841791.05
Logical45841791.05
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
140-79091.15
790-79483.33

Branch Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 186 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 302 2 2 100.00
TERNARY 451 2 2 100.00
TERNARY 513 3 3 100.00
TERNARY 624 3 3 100.00
TERNARY 628 3 3 100.00
TERNARY 654 3 3 100.00
TERNARY 683 2 2 100.00
TERNARY 736 2 2 100.00
TERNARY 747 2 2 100.00
TERNARY 775 2 2 100.00
TERNARY 167 2 2 100.00
IF 257 3 3 100.00
IF 360 4 4 100.00
IF 600 4 4 100.00
IF 674 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 186 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 232 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 302 ((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 451 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T2,T30,T43
0 Covered T1,T2,T3


LineNo. Expression -1-: 513 (hint_descram) ? -2-: 513 (hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T61,T29,T36
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 624 (forward) ? -2-: 624 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 628 (forward) ? -2-: 628 ((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T2,T4,T7


LineNo. Expression -1-: 654 (forward) ? -2-: 654 (((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 683 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 736 (data_err_o) ?

Branches:
-1-StatusTests
1 Covered T11,T30,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 747 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 257 if ((!rst_ni)) -2-: 259 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 360 if ((!rst_ni)) -2-: 364 if (rd_start) -3-: 371 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 600 if ((!rst_ni)) -2-: 602 if (calc_req_start) -3-: 604 if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 674 if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 778265414 1607151 0 0
ExclusiveOps_A 778265414 776636618 0 0
ExclusiveProgHazard_A 778265414 776636618 0 0
ExclusiveState_A 778265414 776636618 0 0
ForwardCheck_A 778265414 4145715 0 0
IdleCheck_A 778265414 101699700 0 0
MaxBufs_A 2122 2122 0 0
OneHotAlloc_A 778265414 776636618 0 0
OneHotMatch_A 778265414 776636618 0 0
OneHotRspMatch_A 778265414 776636618 0 0
OneHotUpdate_A 778265414 776636618 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 1607151 0 0
T2 312568 721 0 0
T3 3306 0 0 0
T4 1156134 4 0 0
T5 193854 1194 0 0
T6 0 9 0 0
T7 245876 12810 0 0
T11 7746 0 0 0
T12 2480 0 0 0
T17 3296 0 0 0
T18 13544 126 0 0
T29 0 1206 0 0
T30 0 67 0 0
T54 0 181 0 0
T60 2118 10 0 0
T61 0 2937 0 0
T62 0 1000 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 4145715 0 0
T2 312568 3149 0 0
T3 3306 0 0 0
T4 1156134 16645 0 0
T5 193854 1194 0 0
T6 0 12 0 0
T7 245876 30765 0 0
T11 7746 0 0 0
T12 2480 0 0 0
T17 3296 0 0 0
T18 13544 155 0 0
T29 0 1200 0 0
T30 0 36 0 0
T54 0 220 0 0
T60 2118 7 0 0
T61 0 44988 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 101699700 0 0
T1 1633 128 0 0
T2 312568 82641 0 0
T3 3306 256 0 0
T4 1156134 850821 0 0
T5 193854 3710 0 0
T6 0 13 0 0
T7 245876 1583738 0 0
T11 7746 647 0 0
T12 2480 128 0 0
T17 3296 256 0 0
T18 13544 614 0 0
T29 0 1554 0 0
T30 0 39 0 0
T54 0 621 0 0
T60 1059 0 0 0
T61 0 89037 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2122 2122 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T7 2 2 0 0
T11 2 2 0 0
T12 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 778265414 776636618 0 0
T1 3266 3074 0 0
T2 312568 312382 0 0
T3 3306 2984 0 0
T4 1156134 1155842 0 0
T5 193854 193740 0 0
T7 245876 245852 0 0
T11 7746 6314 0 0
T12 2480 2312 0 0
T17 3296 2994 0 0
T18 13544 13412 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23211100.00
ALWAYS25744100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
ALWAYS3601212100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
ALWAYS60066100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61411100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
ALWAYS67088100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN78711100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN80011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
137 1 1
140 4 4
141 4 4
146 4 4
152 1 1
154 3 3
186 1 1
193 4 4
194 4 4
196 4 4
212 4 4
218 4 4
222 4 4
229 1 1
232 1 1
257 1 1
258 1 1
259 1 1
260 1 1
MISSING_ELSE
291 1 1
292 1 1
302 1 1
305 1 1
308 1 1
326 1 1
331 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
MISSING_ELSE
377 1 1
382 1 1
393 1 1
399 1 1
407 1 1
428 1 1
432 1 1
442 1 1
445 1 1
451 1 1
456 1 1
459 1 1
491 1 1
494 1 1
497 1 1
501 1 1
503 1 1
504 1 1
505 1 1
513 1 1
521 1 1
523 1 1
597 1 1
598 1 1
600 1 1
601 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
614 1 1
617 1 1
624 1 1
628 1 1
636 1 1
654 1 1
659 1 1
664 4 4
670 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
MISSING_ELSE
683 1 1
704 1 1
724 1 1
736 1 1
738 1 1
744 1 1
745 1 1
747 1 1
751 1 1
762 1 1
775 1 1
787 1 1
790 1 1
794 1 1
797 1 1
800 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalCoveredPercent
Conditions45841490.39
Logical45841490.39
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
140-79090.49
790-79483.33

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 186 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 302 2 2 100.00
TERNARY 451 2 2 100.00
TERNARY 513 3 3 100.00
TERNARY 624 3 3 100.00
TERNARY 628 3 3 100.00
TERNARY 654 3 3 100.00
TERNARY 683 2 2 100.00
TERNARY 736 2 2 100.00
TERNARY 747 2 2 100.00
TERNARY 775 2 2 100.00
TERNARY 167 2 2 100.00
IF 257 3 3 100.00
IF 360 4 4 100.00
IF 600 4 4 100.00
IF 674 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 186 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 232 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 302 ((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 451 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T2,T30,T43
0 Covered T1,T2,T3


LineNo. Expression -1-: 513 (hint_descram) ? -2-: 513 (hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T30,T61
0 1 Covered T61,T36,T72
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 624 (forward) ? -2-: 624 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T2,T30,T61
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 628 (forward) ? -2-: 628 ((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T2,T4,T7


LineNo. Expression -1-: 654 (forward) ? -2-: 654 (((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T2,T30,T61
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 683 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 736 (data_err_o) ?

Branches:
-1-StatusTests
1 Covered T30,T20,T34
0 Covered T1,T2,T3


LineNo. Expression -1-: 747 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T2,T30,T61
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 257 if ((!rst_ni)) -2-: 259 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T2,T4,T7


LineNo. Expression -1-: 360 if ((!rst_ni)) -2-: 364 if (rd_start) -3-: 371 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T4,T7
0 0 1 Covered T2,T4,T7
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 600 if ((!rst_ni)) -2-: 602 if (calc_req_start) -3-: 604 if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T30,T61
0 0 1 Covered T2,T30,T61
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 674 if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 389132707 785352 0 0
ExclusiveOps_A 389132707 388318309 0 0
ExclusiveProgHazard_A 389132707 388318309 0 0
ExclusiveState_A 389132707 388318309 0 0
ForwardCheck_A 389132707 1906318 0 0
IdleCheck_A 389132707 49369115 0 0
MaxBufs_A 1061 1061 0 0
OneHotAlloc_A 389132707 388318309 0 0
OneHotMatch_A 389132707 388318309 0 0
OneHotRspMatch_A 389132707 388318309 0 0
OneHotUpdate_A 389132707 388318309 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 785352 0 0
T2 156284 300 0 0
T3 1653 0 0 0
T4 578067 4 0 0
T5 96927 652 0 0
T6 0 3 0 0
T7 122938 7061 0 0
T11 3873 0 0 0
T12 1240 0 0 0
T17 1648 0 0 0
T18 6772 84 0 0
T29 0 518 0 0
T30 0 5 0 0
T54 0 181 0 0
T60 1059 0 0 0
T61 0 1417 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 1906318 0 0
T2 156284 315 0 0
T3 1653 0 0 0
T4 578067 7761 0 0
T5 96927 652 0 0
T6 0 5 0 0
T7 122938 16228 0 0
T11 3873 0 0 0
T12 1240 0 0 0
T17 1648 0 0 0
T18 6772 104 0 0
T29 0 518 0 0
T30 0 7 0 0
T54 0 220 0 0
T60 1059 0 0 0
T61 0 22558 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 49369115 0 0
T2 156284 30466 0 0
T3 1653 0 0 0
T4 578067 395815 0 0
T5 96927 1956 0 0
T6 0 13 0 0
T7 122938 834689 0 0
T11 3873 0 0 0
T12 1240 0 0 0
T17 1648 0 0 0
T18 6772 342 0 0
T29 0 1554 0 0
T30 0 39 0 0
T54 0 621 0 0
T60 1059 0 0 0
T61 0 89037 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23211100.00
ALWAYS25744100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30511100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
ALWAYS3601212100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN49111100.00
CONT_ASSIGN49411100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN59811100.00
ALWAYS60066100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61411100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62411100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN63611100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66411100.00
ALWAYS67088100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73811100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN76211100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN78711100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN80011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
137 1 1
140 4 4
141 4 4
146 4 4
152 1 1
154 3 3
186 1 1
193 4 4
194 4 4
196 4 4
212 4 4
218 4 4
222 4 4
229 1 1
232 1 1
257 1 1
258 1 1
259 1 1
260 1 1
MISSING_ELSE
291 1 1
292 1 1
302 1 1
305 1 1
308 1 1
326 1 1
331 1 1
360 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
372 1 1
MISSING_ELSE
377 1 1
382 1 1
393 1 1
399 1 1
407 1 1
428 1 1
432 1 1
442 1 1
445 1 1
451 1 1
456 1 1
459 1 1
491 1 1
494 1 1
497 1 1
501 1 1
503 1 1
504 1 1
505 1 1
513 1 1
521 1 1
523 1 1
597 1 1
598 1 1
600 1 1
601 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
614 1 1
617 1 1
624 1 1
628 1 1
636 1 1
654 1 1
659 1 1
664 4 4
670 1 1
671 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
MISSING_ELSE
683 1 1
704 1 1
724 1 1
736 1 1
738 1 1
744 1 1
745 1 1
747 1 1
751 1 1
762 1 1
775 1 1
787 1 1
790 1 1
794 1 1
797 1 1
800 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalCoveredPercent
Conditions45841590.61
Logical45841590.61
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
140-79090.71
790-79483.33

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 186 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 302 2 2 100.00
TERNARY 451 2 2 100.00
TERNARY 513 3 3 100.00
TERNARY 624 3 3 100.00
TERNARY 628 3 3 100.00
TERNARY 654 3 3 100.00
TERNARY 683 2 2 100.00
TERNARY 736 2 2 100.00
TERNARY 747 2 2 100.00
TERNARY 775 2 2 100.00
TERNARY 167 2 2 100.00
IF 257 3 3 100.00
IF 360 4 4 100.00
IF 600 4 4 100.00
IF 674 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 186 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 232 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 302 ((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 451 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T2,T43,T35
0 Covered T1,T2,T3


LineNo. Expression -1-: 513 (hint_descram) ? -2-: 513 (hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T61,T29,T36
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 624 (forward) ? -2-: 624 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 628 (forward) ? -2-: 628 ((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T2,T4,T7


LineNo. Expression -1-: 654 (forward) ? -2-: 654 (((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T7
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 683 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T7,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 736 (data_err_o) ?

Branches:
-1-StatusTests
1 Covered T11,T20,T57
0 Covered T1,T2,T3


LineNo. Expression -1-: 747 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T7,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T7


LineNo. Expression -1-: 257 if ((!rst_ni)) -2-: 259 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 360 if ((!rst_ni)) -2-: 364 if (rd_start) -3-: 371 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 600 if ((!rst_ni)) -2-: 602 if (calc_req_start) -3-: 604 if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 674 if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T2,T7,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 389132707 821799 0 0
ExclusiveOps_A 389132707 388318309 0 0
ExclusiveProgHazard_A 389132707 388318309 0 0
ExclusiveState_A 389132707 388318309 0 0
ForwardCheck_A 389132707 2239397 0 0
IdleCheck_A 389132707 52330585 0 0
MaxBufs_A 1061 1061 0 0
OneHotAlloc_A 389132707 388318309 0 0
OneHotMatch_A 389132707 388318309 0 0
OneHotRspMatch_A 389132707 388318309 0 0
OneHotUpdate_A 389132707 388318309 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 821799 0 0
T2 156284 421 0 0
T3 1653 0 0 0
T4 578067 0 0 0
T5 96927 542 0 0
T6 0 6 0 0
T7 122938 5749 0 0
T11 3873 0 0 0
T12 1240 0 0 0
T17 1648 0 0 0
T18 6772 42 0 0
T29 0 688 0 0
T30 0 62 0 0
T60 1059 10 0 0
T61 0 1520 0 0
T62 0 1000 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 2239397 0 0
T2 156284 2834 0 0
T3 1653 0 0 0
T4 578067 8884 0 0
T5 96927 542 0 0
T6 0 7 0 0
T7 122938 14537 0 0
T11 3873 0 0 0
T12 1240 0 0 0
T17 1648 0 0 0
T18 6772 51 0 0
T29 0 682 0 0
T30 0 29 0 0
T60 1059 7 0 0
T61 0 22430 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 52330585 0 0
T1 1633 128 0 0
T2 156284 52175 0 0
T3 1653 256 0 0
T4 578067 455006 0 0
T5 96927 1754 0 0
T7 122938 749049 0 0
T11 3873 647 0 0
T12 1240 128 0 0
T17 1648 256 0 0
T18 6772 272 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389132707 388318309 0 0
T1 1633 1537 0 0
T2 156284 156191 0 0
T3 1653 1492 0 0
T4 578067 577921 0 0
T5 96927 96870 0 0
T7 122938 122926 0 0
T11 3873 3157 0 0
T12 1240 1156 0 0
T17 1648 1497 0 0
T18 6772 6706 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%