Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_phy
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.56 97.67 86.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash 94.56 97.67 86.00 100.00


Module Instance : tb.dut.u_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.56 97.67 86.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.46 98.05 93.27 99.49 97.62 99.40 96.96


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flash_cores[0].u_core 97.84 97.07 93.60 100.00 100.00 99.29 97.06
gen_flash_cores[0].u_host_rsp_fifo 97.45 100.00 87.23 100.00 100.00 100.00
gen_flash_cores[1].u_core 97.21 97.07 92.91 96.90 100.00 99.29 97.06
gen_flash_cores[1].u_host_rsp_fifo 96.60 100.00 82.98 100.00 100.00 100.00
u_bank_sequence_fifo 96.53 100.00 86.11 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_flash 97.75 98.80 94.58 100.00 93.75 99.37 100.00
u_lc_nvm_debug_en_sync 100.00 100.00 100.00 100.00
u_region_sel 100.00 100.00 100.00 100.00
u_scramble 97.22 100.00 92.15 100.00 100.00 93.94

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_phy
Line No.TotalCoveredPercent
TOTAL434297.67
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13300
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN33300
CONT_ASSIGN34911100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN392100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
121 1 1
122 1 1
125 1 1
128 1 1
129 1 1
130 1 1
133 unreachable
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
147 1 1
178 9 9
193 1 1
199 1 1
201 1 1
211 1 1
212 1 1
230 2 2
254 2 2
255 2 2
333 unreachable
349 1 1
389 1 1
392 0 1

Cond Coverage for Module : flash_phy
TotalCoveredPercent
Conditions504386.00
Logical504386.00
Non-Logical00
Event00

 LINE       121
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7 

 LINE       125
 EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
             -------------1-------------   --------------2--------------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T5,T7 

 LINE       128
 EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
             --------1-------   -------------2------------
-1--2-StatusTests
01CoveredT16,T17,T67
10CoveredT4,T5,T7
11CoveredT4,T5,T7 

 LINE       145
 EXPRESSION (((|arb_err)) | scramble_arb_err)
             ------1-----   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT85,T86,T87
10CoveredT88 

 LINE       155
 EXPRESSION (host_req_i & host_req_rdy_o)
             -----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11CoveredT4,T5,T7 

 LINE       230
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
             -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT4,T5,T7 

 LINE       230
 SUB-EXPRESSION (rsp_bank_sel == 0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       230
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
             -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT4,T5,T7
11CoveredT4,T5,T7 

 LINE       230
 SUB-EXPRESSION (rsp_bank_sel == 1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7 

 LINE       254
 EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
             -----1----   ----------2---------   --------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T7
110CoveredT7,T10,T51
111CoveredT4,T5,T7 

 LINE       254
 SUB-EXPRESSION (host_bank_sel == 0)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       254
 EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
             -----1----   ----------2---------   --------3--------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T7
110CoveredT7,T10,T51
111CoveredT4,T5,T7 

 LINE       254
 SUB-EXPRESSION (host_bank_sel == 1)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7 

 LINE       255
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
             --------1-------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11CoveredT1,T2,T3 

 LINE       255
 SUB-EXPRESSION (ctrl_bank_sel == 0)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       255
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
             --------1-------   ----------2---------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT4,T6,T7 

 LINE       255
 SUB-EXPRESSION (ctrl_bank_sel == 1)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7 

 LINE       389
 EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Module : flash_phy
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 121 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	121	(host_req_i) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%