SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.96 | 100.00 | 93.75 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.56 | 97.67 | 86.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10380 | 10380 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21522 |
gen_no_flops.OutputDelay_A | 739448100 | 737794260 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10380 | 10380 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T7 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
T20 | 10 | 10 | 0 | 0 |
T21 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 34930 | 27700 | 0 | 0 |
T2 | 28590 | 22380 | 0 | 0 |
T3 | 11670 | 9230 | 0 | 0 |
T4 | 51350 | 50280 | 0 | 0 |
T5 | 5701160 | 5699450 | 0 | 0 |
T6 | 2381040 | 2380080 | 0 | 0 |
T7 | 3381820 | 3381260 | 0 | 0 |
T19 | 25700 | 24790 | 0 | 0 |
T20 | 36130 | 29090 | 0 | 0 |
T21 | 52230 | 51520 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21522 |
T1 | 27944 | 21944 | 0 | 24 |
T2 | 22872 | 17688 | 0 | 24 |
T3 | 9336 | 7312 | 0 | 24 |
T4 | 41080 | 40176 | 0 | 24 |
T5 | 4560928 | 4559512 | 0 | 24 |
T6 | 1904832 | 1904040 | 0 | 24 |
T7 | 2705456 | 2704984 | 0 | 24 |
T19 | 20560 | 19808 | 0 | 24 |
T20 | 28904 | 23056 | 0 | 24 |
T21 | 41784 | 41192 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 739448100 | 737794260 | 0 | 0 |
T1 | 6986 | 5540 | 0 | 0 |
T2 | 5718 | 4476 | 0 | 0 |
T3 | 2334 | 1846 | 0 | 0 |
T4 | 10270 | 10056 | 0 | 0 |
T5 | 1140232 | 1139890 | 0 | 0 |
T6 | 476208 | 476016 | 0 | 0 |
T7 | 676364 | 676252 | 0 | 0 |
T19 | 5140 | 4958 | 0 | 0 |
T20 | 7226 | 5818 | 0 | 0 |
T21 | 10446 | 10304 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724079 | 368897159 | 0 | 0 |
gen_flops.OutputDelay_A | 369724079 | 368864624 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368897159 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368864624 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724079 | 368897159 | 0 | 0 |
gen_flops.OutputDelay_A | 369724079 | 368864624 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368897159 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368864624 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724079 | 368897159 | 0 | 0 |
gen_flops.OutputDelay_A | 369724079 | 368864624 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368897159 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368864624 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724079 | 368897159 | 0 | 0 |
gen_flops.OutputDelay_A | 369724079 | 368864624 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368897159 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368864624 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724079 | 368897159 | 0 | 0 |
gen_flops.OutputDelay_A | 369724079 | 368864624 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368897159 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368864624 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724079 | 368897159 | 0 | 0 |
gen_flops.OutputDelay_A | 369724079 | 368864624 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368897159 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724079 | 368864624 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724050 | 368897130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 369724050 | 368897130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724050 | 368897130 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724050 | 368897130 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369702367 | 368875447 | 0 | 0 |
gen_flops.OutputDelay_A | 369702367 | 368843062 | 0 | 2559 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369702367 | 368875447 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369702367 | 368843062 | 0 | 2559 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724050 | 368897130 | 0 | 0 |
gen_no_flops.OutputDelay_A | 369724050 | 368897130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724050 | 368897130 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724050 | 368897130 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1038 | 1038 | 0 | 0 |
OutputsKnown_A | 369724050 | 368897130 | 0 | 0 |
gen_flops.OutputDelay_A | 369724050 | 368864610 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1038 | 1038 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724050 | 368897130 | 0 | 0 |
T1 | 3493 | 2770 | 0 | 0 |
T2 | 2859 | 2238 | 0 | 0 |
T3 | 1167 | 923 | 0 | 0 |
T4 | 5135 | 5028 | 0 | 0 |
T5 | 570116 | 569945 | 0 | 0 |
T6 | 238104 | 238008 | 0 | 0 |
T7 | 338182 | 338126 | 0 | 0 |
T19 | 2570 | 2479 | 0 | 0 |
T20 | 3613 | 2909 | 0 | 0 |
T21 | 5223 | 5152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 369724050 | 368864610 | 0 | 2709 |
T1 | 3493 | 2743 | 0 | 3 |
T2 | 2859 | 2211 | 0 | 3 |
T3 | 1167 | 914 | 0 | 3 |
T4 | 5135 | 5022 | 0 | 3 |
T5 | 570116 | 569939 | 0 | 3 |
T6 | 238104 | 238005 | 0 | 3 |
T7 | 338182 | 338123 | 0 | 3 |
T19 | 2570 | 2476 | 0 | 3 |
T20 | 3613 | 2882 | 0 | 3 |
T21 | 5223 | 5149 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |