Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	95.28		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.36	100.00	83.96		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	99.06	100.00	95.28		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	83.96		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.15	97.07	92.57	96.90	100.00	99.29	97.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.00	97.64	93.15	100.00		99.37	94.83
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	95.28		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.88	97.07	93.53	100.00	100.00	99.65	97.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.49	100.00	96.92	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	96.98	97.64	93.07	100.00		99.37	94.83
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	101	95.28
Logical	106	101	95.28
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T10,T134,T231

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T134,T231

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T7

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T5,T7
1	1	0	Covered	T67,T68,T76
1	1	1	Covered	T1,T5,T7

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T93
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T7

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T10,T35

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T19
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T19,T13,T14
1	1	Covered	T3,T4,T20

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T67,T68,T76
1	0	Covered	T245

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T245

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T67,T68,T76

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T20

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T13,T14

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T42,T30
1	0	Covered	T19,T13,T14

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T231

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T231
1	1	Covered	T231

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T19
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T231

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T43
1	0	Covered	T17,T18,T43

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T13

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T13

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T13

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T13

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T19,T13,T14
StCtrlProg	339	Covered	T3,T4,T20
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T5,T13,T14
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T19,T13,T14
StCtrlProg->StIdle	359	Covered	T3,T4,T20
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T19,T13,T14
StIdle->StCtrlProg	339	Covered	T3,T4,T20
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T5,T13,T14

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	2	100.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T231
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T10,T35
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T134,T231
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T231,T15
0	0	0	Covered	T1,T5,T7

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T5,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T3,T4,T20
StIdle	0	0	0	1	-	-	-	Covered	T19,T13,T14
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T4,T20
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T4,T20
StCtrl	-	-	-	-	-	-	1	Covered	T19,T13,T14
StCtrl	-	-	-	-	-	-	0	Covered	T19,T13,T14
StDisable	-	-	-	-	-	-	-	Covered	T5,T13,T14
default	-	-	-	-	-	-	-	Covered	T10,T17,T18

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	802241832	2761800	0	0
CtrlPrio_A	802241832	2761800	0	0
HostTransIdleChk_A	802241832	44047697	0	0
NoRemainder_A	2098	2098	0	0
OneHotReqs_A	802241832	800580754	0	0
Pow2Multiple_A	2098	2098	0	0
RdTxnCheck_A	802031718	800370640	0	0
u_state_regs_A	802241832	800580754	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	2761800	0	0
T6	2680	0	0	0
T7	244312	77559	0	0
T10	0	15	0	0
T13	770194	0	0	0
T14	770132	0	0	0
T19	12584	0	0	0
T20	6654	0	0	0
T21	6728	0	0	0
T32	0	5778	0	0
T35	0	5782	0	0
T36	0	83430	0	0
T44	278604	0	0	0
T52	7846	0	0	0
T61	0	2256	0	0
T63	2010	0	0	0
T74	0	15188	0	0
T77	0	5740	0	0
T170	0	2965	0	0
T222	0	2948	0	0
T223	0	2011	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	2761800	0	0
T6	2680	0	0	0
T7	244312	77559	0	0
T10	0	15	0	0
T13	770194	0	0	0
T14	770132	0	0	0
T19	12584	0	0	0
T20	6654	0	0	0
T21	6728	0	0	0
T32	0	5778	0	0
T35	0	5782	0	0
T36	0	83430	0	0
T44	278604	0	0	0
T52	7846	0	0	0
T61	0	2256	0	0
T63	2010	0	0	0
T74	0	15188	0	0
T77	0	5740	0	0
T170	0	2965	0	0
T222	0	2948	0	0
T223	0	2011	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	44047697	0	0
T1	12580	878	0	0
T2	2606	0	0	0
T3	3284	0	0	0
T4	3784	0	0	0
T5	1708	10	0	0
T6	2680	15	0	0
T7	244312	863073	0	0
T8	0	45	0	0
T13	770194	0	0	0
T19	12584	79	0	0
T20	6654	34	0	0
T23	0	20	0	0
T24	0	12	0	0
T25	0	38	0	0
T63	0	5	0	0
T70	0	28	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098	2098	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T13	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	800580754	0	0
T1	12580	11610	0	0
T2	2606	2090	0	0
T3	3284	3112	0	0
T4	3784	3642	0	0
T5	1708	1546	0	0
T6	2680	2520	0	0
T7	244312	244284	0	0
T13	770194	770164	0	0
T19	12584	12306	0	0
T20	6654	6354	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098	2098	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T13	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802031718	800370640	0	0
T1	12580	11610	0	0
T2	2606	2090	0	0
T3	3284	3112	0	0
T4	3784	3642	0	0
T5	1708	1546	0	0
T6	2680	2520	0	0
T7	244312	244284	0	0
T13	770194	770164	0	0
T19	12584	12306	0	0
T20	6654	6354	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	800580754	0	0
T1	12580	11610	0	0
T2	2606	2090	0	0
T3	3284	3112	0	0
T4	3784	3642	0	0
T5	1708	1546	0	0
T6	2680	2520	0	0
T7	244312	244284	0	0
T13	770194	770164	0	0
T19	12584	12306	0	0
T20	6654	6354	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T19
1	0	Covered	T1,T5,T7
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T3,T7,T19
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T7

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T7

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T19,T20
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T7

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T7,T19
1	1	Covered	T1,T5,T7

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T3,T7,T19
1	1	Covered	T7,T35,T74

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T20
1	1	Covered	T7,T19,T20

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T13
1	0	Covered	T19,T13,T14
1	1	Covered	T3,T20,T13

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T19
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T20
1	1	Covered	T7,T19,T20

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T7,T19,T20
1	1	Covered	T3,T20,T13

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T13,T14
1	0	Covered	T3,T7,T19
1	1	Covered	T19,T13,T14

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T42,T30
1	0	Covered	T19,T13,T14

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T20
1	1	Covered	T1,T5,T7

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T43
1	0	Covered	T17,T18,T43

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T19
1	0	Covered	T3,T13,T14

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T19
1	0	Covered	T3,T13,T14

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T14

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T14

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T19,T13,T14
StCtrlProg	339	Covered	T3,T20,T21
StCtrlRead	337	Covered	T7,T19,T20
StDisable	335	Covered	T5,T13,T14
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T19,T13,T14
StCtrlProg->StIdle	359	Covered	T3,T20,T21
StCtrlRead->StIdle	349	Covered	T7,T19,T20
StIdle->StCtrl	341	Covered	T19,T13,T14
StIdle->StCtrlProg	339	Covered	T3,T20,T21
StIdle->StCtrlRead	337	Covered	T7,T19,T20
StIdle->StDisable	335	Covered	T5,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T19
0	0	1	Covered	T7,T10,T35
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T15,T16
0	0	0	Covered	T1,T5,T7

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T15,T16
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T5,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T7,T19,T20
StIdle	0	0	1	-	-	-	-	Covered	T3,T20,T13
StIdle	0	0	0	1	-	-	-	Covered	T19,T13,T14
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T7,T19,T20
StCtrlRead	-	-	-	-	0	-	-	Covered	T7,T19,T20
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T20,T13
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T20,T13
StCtrl	-	-	-	-	-	-	1	Covered	T19,T13,T14
StCtrl	-	-	-	-	-	-	0	Covered	T19,T13,T14
StDisable	-	-	-	-	-	-	-	Covered	T5,T13,T14
default	-	-	-	-	-	-	-	Covered	T10,T17,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	401120916	1214146	0	0
CtrlPrio_A	401120916	1214146	0	0
HostTransIdleChk_A	401120916	21802203	0	0
NoRemainder_A	1049	1049	0	0
OneHotReqs_A	401120916	400290377	0	0
Pow2Multiple_A	1049	1049	0	0
RdTxnCheck_A	401015859	400185320	0	0
u_state_regs_A	401120916	400290377	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	1214146	0	0
T6	1340	0	0	0
T7	122156	63963	0	0
T13	385097	0	0	0
T14	385066	0	0	0
T19	6292	0	0	0
T20	3327	0	0	0
T21	3364	0	0	0
T32	0	1723	0	0
T35	0	3483	0	0
T36	0	36668	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T61	0	2256	0	0
T63	1005	0	0	0
T74	0	7187	0	0
T77	0	2420	0	0
T170	0	1198	0	0
T222	0	2010	0	0
T223	0	1372	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	1214146	0	0
T6	1340	0	0	0
T7	122156	63963	0	0
T13	385097	0	0	0
T14	385066	0	0	0
T19	6292	0	0	0
T20	3327	0	0	0
T21	3364	0	0	0
T32	0	1723	0	0
T35	0	3483	0	0
T36	0	36668	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T61	0	2256	0	0
T63	1005	0	0	0
T74	0	7187	0	0
T77	0	2420	0	0
T170	0	1198	0	0
T222	0	2010	0	0
T223	0	1372	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	21802203	0	0
T1	6290	350	0	0
T2	1303	0	0	0
T3	1642	0	0	0
T4	1892	0	0	0
T5	854	10	0	0
T6	1340	0	0	0
T7	122156	433296	0	0
T13	385097	0	0	0
T19	6292	34	0	0
T20	3327	10	0	0
T23	0	8	0	0
T24	0	2	0	0
T25	0	22	0	0
T63	0	5	0	0
T70	0	12	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401015859	400185320	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
165	3	3
196	1	1
200	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
277	1	1
280	1	1
281	1	1
282	1	1
287	1	1
317	1	1
321	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
			MISSING_ELSE
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
356	1	1
357	1	1
358	1	1
359	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
374	1	1
375	1	1
388	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
415	1	1
428	1	1
523	1	1
550	1	1
551	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
568	1	1
585	1	1
586	1	1
587	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	101	95.28
Logical	106	101	95.28
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6
1	1	Covered	T10,T134,T231

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T134,T231

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T7,T6
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T7,T6
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T7,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T6

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T6
1	0	1	Covered	T1,T7,T6
1	1	0	Covered	T67,T68,T76
1	1	1	Covered	T1,T7,T6

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T19
1	1	Covered	T1,T7,T6

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6
1	1	Covered	T1,T7,T6

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T6

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T93
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T6

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T10,T35

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T7,T19,T20
1	0	Covered	T4,T19,T20
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T13
1	0	Covered	T19,T13,T14
1	1	Covered	T4,T20,T13

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T67,T68,T76
1	0	Covered	T245

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T245

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T67,T68,T76

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T6

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T6

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T6

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T6

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T19
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T13

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T13,T14

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T42,T30
1	0	Covered	T19,T13,T14

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T231

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T6
1	0	Covered	T231
1	1	Covered	T231

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T6

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T20
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T6
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T231

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T43
1	0	Covered	T17,T18,T43

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T14

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T14

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T19,T13,T14
StCtrlProg	339	Covered	T4,T20,T13
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T5,T13,T14
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T19,T13,T14
StCtrlProg->StIdle	359	Covered	T4,T20,T13
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T19,T13,T14
StIdle->StCtrlProg	339	Covered	T4,T20,T13
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T5,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	2	100.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	317	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T231
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))
-2-:	154	if (ctrl_rsp_vld)
-3-:	156	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T10,T35
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))
-2-:	205	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T134,T231
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if ((host_outstanding == '0))
-3-:	219	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T231,T15
0	0	0	Covered	T1,T7,T6

	LineNo.	Expression
-1-:	229	if ((!rst_ni))
-2-:	231	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	233	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	case (state_q)
-2-:	334	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	336	if ((ctrl_gnt && rd_i))
-4-:	338	if ((ctrl_gnt && prog_i))
-5-:	340	if (ctrl_gnt)
-6-:	347	if (rd_stage_data_valid)
-7-:	357	if (prog_ack)
-8-:	367	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T5,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T4,T20,T13
StIdle	0	0	0	1	-	-	-	Covered	T19,T13,T14
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T4,T20,T13
StCtrlProg	-	-	-	-	-	0	-	Covered	T4,T20,T13
StCtrl	-	-	-	-	-	-	1	Covered	T19,T13,T14
StCtrl	-	-	-	-	-	-	0	Covered	T19,T13,T14
StDisable	-	-	-	-	-	-	-	Covered	T5,T13,T14
default	-	-	-	-	-	-	-	Covered	T10,T17,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	401120916	1547654	0	0
CtrlPrio_A	401120916	1547654	0	0
HostTransIdleChk_A	401120916	22245494	0	0
NoRemainder_A	1049	1049	0	0
OneHotReqs_A	401120916	400290377	0	0
Pow2Multiple_A	1049	1049	0	0
RdTxnCheck_A	401015859	400185320	0	0
u_state_regs_A	401120916	400290377	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	1547654	0	0
T6	1340	0	0	0
T7	122156	13596	0	0
T10	0	15	0	0
T13	385097	0	0	0
T14	385066	0	0	0
T19	6292	0	0	0
T20	3327	0	0	0
T21	3364	0	0	0
T32	0	4055	0	0
T35	0	2299	0	0
T36	0	46762	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T63	1005	0	0	0
T74	0	8001	0	0
T77	0	3320	0	0
T170	0	1767	0	0
T222	0	938	0	0
T223	0	639	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	1547654	0	0
T6	1340	0	0	0
T7	122156	13596	0	0
T10	0	15	0	0
T13	385097	0	0	0
T14	385066	0	0	0
T19	6292	0	0	0
T20	3327	0	0	0
T21	3364	0	0	0
T32	0	4055	0	0
T35	0	2299	0	0
T36	0	46762	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T63	1005	0	0	0
T74	0	8001	0	0
T77	0	3320	0	0
T170	0	1767	0	0
T222	0	938	0	0
T223	0	639	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	22245494	0	0
T1	6290	528	0	0
T2	1303	0	0	0
T3	1642	0	0	0
T4	1892	0	0	0
T5	854	0	0	0
T6	1340	15	0	0
T7	122156	429777	0	0
T8	0	45	0	0
T13	385097	0	0	0
T19	6292	45	0	0
T20	3327	24	0	0
T23	0	12	0	0
T24	0	10	0	0
T25	0	16	0	0
T70	0	16	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401015859	400185320	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0