Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T20

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T20

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T186
1	0	Covered	T11,T12,T186

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T20
1	1	Covered	T11,T12,T186

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T186
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T20

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T21,T41,T42

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T3,T4,T20
1	1	Covered	T3,T4,T20

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T20

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T20
1	1	Covered	T21,T42,T30

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T21,T42,T30

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T3,T4,T20
1	1	Covered	T3,T4,T20

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T3,T4,T20

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T3,T4,T20
1	1	Covered	T21,T41,T42

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T21,T41,T42

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T20,T21,T41
1	Covered	T3,T4,T13

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T4,T21
1	Covered	T3,T4,T20

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T4,T21
1	Covered	T3,T4,T13

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T21
1	1	Covered	T3,T4,T20

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T13
1	1	Covered	T3,T4,T13

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T13
1	1	Covered	T3,T4,T13

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T20
1	1	0	Covered	T3,T4,T20
1	1	1	Covered	T3,T4,T20

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T20

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T3,T4,T13
StCalcMask	237	Covered	T3,T4,T13
StCalcPlainEcc	215	Covered	T3,T4,T20
StDisabled	193	Covered	T5,T13,T14
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T3,T4,T20
StPostPack	218	Covered	T21,T41,T42
StPrePack	195	Covered	T21,T42,T30
StReqFlash	237	Covered	T3,T4,T20
StScrambleData	244	Covered	T3,T4,T13
StWaitFlash	270	Covered	T3,T4,T20

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T3,T4,T13
StCalcMask->StScrambleData	244	Covered	T3,T4,T13
StCalcPlainEcc->StCalcMask	237	Covered	T3,T4,T13
StCalcPlainEcc->StReqFlash	237	Covered	T20,T21,T41
StIdle->StDisabled	193	Covered	T5,T13,T14
StIdle->StPackData	197	Covered	T3,T4,T20
StIdle->StPrePack	195	Covered	T21,T42,T30
StPackData->StCalcPlainEcc	215	Covered	T3,T4,T20
StPackData->StPostPack	218	Covered	T21,T41,T42
StPostPack->StCalcPlainEcc	231	Covered	T21,T41,T42
StPrePack->StPackData	205	Covered	T21,T42,T30
StReqFlash->StIdle	273	Covered	T3,T4,T13
StReqFlash->StWaitFlash	270	Covered	T3,T4,T20
StScrambleData->StCalcEcc	252	Covered	T3,T4,T13
StWaitFlash->StIdle	280	Covered	T3,T4,T20

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T20
0	0	1	Covered	T3,T4,T20
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T42,T30
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T42,T30
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T41,T42
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T41,T42
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T15,T16
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T4,T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T20,T21,T41
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T4,T13
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T4,T13
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T4,T13
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T4,T13
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T13
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T4,T20
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T3,T4,T21
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T3,T4,T13
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T3,T4,T21
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T20
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T20
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T3,T4,T20
0	0	1	-	-	Covered	T3,T4,T13
0	0	0	1	-	Covered	T3,T4,T13
0	0	0	0	1	Covered	T3,T4,T20
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	802241832	2432627	0	0
PostPackRule_A	802241832	1921	0	0
PrePackRule_A	802241832	1340	0	0
WidthCheck_A	2098	2098	0	0
u_state_regs_A	802241832	800580754	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	2432627	0	0
T3	1642	1	0	0
T4	3784	1	0	0
T5	1708	0	0	0
T6	2680	0	0	0
T7	244312	0	0	0
T13	770194	65920	0	0
T14	770132	65920	0	0
T19	12584	0	0	0
T20	6654	4	0	0
T21	6728	4	0	0
T23	0	1	0	0
T24	0	1	0	0
T29	0	32	0	0
T30	0	173	0	0
T41	0	1	0	0
T42	0	39	0	0
T52	3923	0	0	0
T64	0	180	0	0
T65	0	337	0	0
T97	0	51	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	1921	0	0
T8	0	2	0	0
T14	770132	0	0	0
T21	6728	4	0	0
T30	0	16	0	0
T41	4256	1	0	0
T42	0	24	0	0
T44	278604	0	0	0
T52	7846	0	0	0
T54	2554	0	0	0
T63	2010	0	0	0
T64	304722	0	0	0
T84	0	35	0	0
T85	0	46	0	0
T86	8184	0	0	0
T100	0	67	0	0
T116	2936	0	0	0
T153	0	13	0	0
T221	0	3	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	3	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	1340	0	0
T8	0	2	0	0
T14	385066	0	0	0
T21	3364	2	0	0
T23	1726	0	0	0
T24	2748	0	0	0
T30	901639	14	0	0
T31	200027	0	0	0
T41	2128	0	0	0
T42	81021	22	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T53	3452	0	0	0
T54	1277	0	0	0
T63	1005	0	0	0
T64	152361	0	0	0
T66	0	1	0	0
T84	0	24	0	0
T85	0	28	0	0
T86	4092	0	0	0
T90	3519	0	0	0
T97	97064	0	0	0
T100	0	57	0	0
T101	0	36	0	0
T115	95405	0	0	0
T116	1468	0	0	0
T153	0	7	0	0
T162	1064	0	0	0
T221	0	7	0	0
T247	0	1	0	0
T248	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098	2098	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T13	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802241832	800580754	0	0
T1	12580	11610	0	0
T2	2606	2090	0	0
T3	3284	3112	0	0
T4	3784	3642	0	0
T5	1708	1546	0	0
T6	2680	2520	0	0
T7	244312	244284	0	0
T13	770194	770164	0	0
T19	12584	12306	0	0
T20	6654	6354	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T13

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T13

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T186
1	0	Covered	T11,T12,T186

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T20,T13
1	1	Covered	T11,T12,T186

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T186
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T13

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T20,T13
1	Covered	T21,T42,T30

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T13
1	0	Covered	T4,T20,T13
1	1	Covered	T4,T20,T13

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T13

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T20,T13
1	1	Covered	T21,T42,T30

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T21,T42,T30

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T13
1	0	Covered	T4,T20,T13
1	1	Covered	T4,T20,T13

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T20,T13
1	Covered	T4,T20,T13

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T13
1	0	Covered	T4,T20,T13
1	1	Covered	T21,T42,T30

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T21,T42,T30

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T20,T21,T29
1	Covered	T4,T13,T14

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T21,T64
1	Covered	T4,T20,T13

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T21,T64
1	Covered	T4,T13,T21

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T21,T64
1	1	Covered	T4,T20,T13

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14
1	1	Covered	T4,T13,T14

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T14
1	1	Covered	T4,T13,T14

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T13
1	1	0	Covered	T4,T20,T13
1	1	1	Covered	T4,T20,T13

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T13

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T13,T14
StCalcMask	237	Covered	T4,T13,T14
StCalcPlainEcc	215	Covered	T4,T20,T13
StDisabled	193	Covered	T5,T13,T14
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T20,T13
StPostPack	218	Covered	T21,T42,T30
StPrePack	195	Covered	T21,T42,T30
StReqFlash	237	Covered	T4,T20,T13
StScrambleData	244	Covered	T4,T13,T14
StWaitFlash	270	Covered	T4,T20,T13

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T13,T14
StCalcMask->StScrambleData	244	Covered	T4,T13,T14
StCalcPlainEcc->StCalcMask	237	Covered	T4,T13,T14
StCalcPlainEcc->StReqFlash	237	Covered	T20,T21,T29
StIdle->StDisabled	193	Covered	T5,T13,T14
StIdle->StPackData	197	Covered	T4,T20,T13
StIdle->StPrePack	195	Covered	T21,T42,T30
StPackData->StCalcPlainEcc	215	Covered	T4,T20,T13
StPackData->StPostPack	218	Covered	T21,T42,T30
StPostPack->StCalcPlainEcc	231	Covered	T21,T42,T30
StPrePack->StPackData	205	Covered	T21,T42,T30
StReqFlash->StIdle	273	Covered	T4,T13,T21
StReqFlash->StWaitFlash	270	Covered	T4,T20,T13
StScrambleData->StCalcEcc	252	Covered	T4,T13,T14
StWaitFlash->StIdle	280	Covered	T4,T20,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T13
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T20,T13
0	0	1	Covered	T4,T20,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T42,T30
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T42,T30
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T42,T30
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T20,T13
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T42,T30
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T15,T16
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T20,T21,T29
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T13,T14
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T13,T14
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T13,T14
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T13,T14
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T20,T13
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T21,T64
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T13,T21
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T21,T64
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T20,T13
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T20,T13
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T20,T13
0	0	1	-	-	Covered	T4,T13,T14
0	0	0	1	-	Covered	T4,T13,T14
0	0	0	0	1	Covered	T4,T20,T13
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T20,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	401120916	1247139	0	0
PostPackRule_A	401120916	957	0	0
PrePackRule_A	401120916	664	0	0
WidthCheck_A	1049	1049	0	0
u_state_regs_A	401120916	400290377	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	1247139	0	0
T4	1892	1	0	0
T5	854	0	0	0
T6	1340	0	0	0
T7	122156	0	0	0
T13	385097	33152	0	0
T14	385066	33152	0	0
T19	6292	0	0	0
T20	3327	3	0	0
T21	3364	3	0	0
T23	0	1	0	0
T29	0	32	0	0
T42	0	13	0	0
T52	3923	0	0	0
T64	0	180	0	0
T65	0	337	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	957	0	0
T8	0	2	0	0
T14	385066	0	0	0
T21	3364	3	0	0
T30	0	5	0	0
T41	2128	0	0	0
T42	0	10	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T54	1277	0	0	0
T63	1005	0	0	0
T64	152361	0	0	0
T84	0	18	0	0
T85	0	24	0	0
T86	4092	0	0	0
T100	0	27	0	0
T116	1468	0	0	0
T153	0	10	0	0
T221	0	3	0	0
T248	0	3	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	664	0	0
T8	0	2	0	0
T14	385066	0	0	0
T21	3364	2	0	0
T30	0	5	0	0
T41	2128	0	0	0
T42	0	6	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T54	1277	0	0	0
T63	1005	0	0	0
T64	152361	0	0	0
T66	0	1	0	0
T84	0	13	0	0
T85	0	16	0	0
T86	4092	0	0	0
T100	0	23	0	0
T116	1468	0	0	0
T153	0	4	0	0
T221	0	3	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T13

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T13

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T109
1	0	Covered	T11,T12,T109

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T20,T13
1	1	Covered	T11,T12,T109

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T109
1	0	Covered	T1,T3,T5

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T13

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T20,T13
1	Covered	T21,T41,T42

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T13
1	0	Covered	T3,T20,T13
1	1	Covered	T3,T20,T13

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T13

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T20,T13
1	1	Covered	T42,T30,T84

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T42,T30,T84

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T13
1	0	Covered	T3,T20,T13
1	1	Covered	T3,T20,T13

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T3,T20,T13
1	Covered	T3,T20,T13

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T13
1	0	Covered	T3,T20,T13
1	1	Covered	T21,T41,T42

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T21,T41,T42

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T20,T21,T41
1	Covered	T3,T13,T14

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T21,T41
1	Covered	T3,T20,T13

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T3,T41,T42
1	Covered	T3,T13,T21

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T21,T41
1	1	Covered	T3,T20,T13

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T3,T13,T14
1	1	Covered	T3,T13,T14

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T3,T13,T14
1	1	Covered	T3,T13,T14

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T20,T13
1	1	0	Covered	T3,T20,T13
1	1	1	Covered	T3,T20,T13

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T13

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T3,T249,T74
StCalcMask	237	Covered	T3,T249,T74
StCalcPlainEcc	215	Covered	T3,T20,T21
StDisabled	193	Covered	T5,T13,T14
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T3,T20,T21
StPostPack	218	Covered	T21,T41,T42
StPrePack	195	Covered	T42,T30,T84
StReqFlash	237	Covered	T3,T20,T21
StScrambleData	244	Covered	T3,T249,T74
StWaitFlash	270	Covered	T3,T20,T13

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T3,T249,T74
StCalcMask->StScrambleData	244	Covered	T3,T249,T74
StCalcPlainEcc->StCalcMask	237	Covered	T3,T249,T74
StCalcPlainEcc->StReqFlash	237	Covered	T20,T21,T41
StIdle->StDisabled	193	Covered	T5,T13,T14
StIdle->StPackData	197	Covered	T3,T20,T21
StIdle->StPrePack	195	Covered	T42,T30,T84
StPackData->StCalcPlainEcc	215	Covered	T3,T20,T21
StPackData->StPostPack	218	Covered	T21,T41,T42
StPostPack->StCalcPlainEcc	231	Covered	T21,T41,T42
StPrePack->StPackData	205	Covered	T42,T30,T84
StReqFlash->StIdle	273	Covered	T3,T13,T21
StReqFlash->StWaitFlash	270	Covered	T3,T20,T13
StScrambleData->StCalcEcc	252	Covered	T3,T249,T74
StWaitFlash->StIdle	280	Covered	T3,T20,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T20,T13
0	1	Covered	T1,T5,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T20,T13
0	0	1	Covered	T3,T20,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T42,T30,T84
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T13
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T42,T30,T84
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T15,T16
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T13
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T41,T42
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T3,T20,T13
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T3,T20,T13
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T41,T42
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T15,T16
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T20,T21,T41
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T13,T14
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T13,T14
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T13,T14
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T13,T14
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T14
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T20,T13
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T3,T21,T41
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T3,T13,T21
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T3,T41,T42
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T20,T13
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T20,T13
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T3,T20,T13
0	0	1	-	-	Covered	T3,T13,T14
0	0	0	1	-	Covered	T3,T13,T14
0	0	0	0	1	Covered	T3,T20,T13
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T20,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	401120916	1185488	0	0
PostPackRule_A	401120916	964	0	0
PrePackRule_A	401120916	676	0	0
WidthCheck_A	1049	1049	0	0
u_state_regs_A	401120916	400290377	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	1185488	0	0
T3	1642	1	0	0
T4	1892	0	0	0
T5	854	0	0	0
T6	1340	0	0	0
T7	122156	0	0	0
T13	385097	32768	0	0
T14	385066	32768	0	0
T19	6292	0	0	0
T20	3327	1	0	0
T21	3364	1	0	0
T24	0	1	0	0
T30	0	173	0	0
T41	0	1	0	0
T42	0	26	0	0
T97	0	51	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	964	0	0
T14	385066	0	0	0
T21	3364	1	0	0
T30	0	11	0	0
T41	2128	1	0	0
T42	0	14	0	0
T44	139302	0	0	0
T52	3923	0	0	0
T54	1277	0	0	0
T63	1005	0	0	0
T64	152361	0	0	0
T84	0	17	0	0
T85	0	22	0	0
T86	4092	0	0	0
T100	0	40	0	0
T116	1468	0	0	0
T153	0	3	0	0
T246	0	1	0	0
T247	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	676	0	0
T23	1726	0	0	0
T24	2748	0	0	0
T30	901639	9	0	0
T31	200027	0	0	0
T42	81021	16	0	0
T53	3452	0	0	0
T84	0	11	0	0
T85	0	12	0	0
T90	3519	0	0	0
T97	97064	0	0	0
T100	0	34	0	0
T101	0	36	0	0
T115	95405	0	0	0
T153	0	3	0	0
T162	1064	0	0	0
T221	0	4	0	0
T247	0	1	0	0
T248	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0