Unified Coverage Report :: Module :: prim_secded_hamming_72_64_enc

Module : prim_secded_hamming_72_64_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.93	100.00	91.70			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	100.00	93.85		100.00	96.36	100.00	gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	100.00	93.85		100.00	96.36	100.00	gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_secded_hamming_72_64_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1