Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	98.04	100.00	93.85		100.00	96.36	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	98.04	100.00	93.85		100.00	96.36	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.85	100.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.59	98.88	96.23		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	93.85	95.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	96.63	84.91		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T177,T193,T195
1	0	Covered	T177,T193,T195

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T177,T193,T195

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T177,T193,T195
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T5,T11,T23

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T5,T23

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T23

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T23,T24

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T23,T24

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T11,T7

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T7
1	1	Covered	T2,T11,T7

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T7
1	1	Covered	T2,T11,T7

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T2,T11,T7
StCalcMask	237	Covered	T2,T11,T7
StCalcPlainEcc	215	Covered	T1,T2,T5
StDisabled	193	Covered	T3,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T5
StPostPack	218	Covered	T5,T23,T24
StPrePack	195	Covered	T1,T5,T23
StReqFlash	237	Covered	T1,T2,T5
StScrambleData	244	Covered	T2,T11,T7
StWaitFlash	270	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T2,T11,T7
StCalcMask->StScrambleData	244	Covered	T2,T11,T7
StCalcPlainEcc->StCalcMask	237	Covered	T2,T11,T7
StCalcPlainEcc->StReqFlash	237	Covered	T1,T2,T5
StIdle->StDisabled	193	Covered	T3,T11,T12
StIdle->StPackData	197	Covered	T1,T2,T5
StIdle->StPrePack	195	Covered	T1,T5,T23
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T5
StPackData->StPostPack	218	Covered	T5,T23,T24
StPostPack->StCalcPlainEcc	231	Covered	T5,T23,T24
StPrePack->StPackData	205	Covered	T1,T5,T23
StReqFlash->StIdle	273	Covered	T1,T2,T5
StReqFlash->StWaitFlash	270	Covered	T1,T2,T5
StScrambleData->StCalcEcc	252	Covered	T2,T11,T7
StWaitFlash->StIdle	280	Covered	T1,T2,T5

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T24
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T23,T24
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T11,T7
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T5
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T11,T7
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T11,T7
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T11,T7
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T11,T7
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T2,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T5
0	0	1	-	-	Covered	T2,T11,T7
0	0	0	1	-	Covered	T2,T11,T7
0	0	0	0	1	Covered	T1,T2,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	787959466	2436983	0	0
PostPackRule_A	787959466	2010	0	0
PrePackRule_A	787959466	1382	0	0
WidthCheck_A	2090	2090	0	0
u_state_regs_A	787959466	786155052	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787959466	2436983	0	0
T1	4582	2	0	0
T2	437420	1281	0	0
T3	2514	0	0	0
T4	240488	0	0	0
T5	6768	3	0	0
T6	89552	0	0	0
T7	343582	891	0	0
T11	770710	65920	0	0
T12	0	1	0	0
T16	6624	0	0	0
T17	78966	0	0	0
T18	0	388	0	0
T23	0	58	0	0
T24	0	175	0	0
T56	0	1130	0	0
T89	0	55	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787959466	2010	0	0
T5	3384	1	0	0
T7	171791	0	0	0
T11	385355	0	0	0
T12	1017	0	0	0
T17	39483	0	0	0
T18	101013	0	0	0
T23	1033878	36	0	0
T24	205112	11	0	0
T25	0	47	0	0
T32	0	10	0	0
T38	127746	0	0	0
T41	0	3	0	0
T42	0	2	0	0
T47	1265	0	0	0
T51	5733	0	0	0
T56	293122	0	0	0
T65	7692	0	0	0
T66	1596	0	0	0
T89	163111	0	0	0
T90	0	3	0	0
T91	0	6	0	0
T106	0	61	0	0
T112	1518	0	0	0
T213	0	2	0	0
T214	0	4	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787959466	1382	0	0
T1	2291	1	0	0
T2	218710	0	0	0
T3	1257	0	0	0
T4	120244	0	0	0
T5	6768	3	0	0
T6	44776	0	0	0
T7	343582	0	0	0
T11	770710	0	0	0
T12	1017	0	0	0
T16	3312	0	0	0
T17	78966	0	0	0
T18	101013	0	0	0
T23	516939	24	0	0
T24	102556	8	0	0
T25	0	27	0	0
T32	0	5	0	0
T38	63873	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T65	3846	0	0	0
T90	0	2	0	0
T91	0	1	0	0
T106	0	47	0	0
T213	0	2	0	0
T214	0	5	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090	2090	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T11	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787959466	786155052	0	0
T1	4582	4430	0	0
T2	437420	437226	0	0
T3	2514	2376	0	0
T4	240488	240460	0	0
T5	6768	6580	0	0
T6	89552	89422	0	0
T7	343582	343476	0	0
T11	770710	770680	0	0
T16	6624	6486	0	0
T17	78966	78710	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T177,T193,T195
1	0	Covered	T177,T193,T195

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T177,T193,T195

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T177,T193,T195
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T11,T23,T24

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T23,T24

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T23,T24

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T23,T24,T25

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T23,T24,T25

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T11,T7

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T7
1	1	Covered	T2,T11,T7

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T7
1	1	Covered	T2,T11,T7

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T2,T11,T7
StCalcMask	237	Covered	T2,T11,T7
StCalcPlainEcc	215	Covered	T1,T2,T5
StDisabled	193	Covered	T3,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T5
StPostPack	218	Covered	T23,T24,T25
StPrePack	195	Covered	T5,T23,T24
StReqFlash	237	Covered	T1,T2,T5
StScrambleData	244	Covered	T2,T11,T7
StWaitFlash	270	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T2,T11,T7
StCalcMask->StScrambleData	244	Covered	T2,T11,T7
StCalcPlainEcc->StCalcMask	237	Covered	T2,T11,T7
StCalcPlainEcc->StReqFlash	237	Covered	T1,T2,T5
StIdle->StDisabled	193	Covered	T3,T11,T12
StIdle->StPackData	197	Covered	T1,T2,T5
StIdle->StPrePack	195	Covered	T5,T23,T24
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T5
StPackData->StPostPack	218	Covered	T23,T24,T25
StPostPack->StCalcPlainEcc	231	Covered	T23,T24,T25
StPrePack->StPackData	205	Covered	T5,T23,T24
StReqFlash->StIdle	273	Covered	T1,T2,T5
StReqFlash->StWaitFlash	270	Covered	T1,T2,T5
StScrambleData->StCalcEcc	252	Covered	T2,T11,T7
StWaitFlash->StIdle	280	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T24
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T24
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T23,T24,T25
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T11,T7
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T5
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T11,T7
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T11,T7
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T11,T7
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T11,T7
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T2,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T5
0	0	1	-	-	Covered	T2,T11,T7
0	0	0	1	-	Covered	T2,T11,T7
0	0	0	0	1	Covered	T1,T2,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	393979733	1250439	0	0
PostPackRule_A	393979733	967	0	0
PrePackRule_A	393979733	667	0	0
WidthCheck_A	1045	1045	0	0
u_state_regs_A	393979733	393077526	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	1250439	0	0
T1	2291	1	0	0
T2	218710	710	0	0
T3	1257	0	0	0
T4	120244	0	0	0
T5	3384	1	0	0
T6	44776	0	0	0
T7	171791	403	0	0
T11	385355	33152	0	0
T16	3312	0	0	0
T17	39483	0	0	0
T18	0	218	0	0
T23	0	29	0	0
T24	0	70	0	0
T56	0	531	0	0
T89	0	55	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	967	0	0
T23	516939	17	0	0
T24	102556	4	0	0
T25	0	15	0	0
T32	0	5	0	0
T38	63873	0	0	0
T41	0	2	0	0
T47	1265	0	0	0
T51	5733	0	0	0
T56	293122	0	0	0
T65	3846	0	0	0
T66	1596	0	0	0
T89	163111	0	0	0
T90	0	1	0	0
T91	0	1	0	0
T106	0	23	0	0
T112	1518	0	0	0
T213	0	2	0	0
T214	0	4	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	667	0	0
T5	3384	1	0	0
T7	171791	0	0	0
T11	385355	0	0	0
T12	1017	0	0	0
T17	39483	0	0	0
T18	101013	0	0	0
T23	516939	11	0	0
T24	102556	4	0	0
T25	0	15	0	0
T32	0	2	0	0
T38	63873	0	0	0
T41	0	1	0	0
T65	3846	0	0	0
T91	0	1	0	0
T106	0	18	0	0
T213	0	2	0	0
T214	0	5	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			==> MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T19
1	0	Covered	T8,T9,T19

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T8,T9,T19

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T19
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T5,T23,T24

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T5,T23

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T23

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T23,T24

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T23,T24

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T11,T18,T66

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T18,T38
1	0	Covered	T11,T18,T66
1	1	Covered	T11,T18,T66

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T18,T38
1	0	Covered	T11,T18,T66
1	1	Covered	T11,T18,T66

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T18,T66,T56
StCalcMask	237	Covered	T18,T66,T56
StCalcPlainEcc	215	Covered	T1,T2,T5
StDisabled	193	Covered	T3,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T5
StPostPack	218	Covered	T5,T23,T24
StPrePack	195	Covered	T1,T5,T23
StReqFlash	237	Covered	T1,T2,T5
StScrambleData	244	Covered	T18,T66,T56
StWaitFlash	270	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T18,T56,T52
StCalcMask->StScrambleData	244	Covered	T18,T66,T56
StCalcPlainEcc->StCalcMask	237	Covered	T18,T66,T56
StCalcPlainEcc->StReqFlash	237	Covered	T1,T2,T5
StIdle->StDisabled	193	Covered	T3,T11,T12
StIdle->StPackData	197	Covered	T1,T2,T5
StIdle->StPrePack	195	Covered	T1,T5,T23
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T5
StPackData->StPostPack	218	Covered	T5,T23,T24
StPostPack->StCalcPlainEcc	231	Covered	T5,T23,T24
StPrePack->StPackData	205	Covered	T1,T5,T23
StReqFlash->StIdle	273	Covered	T1,T2,T5
StReqFlash->StWaitFlash	270	Covered	T1,T2,T5
StScrambleData->StCalcEcc	252	Covered	T18,T66,T56
StWaitFlash->StIdle	280	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T23
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T24
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T23,T24
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T11,T18,T66
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T5
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T11,T18,T66
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T11,T18,T66
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T11,T18,T66
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T11,T18,T66
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T18,T66
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T2,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T5
0	0	1	-	-	Covered	T11,T18,T66
0	0	0	1	-	Covered	T11,T18,T66
0	0	0	0	1	Covered	T1,T2,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	393979733	1186544	0	0
PostPackRule_A	393979733	1043	0	0
PrePackRule_A	393979733	715	0	0
WidthCheck_A	1045	1045	0	0
u_state_regs_A	393979733	393077526	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	1186544	0	0
T1	2291	1	0	0
T2	218710	571	0	0
T3	1257	0	0	0
T4	120244	0	0	0
T5	3384	2	0	0
T6	44776	0	0	0
T7	171791	488	0	0
T11	385355	32768	0	0
T12	0	1	0	0
T16	3312	0	0	0
T17	39483	0	0	0
T18	0	170	0	0
T23	0	29	0	0
T24	0	105	0	0
T56	0	599	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	1043	0	0
T5	3384	1	0	0
T7	171791	0	0	0
T11	385355	0	0	0
T12	1017	0	0	0
T17	39483	0	0	0
T18	101013	0	0	0
T23	516939	19	0	0
T24	102556	7	0	0
T25	0	32	0	0
T32	0	5	0	0
T38	63873	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T65	3846	0	0	0
T90	0	2	0	0
T91	0	5	0	0
T106	0	38	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	715	0	0
T1	2291	1	0	0
T2	218710	0	0	0
T3	1257	0	0	0
T4	120244	0	0	0
T5	3384	2	0	0
T6	44776	0	0	0
T7	171791	0	0	0
T11	385355	0	0	0
T16	3312	0	0	0
T17	39483	0	0	0
T23	0	13	0	0
T24	0	4	0	0
T25	0	12	0	0
T32	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T90	0	2	0	0
T106	0	29	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0