Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.48			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.33	100.00	89.30			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.82	100.00	91.27			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	89.30			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.92	97.64	92.75	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.82	100.00	91.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	97.64	93.48	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	100.00	96.23		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	458	419	91.48
Logical	458	419	91.48
Non-Logical	0	0
Event	0	0

 LINE       140
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T25,T193
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T201
1	1	1	Covered	T17,T25,T193

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T148,T202,T203
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T148,T202,T203

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T202,T204,T159
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T202,T204,T159

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T119,T202,T136
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T205
1	1	1	Covered	T119,T202,T136

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (req_o & ack_i & no_match)
             --1--   --2--   ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T57,T124
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T41,T24,T193
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T57,T145,T206
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T41,T24,T88
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Covered	T207,T205
1	1	1	1	1	0	1	Covered	T208
1	1	1	1	1	1	0	Covered	T4,T124,T155
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	1	Covered	T106
1	1	0	1	1	1	1	Covered	T1,T41,T24
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Covered	T160
1	1	1	1	1	1	0	Covered	T2,T57,T124
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T41,T24
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T205,T201
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T2,T4,T20
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T25,T57,T145
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T124,T155
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T57,T124
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T20
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T17
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T21,T57
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T20,T57
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T20
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T65,T66,T67

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       222
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T65,T66,T67

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       222
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T65,T66,T67

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       222
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T65,T66,T67

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       232
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T202,T204,T159
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T53,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T57,T124
1	1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       305
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       382
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T14
1	0	Covered	T14
1	1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T53,T23
1	1	1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T209
1	1	0	1	1	1	Covered	T1,T2,T15
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T1,T2,T3
1	1	1	1	1	0	Covered	T2,T4,T23
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       407
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       428
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T3

 LINE       432
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T57

 LINE       432
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T18

 LINE       442
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T25,T193

 LINE       451
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T20,T25

 LINE       451
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T23,T35
1	0	Covered	T17,T25,T193

 LINE       456
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T23,T35

 LINE       491
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14
1	0	1	Not Covered
1	1	0	Covered	T1,T53,T23
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T15,T16
1	1	0	Covered	T2,T4,T57
1	1	1	Covered	T1,T2,T3

 LINE       497
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T124,T65
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T4,T57

 LINE       501
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T57,T155
1	1	1	Covered	T1,T2,T4

 LINE       503
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       504
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T57

 LINE       505
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       513
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       513
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       513
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T57

 LINE       521
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T57
1	1	Covered	T1,T2,T4

 LINE       521
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T57

 LINE       523
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       597
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T57,T155
1	1	0	Covered	T1,T2,T15
1	1	1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T23
1	1	0	Covered	T2,T4,T57
1	1	1	Covered	T1,T2,T3

 LINE       624
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       624
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       628
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       628
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       636
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       636
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       654
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       654
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       654
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       659
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       659
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T4

 LINE       677
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T205,T201
1	0	Not Covered

 LINE       683
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T20,T25

 LINE       747
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       775
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       775
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       787
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       790
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T165
1	0	Covered	T17,T20,T25

 LINE       790
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T20,T25

 LINE       790
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T193,T202,T204

 LINE       790
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T205,T201

 LINE       794
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T20,T25

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T20,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T20,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	772207962	1590779	0	0
ExclusiveOps_A	772207962	770651850	0	0
ExclusiveProgHazard_A	772207962	770651850	0	0
ExclusiveState_A	772207962	770651850	0	0
ForwardCheck_A	772207962	4200363	0	0
IdleCheck_A	772207962	100612657	0	0
MaxBufs_A	2094	2094	0	0
OneHotAlloc_A	772207962	770651850	0	0
OneHotMatch_A	772207962	770651850	0	0
OneHotRspMatch_A	772207962	770651850	0	0
OneHotUpdate_A	772207962	770651850	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	1590779	0	0
T1	7548	85	0	0
T2	103840	2040	0	0
T3	1990	4	0	0
T4	121186	2961	0	0
T5	0	256	0	0
T15	1162680	0	0	0
T16	238542	12369	0	0
T17	3226	17	0	0
T18	309084	0	0	0
T19	21410	0	0	0
T20	2732	22	0	0
T21	0	28	0	0
T23	0	829	0	0
T25	0	29	0	0
T53	0	17	0	0
T57	0	1497	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	4200363	0	0
T1	7548	89	0	0
T2	103840	19961	0	0
T3	1990	0	0	0
T4	121186	20610	0	0
T5	0	288	0	0
T15	1162680	17006	0	0
T16	238542	30185	0	0
T17	3226	0	0	0
T18	309084	0	0	0
T19	21410	0	0	0
T20	2732	0	0	0
T21	0	54	0	0
T23	0	3219	0	0
T25	0	12	0	0
T29	0	8234	0	0
T53	0	118	0	0
T57	0	44291	0	0
T124	0	22902	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	100612657	0	0
T1	7548	391	0	0
T2	103840	43040	0	0
T3	1990	160	0	0
T4	121186	45525	0	0
T15	1162680	869184	0	0
T16	238542	1553649	0	0
T17	3226	365	0	0
T18	309084	128	0	0
T19	21410	128	0	0
T20	2732	402	0	0
T25	0	20	0	0
T53	0	236	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2094	2094	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772207962	770651850	0	0
T1	7548	7436	0	0
T2	103840	103692	0	0
T3	1990	1884	0	0
T4	121186	120998	0	0
T15	1162680	1162414	0	0
T16	238542	238510	0	0
T17	3226	2856	0	0
T18	309084	308934	0	0
T19	21410	21282	0	0
T20	2732	2432	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	458	409	89.30
Logical	458	409	89.30
Non-Logical	0	0
Event	0	0

 LINE       140
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T51,T115
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T51,T115

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T148,T202,T210
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T148,T202,T210

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T202,T204,T159
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T202,T204,T159

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T119,T202,T204
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T119,T202,T204

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (req_o & ack_i & no_match)
             --1--   --2--   ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T57,T124
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T59,T211,T212
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T57,T82,T33
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T59,T213,T214
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T4,T155,T145
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T59,T213
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T124,T155,T145
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T59,T213
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T2,T4,T124
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T25,T57,T82
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T155,T145
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T124,T155,T145
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T124
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T25,T57,T29
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T29,T124
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T29,T124,T155
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T29
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T65,T66

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T67,T104
0	1	0	Covered	T1,T11,T65
1	0	0	Covered	T65,T66,T71

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T11,T65

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T65,T66
1	1	Covered	T11,T67,T104

 LINE       222
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T65,T66

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T67,T104
0	1	0	Covered	T1,T11,T65
1	0	0	Covered	T65,T66,T71

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T11,T65

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T65,T66
1	1	Covered	T11,T67,T104

 LINE       222
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T65,T66

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T67,T104
0	1	0	Covered	T1,T11,T65
1	0	0	Covered	T65,T66,T71

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T11,T65

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T65,T66
1	1	Covered	T11,T67,T104

 LINE       222
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T65,T66

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T67,T104
0	1	0	Covered	T1,T11,T65
1	0	0	Covered	T65,T66,T71

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T11,T65

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T65,T66
1	1	Covered	T11,T67,T104

 LINE       232
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T202,T204,T159
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T57,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T15,T57,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T57,T29,T124
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       291
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T57,T124
1	1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       305
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       382
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T14
1	0	Covered	T14
1	1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T23,T57
1	1	1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       407
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T209
1	1	0	1	1	1	Covered	T1,T2,T15
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T1,T2,T3
1	1	1	1	1	0	Covered	T2,T4,T23
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       407
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       428
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T15
1	1	Covered	T2,T3,T4

 LINE       432
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T3,T15
1	1	Covered	T2,T4,T57

 LINE       432
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T18

 LINE       442
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T17,T148,T51

 LINE       451
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T23,T36

 LINE       451
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T36,T37
1	0	Covered	T17,T148,T51

 LINE       456
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T23,T36,T37

 LINE       491
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14
1	0	1	Not Covered
1	1	0	Covered	T1,T23,T57
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T15,T16
1	1	0	Covered	T2,T4,T57
1	1	1	Covered	T3,T17,T20

 LINE       497
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T124,T65
1	1	0	Covered	T3,T17,T20
1	1	1	Covered	T2,T4,T57

 LINE       501
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T17,T20
1	1	0	Covered	T57,T155,T145
1	1	1	Covered	T1,T2,T4

 LINE       503
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T17,T20

 LINE       504
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T57

 LINE       505
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T17,T20
1	1	Covered	T1,T2,T4

 LINE       513
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T20

 LINE       513
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T17,T20
1	1	Covered	T3,T17,T20

 LINE       513
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T57

 LINE       521
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T57
1	1	Covered	T1,T2,T4

 LINE       521
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T57

 LINE       523
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T17,T20

 LINE       597
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T57,T155
1	1	0	Covered	T1,T2,T15
1	1	1	Covered	T2,T3,T4

 LINE       598
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T56,T23
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       614
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T23,T57,T155
1	1	0	Covered	T2,T4,T57
1	1	1	Covered	T3,T17,T20

 LINE       624
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       624
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T20

 LINE       628
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       628
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       636
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T20
1	0	Covered	T1,T2,T4

 LINE       636
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T17,T20

 LINE       654
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       654
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T20

 LINE       654
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T17,T20

 LINE       659
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14
1	0	1	Covered	T11,T67,T104
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       659
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T4

 LINE       677
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       683
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T49,T148

 LINE       747
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       775
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       775
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T17,T20

 LINE       787
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       790
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T49,T148

 LINE       790
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T49,T148

 LINE       790
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T3,T17,T20
1	0	0	Covered	T202,T204,T159

 LINE       790
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       794
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T49,T148

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T23,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T17,T20
0	1	Covered	T2,T4,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T3,T17,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T3,T17,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T49,T148
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	386103981	905061	0	0
ExclusiveOps_A	386103981	385325925	0	0
ExclusiveProgHazard_A	386103981	385325925	0	0
ExclusiveState_A	386103981	385325925	0	0
ForwardCheck_A	386103981	1999026	0	0
IdleCheck_A	386103981	48735386	0	0
MaxBufs_A	1047	1047	0	0
OneHotAlloc_A	386103981	385325925	0	0
OneHotMatch_A	386103981	385325925	0	0
OneHotRspMatch_A	386103981	385325925	0	0
OneHotUpdate_A	386103981	385325925	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	905061	0	0
T1	3774	52	0	0
T2	51920	673	0	0
T3	995	3	0	0
T4	60593	1317	0	0
T15	581340	0	0	0
T16	119271	5805	0	0
T17	1613	4	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	7	0	0
T21	0	28	0	0
T23	0	829	0	0
T57	0	1497	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	1999026	0	0
T1	3774	50	0	0
T2	51920	9292	0	0
T3	995	0	0	0
T4	60593	9743	0	0
T15	581340	8747	0	0
T16	119271	14504	0	0
T17	1613	0	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	0	0	0
T21	0	37	0	0
T29	0	8234	0	0
T53	0	118	0	0
T57	0	21944	0	0
T124	0	22902	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	48735386	0	0
T1	3774	152	0	0
T2	51920	19257	0	0
T3	995	19	0	0
T4	60593	20803	0	0
T15	581340	446097	0	0
T16	119271	745509	0	0
T17	1613	40	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	43	0	0
T25	0	20	0	0
T53	0	236	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	458	418	91.27
Logical	458	418	91.27
Non-Logical	0	0
Event	0	0

 LINE       140
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       141
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       146
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T193,T202
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T201
1	1	1	Covered	T25,T193,T202

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T202,T203,T204
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T202,T203,T204

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T202,T204,T159
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T202,T204,T159

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T202,T136,T204
1	0	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T205
1	1	1	Covered	T202,T136,T204

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       154
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       167
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (req_o & ack_i & no_match)
             --1--   --2--   ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T57,T124
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T41,T24,T193
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T145,T206,T82
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       196
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T41,T24,T88
1	1	1	0	1	1	1	Covered	T1,T2,T3
1	1	1	1	0	1	1	Covered	T207,T205
1	1	1	1	1	0	1	Covered	T208
1	1	1	1	1	1	0	Covered	T124,T155,T206
1	1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	1	Covered	T106
1	1	0	1	1	1	1	Covered	T41,T24,T88
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Not Covered
1	1	1	1	1	0	1	Covered	T160
1	1	1	1	1	1	0	Covered	T2,T57,T49
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       196
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T1,T2,T4
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T1,T41,T24
1	1	1	0	1	1	1	Covered	T1,T2,T4
1	1	1	1	0	1	1	Covered	T205,T201
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T20,T145,T33
1	1	1	1	1	1	1	Covered	T1,T2,T4

 LINE       196
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       196
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T145,T206,T82
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T124,T155,T206
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T57,T49
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T145,T33
1	1	1	Covered	T1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T17
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T21,T57,T29
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T20,T57
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T20,T29
1	1	1	Covered	T1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T67,T69,T70

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       222
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T67,T69,T70

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       222
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T67,T69,T70

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       222
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T41,T30

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T41,T11,T30
0	1	0	Covered	T1,T41,T11
1	0	0	Covered	T67,T69,T70

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T41,T11

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T68,T11
1	1	Covered	T41,T11,T30

 LINE       232
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T202,T204,T159
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T16,T53,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       291
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T57,T124
1	1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       305
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       382
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T14
1	0	Covered	T14
1	1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T2,T4,T17
1	1	1	1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T53,T23
1	1	1	Covered	T1,T2,T3

 LINE       399
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T1,T15,T16
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T1,T2,T3
1	1	1	1	1	0	Covered	T2,T4,T23
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       407
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       428
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T3

 LINE       432
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T57

 LINE       432
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T18

 LINE       442
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T193,T202

 LINE       451
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T25,T23

 LINE       451
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T23,T35
1	0	Covered	T25,T193,T202

 LINE       456
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T23,T35

 LINE       491
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14
1	0	1	Not Covered
1	1	0	Covered	T1,T53,T23
1	1	1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T15,T16
1	1	0	Covered	T2,T4,T57
1	1	1	Covered	T1,T2,T3

 LINE       497
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T124,T65
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T4,T57

 LINE       501
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T57,T155
1	1	1	Covered	T1,T2,T4

 LINE       503
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       504
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T57

 LINE       505
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       513
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       513
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       513
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T57

 LINE       521
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T57
1	1	Covered	T1,T2,T4

 LINE       521
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T57

 LINE       523
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       597
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T57,T155
1	1	0	Covered	T1,T2,T15
1	1	1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T23
1	1	0	Covered	T2,T4,T57
1	1	1	Covered	T1,T2,T3

 LINE       624
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       624
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       628
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       628
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       636
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       636
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       654
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       654
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       654
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       659
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       659
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T4

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T4

 LINE       664
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       677
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T205,T201
1	0	Not Covered

 LINE       683
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T25,T68

 LINE       747
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       775
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       775
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       787
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       790
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T165
1	0	Covered	T20,T25,T68

 LINE       790
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T25,T68

 LINE       790
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T193,T202,T204

 LINE       790
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T205,T201

 LINE       794
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T25,T68

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T25,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T25,T68
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	386103981	685718	0	0
ExclusiveOps_A	386103981	385325925	0	0
ExclusiveProgHazard_A	386103981	385325925	0	0
ExclusiveState_A	386103981	385325925	0	0
ForwardCheck_A	386103981	2201337	0	0
IdleCheck_A	386103981	51877271	0	0
MaxBufs_A	1047	1047	0	0
OneHotAlloc_A	386103981	385325925	0	0
OneHotMatch_A	386103981	385325925	0	0
OneHotRspMatch_A	386103981	385325925	0	0
OneHotUpdate_A	386103981	385325925	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	685718	0	0
T1	3774	33	0	0
T2	51920	1367	0	0
T3	995	1	0	0
T4	60593	1644	0	0
T5	0	256	0	0
T15	581340	0	0	0
T16	119271	6564	0	0
T17	1613	13	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	15	0	0
T25	0	29	0	0
T53	0	17	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	2201337	0	0
T1	3774	39	0	0
T2	51920	10669	0	0
T3	995	0	0	0
T4	60593	10867	0	0
T5	0	288	0	0
T15	581340	8259	0	0
T16	119271	15681	0	0
T17	1613	0	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	0	0	0
T21	0	17	0	0
T23	0	3219	0	0
T25	0	12	0	0
T57	0	22347	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	51877271	0	0
T1	3774	239	0	0
T2	51920	23783	0	0
T3	995	141	0	0
T4	60593	24722	0	0
T15	581340	423087	0	0
T16	119271	808140	0	0
T17	1613	325	0	0
T18	154542	128	0	0
T19	10705	128	0	0
T20	1366	359	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0